RU29194U1 - FREQUENCY COMPARATOR - Google Patents

Description

The utility model relates to pulsed technology, and more specifically serves to control the characteristics of a series of pulses.

Frequency comparators are known (see US patent No. 3987365; A.S. No. 504299 class. NOZK 5/18, USSR, published in Bulletin No. 7 for 1976) containing two counters, a memory trigger, and another counter. Compared pulse signals are fed to the inputs of the counters, and the outputs of the counters control a memory trigger. At the output of the counter having a large input frequency, a trigger signal is triggered for the memory trigger; then both counters are reset to the initial state by the output signal of the other counter and the cycle repeats.

The disadvantage of these devices is low accuracy, which is determined by the capacity of N frequency dividers, significant hardware costs when performing frequency comparators.

The closest in technical essence and the achieved result is a frequency comparator (Bespalko V.A. Frequency comparator, Nribor and control systems - 1979, No. 11, p. 30, Fig. 1), containing four D-triggers, the inputs of which are connected to the outputs two sources of input pulse signals, the inverse outputs of the first two triggers are connected to the inputs of the first element AND NOT and the D inputs of the other two

triggers whose direct outputs are connected to the inputs of the second element

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AND-NOT, and the inverted outputs are connected to the S-inputs of the triggers, the output of the first element AND-NOT connected to the S-inputs of the first two triggers, and the output of the second element AND-NOT connected to the R-inputs of the two second triggers.

The disadvantage of this device is the significant time to determine the sign of the frequency difference, which is equal in this device to two periods of the difference frequency; the impossibility of receiving a difference frequency signal in this device. In addition, the device in question is operable only when time-varying pulse sequences of frequencies fl and O are applied to its inputs. These disadvantages do not allow the device to be used effectively in devices and systems designed to work with frequency sensors, and they reduce the speed and accuracy of the devices , systems with frequency sensors, require the use of additional devices to ensure the mismatch of the pulses of frequencies fl and 2.

The technical result, the achievement of which the creation of this utility model is aimed, is to expand the functionality and reduce the time to determine the sign of the frequency difference.

The technical result is achieved in that in a frequency comparator containing four D-flip-flops, the inputs of which are connected to the outputs of two sources of input pulse signals, the first input signal is connected to the D-input of the first trigger and to the C-input of the second-te iiT

th trigger, the second input source is connected to the C-input of the nerve

th trigger and to the D-input of the second trigger, the direct output of the first trigger is connected to the D-input of the third and C-input of the fourth trigger, the direct output of the second trigger is connected to the C-input of the third and to the D-input of the fourth trigger, direct output of the third trigger connected to the R-input of the fourth, and the direct output of the fourth trigger is connected to the R-input of the third, and the direct outputs of the third and fourth triggers are the outputs of the comparator, while the presence of a logical unit on the direct output of the third trigger corresponds to the condition, and the presence of a log unit at the direct output of the fourth trigger corresponds to the condition, where fl, 2 are the frequencies of the input pulses, respectively, from the first and second sources.

The claimed device allows reducing the time of determining the sign of the frequency difference of two pulse sequences to one period of the difference frequency and expanding f) functional possibilities, consisting in the fact that at the outputs of the first and second triggers pulses are generated with a frequency equal to the modulus of the difference of the compared frequencies, when the frequency of the input pulses differ by no more than 30-40%, and the fact that the device is operable even when the pulses arriving at the device inputs coincide in time.

The frequency comparator contains two input pulse sources

signals 1 and 2, the first D-trigger 3, the second D-trigger 4, the third D-trigger 5, the fourth D-trigger 6. The output of the first source of input pulses 1 is connected to the D-input of the first trigger 3 and to the C-input of the second trigger 4; the output of the second source of input pulses 2 is connected to the D-input of the second trigger 4 and to the C-input of the first trigger 3. The direct output of the first trigger 3 is connected to the D-input of the third trigger 5 and to the C-input of the fourth trigger 6; the direct output of the second trigger 4 is connected to the D-input of the fourth trigger 6 and the C-input of the third trigger 5. The direct output of the third trigger 5 is connected to the R-input of the fourth trigger 6, and the direct output of the fourth trigger 6 is connected to the R-input of the third trigger 5 and the direct outputs of the third 5 and fourth 6 triggers are the outputs of the device. Figure 2 shows the timing diagrams of the pulse signals for the inputs (x1, x2) of the device and for the outputs (y1, y2, uz, y4) - triggers 3, 4, 5, 6, respectively.

The device operates as follows. Pa inputs of the first two D triggers 3, 4 receive pulses from 1 and 2 sources of input pulse signals. To analyze the operation, we assume that the frequency fl of the pulse signal of source 1 is greater than the frequency f2 of the pulse signal of source 2. Timing diagrams of the device for this case are shown in the left half of figure 2. In this case, the second trigger 4 is set to O earlier than the first trigger 3, and sets the third trigger 5 to the storage mode of the logic zero, because in the previous clock cycle of the difference-frequency pulse signal existing at the outputs of the first and second triggers,

a logic zero signal was applied to the D input of Third trigger 5. Due to the fact that the frequency of the signal of the first source is greater than the frequency of the signal of the second source, the output of the second trigger 4 produces a logic unity signal earlier than the output of the first trigger 3, i.e. trigger 4 passes from state O to state 1 earlier than trigger 3. This signal is fed to the C-input of the third trigger 5, to the D-input of which a logic zero signal is output from the output of the first trigger 3, while the logical zero signal is rewritten to the input trigger 5. Then, with a certain delay with respect to the time of the transition of trigger 4 from state O to state 1, the transition of trigger 3 from state O to state 1 is performed. The logical unit signal thus generated at the output of trigger 3 is sent to C-input q of the fourth trigger 6, to the D-input of which a signal of a logical unit is supplied from the output of the second trigger 4, while the logical unity is recorded at the output of the fourth trigger 6. This level of logical unit, set at the output of the fourth trigger 6, is fed to the R-input of the third trigger 5, confirming that it is set to zero and thereby performing asynchronous zero setting and further blocking the operation of trigger 5. Analysis of timing diagrams in FIG. 2 shows that in the future, provided the output of the fourth trigger 6 is periodically rewritten, the signal of the logical unit existing at the time of dubbing to D5 iSlUov

inlet of the fourth trigger 6.

When changing the frequency ratio of the input pulses, i.e. when fl becomes less than 0, the relations between the signal durations at the outputs of triggers 3 and 4 change, and there comes a point when a logical unit is formed at the output of the first trigger 3 earlier than at the output of the second trigger 4, and a logical zero is recorded in the same clock cycle the output of the fourth trigger 6, and thereby unlocking the operation of trigger 5. The signal of the logical unit, which then appears at the output of the second trigger 2, writes to the output of the third trigger 5 of the logical unit, which the current presence at the D-input of the third trigger 5. At the same time, the signal of the logical unit from the output of the third trigger 5 goes to the R-input of the fourth trigger 6, thereby performing its asynchronous setting to zero and blocking its further operation. The indicated changes in the states of the outputs of triggers 5, 6 when changing the ratio between the frequencies of the input pulses are carried out in a time not exceeding one period of the difference frequency of the pulse signal, since during this time the order of transitions of triggers 3, 4 from state O to state 1 is changed and the outputs are set accordingly triggers 5, 6 to a state that determines the sign of the frequency difference. When the device is operating, pulse signals of difference frequency are generated at the outputs of triggers 3,4.

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time to determine the sign of the frequency difference and thereby improve performance, the accuracy of the devices with frequency sensors. In addition, the device allows you to receive pulses with a frequency equal to the modulus of the difference of the compared frequencies in the case when the frequencies of the input pulses differ by no more than 30-40%, which significantly expands f) T1functional capabilities of frequency converters, since there is information about the difference frequency module so about her sign. An additional advantage of the proposed device is its operability even when pulses simultaneously arrive at its inputs.

. SH1M

General Director / v / v / X.V. Arkhangelsky

Claims (1)

A frequency comparator containing four D-flip-flops, the inputs of which are connected to the outputs of two sources of input pulse signals, characterized in that the first input signal source is connected to the D-input of the first trigger and to the C-input of the second trigger, the second input source is connected to C -in the input of the first trigger and the D-input of the second trigger, the direct output of the first trigger is connected to the D-input of the third and the C-input of the fourth trigger, the direct output of the second trigger is connected to the C-input of the third and to the D-input of the fourth trigger, direct you the course of the third trigger is connected to the R-input of the fourth, and the direct output of the fourth trigger is connected to the R-input of the third, and the direct outputs of the third and fourth triggers are the outputs of the comparator.