RU2829154C2 - System for transmitting data by orthogonal code sequences and two-stage phase synchronization - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to data transmission means. Disclosed is a data transmission system, which comprises two phase modulators 8, 10, where the output signal modulates the carrier frequency of a harmonic oscillation, and then modulated by pseudorandom sequence generator signal 11, wherein the length of the pseudorandom sequence is equal to n = M, two multipliers 13, 16, phase-locked loop 14, a delay tracking circuit 18 and phase demodulator 15.

EFFECT: high reliability of receiving a radio signal owing to use of code data multiplexing and correlation decoding, two-stage phase modulation of a carrier wave with a multilevel group signal, which enables to realize coherent reception as a whole.

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Description

The invention relates to the field of radio communication technology and can be used in data transmission systems with increased noise immunity due to the use of noise-immune multiplexing by orthogonal binary sequences and their correlation decoding, two-stage phase modulation of the carrier oscillation by a multi-level group signal, making it possible to implement coherent reception of the signal as a whole.

A data transmission system with multiple access and code division multiplexing is known from the prior art, the transmitting side of which consists of: information modulators, the first input of which is connected to the information source, and the second to the carrier frequency generator; multiplier devices, the first input of which is connected to the output of the information modulators, and the second to the output of the code sequence generator; a summing device, the inputs of which are connected to the outputs of the multiplier devices. The receiving side of the transmission system with multiple access and code division multiplexing consists of: a multiplier device, the first input of which is connected to the output of the summing device, and the second to the code sequence generator; an information demodulator, the input of which is connected to the output of the multiplier device [Sklyar, Bernard. Digital Communications. Theoretical Foundations and Practical Application. 2nd ed., corrected: Transl. from English. - M .: Williams Publishing House, 2007. - p. 783].

The disadvantage of this known data transmission device is the absence of a noise-resistant type of modulation of the group signal and the absence of a noise-resistant decoder of the group signal.

The closest known technical solution to the proposed one is a data transmission system using orthogonal codes, consisting of: a summing device, a shaping filter, the input of which is connected to the output of the summing device, a pulse-amplitude modulator, the first input of which is connected to the output of the shaping filter, the second input to the output of the harmonic oscillation generator, and the output is connected to the input of the radio link, a transmitter shift register, M adders modulo two, a generator of orthogonal binary sequences, M polar code generators, a radio signal demodulator, M correlation decoders, a generator of orthogonal binary sequences in a polar code, a receiver shift register, a transmitter shift register, the input of which is connected to the output of a binary data source in a serial code, summers modulo two, the first inputs of which are connected to the outputs of the transmitter shift register, the second inputs to the outputs of the generator of orthogonal binary sequences, M polar code generators, the inputs of which are connected to the outputs of the adders modulo two, and the outputs to the inputs of the adder, a radio signal demodulator, the input of which is connected to the output of the radio line, M correlation decoders, the first inputs of which are connected to the outputs of the signal demodulator, the second inputs to the outputs of the generator of orthogonal binary sequences in the polar code, a receiver shift register, the inputs of which are connected to the outputs of the correlation decoders, and the output to the input of the data receiver [patent RU 2714606, 2020].

The disadvantage of the prototype is that the amplitude-pulse modulation used has low noise immunity, since it does not allow for the implementation of coherent reception of the signal as a whole and does not ensure clock self-synchronization of the received signal.

The technical task of the invention is to increase the noise immunity of a data transmission system, reduce the probability of a bit error P _b with a fixed signal-to-noise ratio per bit h _b ² = const, and also ensure clock self-synchronization of the receiving signal.

The technical result of the invention consists in increasing the reliability of radio signal reception by using phase modulation of the carrier by a group multi-level signal and a pseudo-random n=M-bit sequence, which makes it possible to implement coherent reception of a group signal and clock self-synchronization of the received signal on the receiving side.

The essence of the invention lies in the fact that in addition to the known elements of the system, namely: a summing device, a shaping filter, the input of which is connected to the output of the summing device, a pulse-amplitude modulator, the first input of which is connected to the output of the shaping filter, the second input - to the output of the harmonic oscillation generator, and the output is connected to the input of the radio line, a transmitter shift register, M adders modulo two, a generator of orthogonal binary sequences, M polar code generators, a radio signal demodulator, M correlation decoders, a generator of orthogonal binary sequences in a polar code, a receiver shift register, a transmitter shift register, the input of which is connected to the output of a binary data source in a serial code, modulo two adders, the first inputs of which are connected to the outputs of the transmitter shift register, the second inputs - to the outputs of the generator of orthogonal binary sequences, M polar code formers, the inputs of which are connected to the outputs of the adders modulo two, and the outputs to the inputs of the adder, a radio signal demodulator, the input of which is connected to the output of the radio link, M correlation decoders, the first inputs of which are connected to the outputs of the signal demodulator, the second inputs to the outputs of the former of orthogonal binary sequences in the polar code, a receiver shift register, the inputs of which are connected to the outputs of the correlation decoders, and the output to the input of the data receiver, into it are introduced: on the transmitting side - two phase modulators, a transmitter pseudo-random sequence generator, a clock pulse generator, wherein the first input of the first phase modulator is connected to the output of the shaping filter, and the second input to the output of the harmonic oscillation generator, the first input of the second phase modulator is connected to the output of the first phase modulator, and the second input to the output of the pseudo-random sequence generator, the outputs of the clock pulse generator are connected with the second input of the transmitter shift register, with the input of the binary sequence orthogonal signal generator and with the input of the transmitter pseudo-random sequence generator, the output of the second phase modulator is connected to the input of the radio line; on the receiving side - two multipliers, a phase-locked loop unit, a phase demodulator, a receiver pseudo-random sequence generator, a delay tracking circuit, a clock pulse generator, wherein the first inputs of the first and second multipliers are connected to the output of the radio link, the input of the phase-locked loop unit is connected to the output of the first multiplier, the first input of the phase demodulator is connected to the output of the phase-locked loop unit, and the second input is connected to the output of the first multiplier, the output of the phase-locked loop unit is connected to the second input of the second multiplier, the output of the receiver pseudo-random sequence generator is connected to the second input of the first multiplier and to the second input of the delay tracking circuit, the first input of which is connected to the output of the second multiplier, the input of the clock pulse generator is connected to the output of the delay tracking circuit, and the output is connected to the output of the pseudo-random sequence generator, the input of the generator of orthogonal binary sequences in a polar code and M+1 is the input of the receiver shift register.

Fig. 1 shows a structural diagram of a data transmission system using orthogonal codes and two-stage phase modulation of a signal; Fig. 2 shows a table of probability dependencies P _b =ƒ(h _b ² ).

In the structural diagram of the data transmission system using orthogonal codes and two-stage phase modulation of the signal, shown in Fig. 1, the following designations are introduced:

1 - M-bit transmitter shift register;

2 - M adders modulo two;

3 - generator of orthogonal binary M-bit sequences in binary code;

4 - M polar code generators;

5 - clock pulse generator;

6 - summing device;

7 - shaping filter;

8 - first phase modulator;

9 - harmonic oscillation generator;

10 - second phase modulator;

11 - generator of n=M-bit pseudo-random sequence of the transmitter;

12 - radio line;

13 - first multiplier;

14 - phase-locked loop block;

15 - phase demodulator;

16 - second multiplier;

17 - generator of n=M-bit binary pseudo-random sequence of the receiver;

18 - pseudo-random sequence delay monitoring circuit;

19 - controlled clock pulse generator;

20 - M correlation decoders;

21 - generator of orthogonal binary M-bit sequences in binary code;

22 - M-bit receiver shift register.

In this case, on the transmitting side, the first input of the M-bit shift register of the transmitter 1 is connected to the output of the binary data source in serial code, and the second input is connected to the output of the clock pulse generator 5, the first inputs of the modulo two adders are connected to the outputs of the shift register of the transmitter, and the second inputs are connected to the outputs of the orthogonal binary sequences 3, the input of which is connected to the output of the clock pulse generator. The outputs of the adders modulo two are connected to the inputs of the M polar code generators 4, the outputs of which are connected to the inputs of the adder 6, the output of which is connected to the first input of the first phase modulator 8, the second input of which is connected to the output of the harmonic oscillation generator 9. The output of the first phase modulator is connected to the first input of the second phase modulator 10, the second input of which is connected to the output of the pseudo-random sequence generator of the transmitter 11, the input of which is connected to the output of the clock pulse generator, and the output of the second phase modulator is connected to the input of the radio line 12.

On the receiving side, the output of the radio line is connected to the first input of the first multiplier 13, the output of which is connected to the input of the phase-locked loop block 14, the output of which is connected to the first input of the phase demodulator of the group multilevel signal 15, the second input of which is connected to the output of the first multiplier, and the second input of the multiplier 16, the first input of which is connected to the output of the radio line. The output of the second multiplier is connected to the first input of the delay tracking circuit 18, the second input of which is connected to the output of the controlled clock pulse generator 19, the input of which is connected to the output of the delay tracking circuit. The output of the phase demodulator is connected to the first inputs of M correlation decoders 20, the second inputs of which are connected to M outputs of the generator of orthogonal M-bit binary sequences in polar code 21, and the outputs of which are connected by a parallel binary code to M inputs of the M-bit shift register of the receiver 22, the M+1 input of which is connected to the output of the controlled clock pulse generator of the receiver, and the output of the shift register of the receiver is connected by a serial binary code to the data receiver. The transmitter clock pulse generator, the multiplier, the phase-locked loop unit, the pseudo-random sequence generator, the pseudo-random sequence delay tracking circuit, the controlled clock pulse generator are presented in the well-known scientific literature [Tuzov G.I., Sivov V.A., Prytkov V.I. - M.: Radio and Communications, 1985, p. 126, Fig. 4.11].

The system of data transmission by orthogonal code sequences and two-stage phase modulation of the signal operates as follows. Binary data on the transmitting side from the output of the source in serial code under the action of clock pulses of generator 5 are fed to the input of the M-bit shift register of the transmitter 1, which converts the serial binary code into a parallel one. The parallel binary code from the output of the shift register of the transmitter is fed to the first inputs of M adders modulo two 2, to the second inputs of which orthogonal binary sequences are fed, which are generated in the generator of orthogonal binary sequences 3. The output symbols of the M adders modulo two are fed to the inputs of M polar code generators 4, which convert the unipolar binary code into the polar code {1; - 1}, the symbols of which are fed to M inputs of the adder 6. The multilevel group signal from the output of the adder is fed to the input of the shaping filter 7, from the output of which it is fed to the first input of the first phase modulator 8, where it modulates the carrier of the harmonic signal, which is formed in the generator 9. The output signal of the first phase modulator is fed to the first input of the second phase modulator 10, where it is modulated by the output signal of the pseudo-random sequence generator 11, which is formed under the action of the clock pulses of the generator 5, the output signal of the second phase modulator is fed to the input of the radio line 12.

On the receiving side, the output signal of the radio link 12 is fed to the first input of the first multiplier 13, from the output of which it is fed to the input of the phase-locked loop block 14 and to the first input of the phase demodulator 15, to the second input of which the output signal of the phase-locked loop block is fed. At the output of the phase demodulator, the received multilevel group signal with possible distortions is formed. To ensure clock self-synchronization, the received signal is fed to the first input of the second multiplier 16, to the second input of which the output signal of the phase-locked loop block is fed, and the output signal of the second multiplier is fed to the first input of the delay tracking circuit 18, to the second input of which the output signal of the pseudo-random sequence generator of the receiver 17 is fed, which simultaneously is fed to the second input of the first multiplier.

As a result of such interaction of the structural elements of the receiving path, a harmonic signal modulated in phase by a multilevel group signal is formed at the output of the first multiplier, and a mismatch signal proportional to the time delay between the received pseudo-random sequence at the output of the second multiplier and the local n=M-bit pseudo-random sequence formed by the pseudo-random sequence generator of the receiver is formed at the output of the delay tracking circuit. The output signal of the delay tracking circuit controls the clock frequency of the controlled clock pulse generator of the receiver 19, which ensures clock self-synchronization of the received signal. The output signal of the phase demodulator is fed to the first inputs of M correlation decoders 20, to the second inputs of which copies of binary orthogonal sequences in polar code are fed from the outputs of the generator of orthogonal binary sequences in polar code 21. The generator of orthogonal binary sequences in polar code operates under the action of clock pulses fed from the output of the controlled clock pulse generator of the receiver. The outputs of M correlation decoders produce binary symbols in parallel code to M inputs of the shift register of the receiver 22, to the M+1 input of which clock pulses are fed from the output of the controlled clock pulse generator of the receiver, the output symbols of the shift register of the receiver are fed to the data recipient.

The technical feasibility of the invention is substantiated by the fact that it uses devices whose technical implementation, according to their direct functional purpose, is known in the analogue and in the prototype. In 2020, the applicant's organization manufactured a device implementing the declared data transmission system.

The achieved declared technical result, namely, a reduction in the probability of a bit error in the received message at the output of shift register 22, is obtained by using noise-resistant multiplexing with orthogonal binary sequences and their correlation decoding, two-stage phase modulation of the carrier oscillation with a multi-level group signal, making it possible to implement coherent reception of the signal as a whole.

The probability of a bit error in a received message was determined in a computer experiment.

The probability of a bit error from the proposed data transmission system is determined by the expression [Borisov V.I., Zincuk V.M. et al. Noise immunity of radio communication systems with spread spectrum direct modulation of a pseudo-random sequence - M.: RadioSoft, 2011, p. 84]

The positive effect of increasing the noise immunity of the data transmission system from using the invention is presented in the table in Fig. 2.

The table in Fig. 2 shows the values of the bit error probability P _b depending on the signal-to-noise ratio per bit h _b ² of the prototype and the proposed data transmission system for fixed values of M.

The positive effect from using the invention increases with increasing M=n and at M=n=16 the probability P _b decreases by at least two decimal orders compared to the prototype. The said positive effect is achieved due to the coherent reception of the phase-shift keyed signal as a whole, which is impossible to implement in the prototype with an amplitude-modulated signal.

Claims (1)

A data transmission system using orthogonal code sequences and two-stage phase modulation of a signal, consisting of a transmitter shift register, the input of which is connected to the output of a binary data source in a serial code, M adders modulo two, the first inputs of which are connected to the outputs of the transmitter shift register, an orthogonal binary sequence generator, M polar code formers, the inputs of which are connected to the outputs of the modulo two adders, a summing device, the inputs of which are connected to the outputs of the M polar code formers, M correlation decoders, a receiver shift register, the inputs of which are connected to the outputs of the correlation decoders, characterized in that the following are introduced into it: on the transmitting side - two phase modulators, a transmitter pseudo-random sequence generator, a clock pulse generator, wherein the first input of the first phase modulator is connected to the output of the shaping filter, and the second input to the output of the harmonic oscillation generator, the first input of the second the phase modulator is connected to the output of the first phase modulator, and the second input to the output of the pseudo-random sequence generator, the outputs of the clock pulse generator are connected: to the second input of the transmitter shift register, to the input of the binary sequence orthogonal signal generator and to the input of the transmitter pseudo-random sequence generator, the output of the second phase modulator is connected to the input of the radio line; on the receiving side - two multipliers, a phase-locked loop unit, a phase demodulator, a receiver pseudo-random sequence generator, a delay tracking circuit, a clock pulse generator, wherein the first inputs of the first and second multipliers are connected to the output of the radio link, the input of the phase-locked loop unit is connected to the output of the first multiplier, the first input of the phase demodulator is connected to the output of the phase-locked loop unit, and the second input is connected to the output of the first multiplier, the output of the phase-locked loop unit is connected to the second input of the second multiplier, the output of the receiver pseudo-random sequence generator is connected to the second input of the first multiplier and to the second input of the delay tracking circuit, the first input of which is connected to the output of the second multiplier, the input of the clock pulse generator is connected to the output of the delay tracking circuit, and the output is connected to the input of the pseudo-random sequence generator, the input of the generator of orthogonal binary sequences in a polar code and M+1 is the input of the receiver shift register.

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