RU2817624C1 - Delaying cache state updates in non-speculative cache memory in processor system in response to speculative data request until speculative data request becomes non-speculative - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to methods of managing cache memory of a computer system. Technical result is achieved due to the fact that the cache controller is configured to: select a SAR record in the SAR scheme, wherein the SAR record contains the instruction ID and the main data set; and in response to the fact that the received instruction ID in the fixation indicator indicates that the data request loading instruction is non-speculative, determine whether or not the received instruction ID is contained in the instruction ID entry in the SAR entry in the SAR scheme; and in response to determining that the received instruction ID is contained in the SAR record in the SAR scheme, updating the cache replacement state of the cache entry proper in the main data array corresponding to said index in the main data array entry associated with the target address of the data request in the SAR entry containing the received instruction ID.

EFFECT: faster operation of the system by reducing the occupied cache memory.

14 cl, 13 dwg

Description

Field of technology to which the invention relates

[0001] The technology of the disclosure relates to processor systems using a central processing unit (CPU), also known as a "processor", and more particularly, to a cache memory in a processor system used to store or "cache" copies of information in the main memory for faster access via the processor.

State of the art

[0002] A central processing unit (CPU), also known as a “processor,” performs computing tasks for a wide variety of applications. A traditional processor includes one or more processor cores, also known as "CPU cores". The processor executes computer program instructions (“instructions”), also known as “soft instructions,” which are obtained by fetching instructions from memory. The processor executes fetched instructions from memory to perform operations based on the type of instructions and data operands and produces a result. The result may be provided as input, which must be consumed through another instruction and/or stored in data memory as data. The instruction memory and data memory may be provided in main memory as part of a processor system that includes a processor. Instruction memory and data memory may also be provided in the form of cache memory. For example, a data cache includes or "caches" smaller copies of data stored in main memory to provide the processor with faster access to the data. A cache memory system includes one or more cache memories organized in a hierarchy between the processor and main memory. Data migrates between main memory and various cache levels based on cache hits and cache misses. If the processor requests data that is not stored in any of the cache levels (i.e., a cache miss), the data is fetched from main memory and stored in the cache levels. If a subsequent request for identical data is made that results in a cache hit (that is, the data is requested before the data is evicted from the cache levels), the data is provided from the cache to the processor, as opposed to having to refetch the data from main memory.

[0003] Data retrieved from the high-level cache or main memory as a result of a cache miss in the low-level cache is temporarily stored in a dedicated structure known as a fill buffer in the low-level cache. The padding buffer is also known as the Failed Status Hold Register (MSHR). The cache fill buffer acts as a staging area for incoming data, which must be retained in the cache until a cache entry in the cache becomes available to store the incoming data. The cache must evict an existing cache entry in the cache data array based on an eviction policy, such as the most recently used principle, in order to free up space for new incoming data as a result of a cache miss. A low-level cache miss may result in a data request (i.e., a read request) to the next high-level cache that has the requested data stored in the data array or still stored in the padding buffer before being stored in cache data array. In either case, the requested data contained in the fill buffer or data array of the high-level cache may be provided to the low-level cache in response to a request for data from the low-level cache. The cache can store incoming data in its fill buffer and not store data in its data array until the fill buffer becomes full, since incoming data requests can be satisfied from the fill buffer as well as the data array.

[0004] A processor may use instruction pipelining as a processing technology, whereby the throughput of executing computer instructions can be increased by breaking the processing of each instruction into a sequence of steps. These steps are executed in a command execution pipeline consisting of several stages. However, structural hazards can occur in the instruction processing pipeline when the next instruction cannot be executed without causing incorrect computation results. For example, a control hazard may result from the execution of a control flow instruction that causes a precise interrupt in the processor. One example of a control flow instruction that can cause a control hazard is a conditional branch instruction. A conditional branch instruction can redirect the instruction flow path based on an evaluated condition when the condition of the control branch instruction is satisfied. One approach for maximizing processor performance involves using a prediction circuit to speculatively predict the outcome of a conditional branch instruction before executing it. Thus, low-order instructions that match the predicted conditional branch instruction flow path can be fetched and also processed in the instruction processing pipeline instead of stalling until the branch condition is resolved when the conditional branch instruction is executed. When the conditional branch instruction finally reaches the execution stage of the instruction processing pipeline and is executed, the resulting target address of the conditional branch instruction is verified by comparing it with the previously predicted target addresses when the conditional branch instruction was fetched. If the predicted and actual target addresses are the same, meaning that the correct prediction is made, no delay is caused during instruction execution because subsequent instructions at the target address are correctly fetched and are already present in the instruction processing pipeline when the conditional branch instruction reaches the execution stage of the processing pipeline instructions. However, if the predicted and actual target addresses do not match, a mispredicted branch hazard occurs in the instruction processing pipeline, which causes a precise interrupt. As a result, a misprediction recovery process is performed whereby the low-order instructions relative to the conditional branch instruction in the instruction processing pipeline are reset, and the instruction processing pipeline fetch unit is redirected to be able to fetch new instructions starting from the target address, resulting in latency and reduced productivity.

[0005] Even if recovery from a misprediction involves flushing the minor instructions relative to the conditional branch instruction in the incorrectly predicted flow path and then fetching and processing instructions for the instructions in the correct flow path, processing the minor instructions in the incorrect flow path may still result in sending data to the cache as a result of cache misses. This may cause a security problem in the form of leaks. For example, a malicious attack process running on a processor may include code that loads a large amount of data from memory, causing the shared cache to be filled with that data to prime the cache. The attacking process can also prepare a branch prediction circuit to force the execution of an incorrect speculative prediction of a conditional branch instruction in a later-executing victim process at a later time. Load instructions in an invalid speculated thread path under a conditional branch instruction in the victim process instruct the processor to load data into the cache, even if those load instructions are subsequently cleared when the conditional branch instruction is executed and its condition is resolved. This instructs some data in the cache prepared by the attacking process to be evicted from the cache via load instructions in the invalid thread path in the victim process. When the attacking process executes again after the victim process switches, the attacking process can determine which of its prepared data is evicted from the cache. This information can provide information regarding the data addresses accessed by the victim process.

[0006] The above security problem may be resolved by providing unused speculative buffer(s) outside the shared cache to store loaded data from processing speculatively processed load instructions. Speculatively loaded data into a speculative buffer from processing a speculatively processed load instruction may still be provided to consuming instructions depending on the speculatively processed load instruction. When a load instruction that instructs data to be speculatively loaded into the speculative buffer is executed and becomes non-speculative, if the speculative prediction is correct, the speculative request may be re-issued non-speculatively. If the speculative prediction is incorrect, the speculative data request is not reissued, thereby preventing the speculatively loaded data from being installed in the cache. Thus, data is not loaded into the cache as a result of incorrectly speculated load instructions. However, twice as many (2X) data requests must be issued in order to load the data into the processor, which is inefficient.

The essence of the invention

[0007] Aspects disclosed herein include deferring updates to cache states in a non-speculative cache memory in a processor system in response to a speculative data request until the speculative data request becomes non-speculative. The processor system includes a processor, which may include one or more processor cores that execute computer program instructions to perform operations based on downloaded data stored in main memory. The processor system also includes a cache system that includes one or more private and/or shared cache memories organized in a hierarchy between the processor and main memory. Each cache has a cache eviction policy that governs what data in its cache entries should be evicted to the high-level cache or main memory to free up space for storing new data requests (i.e., load/load requests). reading). Load-based instructions (“load instructions”), which are speculatively processed by the processor as a result of speculatively predicting the condition of a conditional flow control instruction (eg, a conditional branch instruction), instruct data requests to be made to the cache system. However, if the condition of a conditional flow control instruction is determined to be mispredicted during execution, speculatively processed load-based instructions may be discarded. However, previous data requests to the cache system resulting from processing speculative load-based instructions that are no longer valid are executed to the cache system. If such data requests are allowed to instruct the eviction of other cache data in the cache system, this can cause cache pollution. This may also cause security issues. For example, a malicious attacking process may discern information regarding data accessed by a victim process based on incorrect speculative data loaded into the cache system. A malicious attacking process could prime the cache system with its own data and prepare the control prediction circuitry to perform erroneous predictions on conditional flow control instructions in the victim process, causing incorrect speculative data to be loaded into the cache system. The attacking application can discern information regarding the victim process based on which of the prepared data in the cache system is replaced by incorrect speculative data to be loaded into the cache system.

[0008] In this regard, in exemplary aspects disclosed herein, at least one cache state in the cache memory is deferred with respect to an update in the cache memory in response to a received data request until the data request becomes non-speculative . Thus, the cache is not updated based on a data request resulting from a misprediction, which should not be issued if a misprediction occurs, and thus the cache is a non-speculative cache. In this way, cache pollution can be reduced. As another example, an attacking process is prevented from obtaining information regarding data accesses by a victim process running on the processor by seeding mispredictions in a control prediction circuit that instructs data requests to be issued by the victim process, resulting in speculatively modified cache states. in cache memory. If data requests that are not resolved as non-speculative may change the cache state in the cache memory, the attacking application can gain insight into the data accesses by the victim process by understanding the changed cache states in the cache memory.

[0009] In one exemplary aspect, deferring a cache state update in a cache memory is provided by not storing the initially received speculative request data in a cache entry in the main cache data body received from high-level memory as a result of a cache miss. Instead, the received speculative request data is first stored in the speculative buffer memory, i.e. not in the main cache data. For example, a speculative buffer memory may be a fill buffer circuit in a cache memory that acts as a staging area for requested data that must be retained until a cache entry in the main cache data array becomes available in order for save incoming data. Speculative query data stored in speculative buffer memory is stored into an accessible cache entry in the main cache data array if the load instruction that results in the requested data query becomes non-speculative. A new data request need not be issued by the processor to the cache memory system to cause the speculative request data stored in the speculative buffer memory to be stored in a cache entry in the cache memory in response to the data request becoming non-speculative.

[0010] In another exemplary aspect, when a data request issued from the processor to a cache memory in a cache memory system is contained in a cache entry in the main cache memory data array, a cache hit results. Since the speculative request data is already contained in the cache entry of the main cache data, the speculative request data in the hit cache entry in the main cache data is returned to the requester in the processor. However, updating the state of the replacement cache for a cache entry in the main data set containing the speculative query data may be delayed until the load instruction that initiates the data query for the data becomes non-speculative. Thus, for example, the replacement policy for the main cache data body should not be executed based on the state of the replacement cache, which is modified to write the main data body cache containing the speculative requested data as the result of the data request, in case the data request is flushed to as a result of erroneous forecasting.

[0011] In another exemplary aspect, if a data request issued from the processor to a cache memory is not contained in the main data array but is contained in a speculative buffer memory associated with the cache memory, the speculative request data in the speculative buffer memory is also returned to requester in the processor as a successful cache hit. The update of the cache state for speculative request data is delayed by not writing the speculative request data to a cache entry in the main cache data until the data request becomes non-speculative. Additionally, by way of example, updating the state of a replacement cache for speculative data requests is automatically deferred until a new data request for identical data results in a cache hit in the main cache data body, as explained above.

[0012] In this regard, in one exemplary aspect, a non-speculative cache memory is provided in a processor system. The non-speculative cache memory includes a main body of data containing a plurality of cache entries, each of which is configured to store data cache data associated with a memory address in a memory system of the processor system. The non-speculative cache memory also includes a speculative buffer memory comprising a plurality of buffer entries, each of which contains a data record configured to store cached data associated with a memory address in a memory system. The non-speculative cache memory also includes a cache controller configured to receive from a requester a data request containing a target address and an instruction identification (ID) identifying a load instruction containing the target address processed by a processor in the processor system. The cache controller is also configured to search for a cache entry in the main data array associated with the target address of the data request. The cache controller is also configured to search the speculative buffer memory for a buffer entry associated with a data request target address. The cache controller is also configured to send to the requester a data response to a data request based on cache data in the main data array associated with the target address and cache data in a buffer entry in the speculative buffer memory associated with the target address. The cache controller is also configured to receive a commit indicator containing the instruction ID of the instruction itself, which is non-speculative. The cache controller is also configured, in response to receiving an instruction ID in the latch indicator indicating that the data request load instruction is non-speculative, to update the cache state for a cache entry in the main data array associated with the data request target address.

[0013] In another exemplary aspect, a method for updating cache state in a non-speculative cache memory on a processor system is provided. The method comprises receiving from a requester a data request containing a target address and an instruction ID identifying a load instruction containing the target address processed by a processor in the processor system. The method also includes searching the main body of data for a cache entry associated with a target data request address from a plurality of cache entries, each of which is configured to store cache data associated with the memory address in a memory system of the processor system. The method also includes searching the speculative buffer memory for a buffer entry associated with a target data request address from a plurality of cache entries, each of which is configured to store cache data associated with the memory address in a memory system. The method also includes sending to the requester a data response to a data request based on a cache entry in the main data array associated with the target address and cache data in a buffer entry in the speculative buffer memory associated with the target address. The method also includes receiving a commit indicator containing the instruction ID of the instruction itself, which is non-speculative. The method also includes updating a cache state for a cache entry in the main data array associated with a data request target address in response to a received instruction ID in a commit indicator indicating that the data request load instruction is non-speculative.

[0014] Those skilled in the art should appreciate the scope of the present disclosure and implement the additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings.

Brief description of drawings

[0015] The accompanying drawings, incorporated in and forming a part of this detailed description, illustrate several aspects of the disclosure and, along with the description, serve to explain the principles of the disclosure.

[0016] FIG. 1 is a diagram of an exemplary processor system that includes a processor configured to issue memory allocation requests (i.e., data read requests and data write requests) to a memory system that includes a cache memory system and main memory wherein the at least one cache memory in the cache memory system is configured to delay updating a cache state in response to receiving a data request from the processor until the data request becomes non-speculative;

[0017] FIG. 2 is a diagram of an example instruction processing circuit that may be included in the processor of FIG. 1, and which includes one or more instruction processing pipelines for processing computer instructions for execution, wherein the instruction processing circuit includes a control flow prediction circuit configured to speculatively predict the conditions of conditional flow control instructions sampled and processed by the circuit processing instructions;

[0018] FIG. 3 is a diagram of an exemplary non-speculative cache in the cache system of FIG. 1;

[0019] FIG. 4 is a flowchart illustrating an exemplary backoff process by a cache controller in the cache memory of FIG. 3, updating a data cache state for a received data request that is speculative, and updating a deferred cache state in the main data body for data associated with the data request in response to the data request becoming non-speculative;

[0020] FIG. 5A illustrates output by the processor of FIG. 1, a data request to the cache memory system resulting in a cache hit in the main cache data array, wherein the cache memory cache controller allocates a speculative access registration (SAR) entry associated with a load instruction processed by the processor , which generates a data request to register the deferral of cache state updates for a cache entry in the main data array storing the speculative requested data;

[0021] FIG. 5B illustrates reception via the cache of FIG. 3, a non-speculative indicator from the processor indicating that a load instruction processed by the processor becomes non-speculative, and accessing, by a cache controller in the cache memory, a registered cache state update backoff associated with the load instruction that becomes non-speculative thereby that the cache state for the cache entry in the main data array storing the speculative query data is updated;

[0022] FIG. 6A illustrates output by the processor of FIG. 1, a data request to a cache system resulting in a cache miss in the main cache data array, and an entry allocated in a speculative access record (SAR) circuit configured to store an index associated with an instruction associated with the request. data, in a buffer entry in a speculative buffer memory allocated to store cache data for a data request, so as to register deferral of updates of cache states for a data request;

[0023] FIG. 6B illustrates reception via the cache memory of FIG. 3, a non-speculative indicator from the processor indicating that a load instruction processed by the processor becomes non-speculative, and in response, accessing, by a cache controller in the cache memory, a registered cache state update backoff associated with the load instruction in the speculative buffer a memory indexed by an entry in a SAR circuit associated with an instruction associated with a data request to update a cache state for a cache entry in a main data array storing the requested data;

[0024] FIG. 7A-7D illustrate an example of output by the processor of FIG. 1, data requests to a cache memory system resulting in cache hits and cache misses in the main cache data body, and exemplary cache state update deferral processing for cache data in the main data body associated with the data requests, by using a SAR circuit configured to index a virtual fill buffer circuit, and a virtual fill buffer circuit configured to index a speculative buffer memory so as to register a delayed update of a cache state for use in updating a cache state associated with data requests thereafter how they become non-speculative; And

[0025] FIG. 8 is a block diagram of an exemplary processor system including a processor configured to issue memory allocation requests to a memory system that includes a cache memory system and a main memory, wherein the cache memory system includes at least one cache memory, including, but not limited to, the cache memory in FIG. 1, 3, 5A-5B, 6A-6B, and 7A-7D, configured to delay updating a cache state in response to receiving a data request from the processor until the data request becomes non-speculative.

Detailed Description of the Invention

[0026] Aspects disclosed herein include deferring updates to cache states in a non-speculative cache memory in a processor system in response to a speculative data request until the speculative data request becomes non-speculative. The processor system includes a processor, which may include one or more processor cores that execute computer program instructions to perform operations based on downloaded data stored in main memory. The processor system also includes a cache system that includes one or more private and/or shared cache memories organized in a hierarchy between the processor and main memory. Each cache has a cache eviction policy that governs what data in its cache entries should be evicted to the high-level cache or main memory to free up space for storing new data requests (i.e., load/load requests). reading). Load-based instructions (“load instructions”), which are speculatively processed by the processor as a result of speculatively predicting the condition of a conditional flow control instruction (eg, a conditional branch instruction), instruct data requests to be made to the cache system. In exemplary aspects disclosed herein, at least one cache state in the cache memory is delayed with respect to an update in the cache memory in response to a received data request until the data request becomes non-speculative. Thus, the cache is not updated based on a data request resulting from a misprediction, which should not be issued if a misprediction occurs, and thus the cache is a non-speculative cache.

[0027] Thus, cache pollution can be reduced. As another example, an attacking process is prevented from obtaining information regarding data accesses by a victim process running on the processor by seeding mispredictions in a control prediction circuit that instructs data requests to be issued by the victim process, resulting in speculatively modified cache states. to cache memory. If data requests that are not resolved as non-speculative may change the cache state in the cache memory, the attacking application can gain insight into the data accesses by the victim process by understanding the changed cache states in the cache memory.

[0028] FIG. 1 is a diagram of an exemplary processor system 100 that includes a central processing unit (CPU) or processor 102 configured to issue memory allocation requests (i.e., data read requests and data write requests) to a memory system 104 that includes includes a cache memory system 106 and a main memory 108. For example, the main memory 108 may be dynamic random access memory (DRAM) provided on a separate DRAM chip. Processor 102 includes one or more corresponding CPU cores 110(1)-110(N), wherein "N" is a positive integer representing the number of CPU cores included in processor 102. Processor 102 may be packaged within chip 112 with integrated circuits (IC). The cache system 106 includes one or more caches 114(1)-114(X), which may have different hierarchies in the processor system 100, that are logically located between the CPU cores 110(1)-110(N) and main memory 108, where "X" is a positive integer representing the number of CPU cores included in processor 102. The cache memories store or cache a subset of data contained in main memory 108 to provide for CPU cores 110(1) -110(N) faster access to data in main memory 108 to perform data queries. Memory controller 116 controls access to main memory 108.

[0029] For example, the CPU core 110(1)-110(N) as a requesting device may issue a data request 118 to read data in response to load instruction processing. Data request 118 includes a target address of data to be read from memory. The data request 118 may also include an instruction ID identifying an instruction that instructs the CPU core 110(1)-110(N) to issue the data request 118. Using CPU core 110(1) as an example, if the requested data is not in the closed cache 114(1) (i.e., cache 114(1) misses), which may be considered a cache miss first level (L1) cache 114(1) sends a data request 118 over interconnect bus 117 in this example to shared cache 114(X) shared by all CPU cores 110(1)-110(N ), which may be a third-level cache (3). Other shared caches 114(2), 114(3) with processor 102 that are shared only with a subset of CPU cores 110(1)-110(N) may also be considered L2 caches (2). The requested data is ultimately obtained in either cache 114(1)-114(X) or main memory 108 if not contained in either cache 114(1)-114(X). Data received by the cache memory 114(1)-114(X) from the high-level cache memory 114(1)-114(X) or the main memory 108 due to a cache miss instructs the receiving cache memory 114(1)- 114(N) evict cache data into high-level memory to free up space for new cache data. Each cache memory 114(1)-114(X) has a cache replacement policy that controls which of its cache data should be evicted to the high-level cache memory 114(1)-114(X) or to main memory 108 so that free up space to store new cache data for a data request 118 that results in a cache miss.

[0030] FIG. 2 illustrates an instruction processing circuit 200 that is provided in a CPU core 110, which may be any of the CPU cores 110(1)-110(N) in the processor 102 in FIG. 1. The instruction processing circuit 200 includes one or more I pipelines₀-I_N instruction processing for processing sampled computer instructions 202F sampled by instruction sampling circuit 204 for execution from a sequence of instructions 202 stored in instruction cache 206 or instruction memory 208, as examples. Instruction cache 206 may be provided as part of cache 114(1)-114(X) in cache system 106 in processor system 100 in FIG. 1. Instruction memory 208 may be provided in or as part of main memory 108 in the processor system 100 of FIG. 1. The instruction fetch circuit 204 is configured to provide fetched instructions 202F to one or more I pipelines₀-I_N processing instructions as an instruction flow 210 in the instruction processing circuit 200 for preprocessing, before the fetched instructions 202F reach the execution circuit 212 for execution. Conveyors I₀-I_N instruction processing are provided in various circuits or processing stages of the instruction processing circuit 200 to preprocess and process the fetched instructions 202F in a series of steps that can be executed in parallel to increase throughput prior to executing the fetched instructions 202F by the execution circuit 212.

[0031] With further reference to FIG. 2, the instruction processing circuit 200 includes an instruction decoding circuit 214 configured to decode the sampled instructions 202F sampled by the instruction sampling circuit 204 into decoded instructions 202D so as to determine the type of instructions and required actions. The decoded instructions 202D are placed in one or more instruction processing pipelines I ₀ -I _N and are then provided to a renaming circuit 216 in the instruction processing circuit 200 to determine whether register names in the decoded instructions 202D should be renamed to break any dependencies between registers that should prevent parallel processing or out-of-order processing. The renaming circuit 216 is configured to call a register mapping table (RMT) 218 with the ability to rename the logical source register operand and/or write the target register operand of the decoded instruction 202D to the available physical registers 220(1)-220(X) (P ₀ , P ₁ , ..., P _X ) in the 222 physical register file (PRF). RMT 218 contains a plurality of conversion entries mapped (ie, associated) to a corresponding logical register R ₀ -R _P . The conversion records are configured to store information in the form of an address pointer to point to the physical register 220(1)-220(X) in the physical register file (PRF) 222. Each physical register 220(1)-220(X) in the PRF 222 contains a data record configured to store data for a source and/or destination register operand of the decoded instruction 202D.

[0032] The instruction processing circuit 200 also includes a register access circuit (RACC) 224 configured to access the physical register 220(1)-220(X) in the PRF 222 based on a mapping entry mapped to the logical register R ₀ -R _P in the RMT 218 of the source register operand of the decoded instruction 202D to extract the generated value from the executed instruction 202E in the execution circuit 212. The RACC circuit 224 is also configured to provide the extracted generated value from the executing decoded instruction 202E as the source register operand of the decoded instruction 202D to be executed. In addition, in the instruction processing circuit 200, the scheduler circuit 226 is provided in the instruction processing pipeline I ₀ -I _N and is configured to store the decoded instructions 202D in reservation entries until all source register operands for the decoded instruction 202D are available. The scheduler circuit 226 supplies the decoded instructions 202D, ready for execution in the execution path L ₀ -L _K , to the execution circuit 212. Write circuitry 228 is also provided in instruction processing circuitry 200 to write back or commit generated values from executing instructions 202E to memory, for example, to PRF 222, to cache memory system 106, or to main memory 108.

[0033] With further reference to FIG. 2, the instruction processing circuit 200 also includes a control flow prediction circuit 230. The flow prediction control circuit 230 is configured to speculatively predict the outcome of a condition of a sampled conditional flow control instruction 202F, for example, a conditional branch instruction that controls whether or not a selected or unselected path in the instruction control flow path of instruction flow 210 is sampled into pipelines. I ₀ -I _N processing instructions for execution. Thus, the condition of the sampled conditional flow control instruction 202F need not be resolved upon execution by the execution circuit 212 before the instruction processing circuit 200 can continue processing the speculatively sampled instructions 202F. The prediction performed by the control flow prediction circuit 230 may be provided as prediction information 232 to the instruction fetch circuit 204 for use by the instruction fetch circuit 204 to determine the next instructions 202 to fetch.

[0034] However, if the condition of the conditional flow control instruction 202F is determined to be falsely predicted when the conditional flow control instruction 202F is executed in the execution circuit 212, the speculative fetched instructions 202F that are fetched after the conditional flow control instruction 202F are processed in the circuit 202 instruction processing, are reset because these instructions should not be processed. The instruction processing circuit 202 returns to a state that exists before the conditional flow control instruction 202F is processed. Speculative fetch instructions 202F that are cleared in response to a prediction error may include load-based instructions (“load instructions”) that issue speculative data requests 118 to cache memory system 106 in processor system 100 of FIG. 1. If such speculative data requests 118 result in cache misses, the data is evicted from the cache system 106 to make room for responding with data to any such speculative data requests 118. This may cause cache pollution. This may also cause security issues. For example, a malicious attack process running on processor 102 may discern information regarding data accessed by a victim process running on processor 102 based on incorrect speculative data loaded into cache system 106 . A malicious attacking process may prime the cache system 106 with its own data and prepare the flow prediction control circuit 230 to make erroneous predictions for the conditional flow control instructions 202F in the victim process, causing incorrect speculative data to be loaded into the cache system 106. The attacking application can discern information regarding the victim process based on which of the prepared attack data in the cache system 106 is replaced by incorrect speculative data to be loaded into the cache system 106 .

[0035] In this regard, one or more caches 114(1)-114(X) in the cache system 106 in the processor system 100 in FIG. 1 may be configured to be non-speculative cache memories. The non-speculative cache is configured to defer updating a cache state for a cache entry for a received data request 118 for an update until the data request becomes non-speculative. For example, FIG. 3 illustrates an example of cache memory 114 in the processor system 100 of FIG. 1 configured as a non-speculative cache 114. As shown in FIG. 3, non-speculative cache memory 114 includes a cache controller 300, which is circuitry configured to control operations of non-speculative cache memory 114 including processing data requests 118 to access cache data stored in non-speculative cache memory 114 , providing data responses 302 for the cache data to the requestor, padding requests 304 to receive cache data from high-level memory in response to a cache miss for the received data request 118, and padding responses 306 with cache data received from the high-level memory, in response to a 304 padding request.

[0036] Non-speculative cache memory 114 also includes a main data array 308 that includes a plurality of cache entries 310(0)-310(M), each configured to store data 314(0)-314(M). ) caches stored in the memory system 104 of FIG. 1, at the memory address associated with the corresponding tag 312(0)-312(M). The non-speculative cache 114 also includes a tag array 311 that is configured to store a plurality of tags 312(0)-312(M) corresponding to corresponding cache entries 310(0)-310(M). The main data array 308 may also include a cache replacement state 315(0)-315(M) in each corresponding cache entry 310(0)-310(M) to indicate the replacement state for the associated cache entry 310(0)- 310(M) cache used by cache controller 300 to determine which cache entry 310(0)-310(M) should be evicted when new data for non-speculative data request 118 is to be stored in main data array 308. The main data array 308 may also include a valid indicator 316(0)-316(M) in each corresponding cache entry 310(0)-310(M) to indicate whether or not the data 314(0)- 314(M) cache is valid. The non-speculative cache memory 114 in this example also includes a speculative buffer memory 318 that includes a plurality of buffer entries 320(0)-320(B), each configured to store data 324(0)-324(B) ) caches stored in memory system 104 at a memory address associated with a corresponding buffer tag 322(0)-322(B). Non-speculative cache 114 also includes a tag array 323 that is configured to store buffer tags 322(0)-322(B) associated with a corresponding buffer entry 320(0)-320(B). For example, speculative buffer memory 318 may be a fill buffer for non-speculative cache 114 that acts as a staging area for incoming data in fill response 306 in response to an issued fill request 304 to be stored in non-speculative cache 114 until cache entry 310(0)-310(M) in main data array 308 becomes available to store incoming data.

[0037] With further reference to FIG. 3, the speculative buffer memory 318 also includes an instruction ID 326(0)-326(B) in each corresponding buffer entry 320(0)-320(B) to store the instruction ID of the actual load instruction that issues the data request 118 in a non-speculative cache 114 to keep track of whether or not a data request 118 becomes non-speculative. The cache controller 300 is configured to update the cache state associated with the data request 118 in a cache entry 310(0)-310(M) in the main data array 308 associated with the data request 118 after an instruction that causes the request 118 to be issued data becomes non-speculative in processor 102. As explained in more detail below, cache controller 300 is configured to allocate a buffer entry 320(0)-320(B) in speculative buffer memory 318 in response to a received data request 118. The cache controller 300 is configured to initially update the corresponding speculative indicator 330(0)-330(B) (NS) with the speculative state in each buffer entry 320(0)-320(B) for the received data request 118 as speculative. Each buffer entry 320(0)-320(B) in the speculative buffer memory 318 also includes a cache presence indicator 332(0)-332(B) indicating whether or not data is stored for the associated entry 320(0)- 320(B) of a buffer in a cache entry 310(0)-310(M) in the main data array 308, and a valid indicator 334(0)-334(B) indicating whether or not an entry 320(0)-320( B) the buffer is valid. The non-speculative cache 114 is configured to receive a commit indicator 328 provided by the processor 102 containing the instruction ID of the instruction itself, which is non-speculative. The cache controller 300 may use the received instruction ID in the commit indicator 328 to look up the instruction IDs 326(0)-326(B) in the speculative buffer memory 318 to update the corresponding non-speculative indicator 330(0)-330(B) (NS) each entry has 320(0)-320(B) buffers. The cache controller 300 may then update the cache state for the data associated with the data request 118 in the cache entry 310(0)-310(M) in the main data array 308 in response to the non-speculative indicator 330(0)-330(B) (NS ) for a data query 118 that becomes non-speculative.

[0038] For example, if load instruction 202D, which is speculatively processed based on control flow prediction in processor 102 in FIG. 2 instructs processor 102 to issue a data request 118 for data to non-speculative cache 114 in FIG. 3, cache controller 300 is configured to search tag array 311 for tag 312(0)-312(M) in cache entry 310(0)-310(M) associated with the target address of data request 118 to determine whether , whether the data for the 118 data request is present or not. The cache controller 300 is also configured to search the speculative buffer memory 318 for a buffer tag 322(0)-322(B) in the tag array 323 corresponding to a buffer entry 320(0)-320(B) associated with the target request address. 118 data to determine whether or not the data for the data request 118 is present in the speculative buffer memory 318. If a cache miss occurs in which the data for the data request 118 is not present in the main data array 308 or in the speculative buffer memory 318, the controller Cache 300 issues a fill request 304 for data from high-level memory and receives the requested data as a fill response 306. The cache controller 300 may be configured to delay updating the cache state for the data request 118 by not storing the initially received data in the padding response 306 for the data request 118 in the cache entry 310(0)-310(M) in the main data array 308. Instead, received data for data request 118 may first be stored as cache data 324(0)-324(B) in an allocated buffer entry 320(0)-320(B) in speculative buffer memory 318 so as not to pollute the main one. speculative data array 308. When the data request 118 becomes non-speculative, as indicated by the instruction ID in the commit indicator 328 matching the instruction ID 326(0)-326(B) in the buffer entry 320(0)-320(B) in the speculative buffer memory 318, the controller 300 The cache may cause data for the data request 118 to be stored in an allocated cache entry 310(0)-310(M) in the main data array 308.

[0039] In another example, when the target address of data request 118 matches a matching tag 312(0)-312(M) in tag array 311 in non-speculative cache 114, a cache hit results. This means that the data for the data request 118 is already contained in the cache entry 310(0)-310(M) in the main data array 308 corresponding to the matching tag 312(0)-312(M). Cache data 314(0)-314(M) for data request 118 stored in corresponding cache entry 310(0)-310(M) is returned as data response 302 to the requester at processor 102. However, status update 315 A cache replacement (0)-315(M) for a cache entry 310(0)-310(M) that has cache data 314(0)-314(M) for a data request 118 may be delayed until the request 118 data will not become non-speculative. Thus, for example, the replacement policy of the non-speculative cache 114 need not be executed based on the state of the replacement cache for a cache entry 310(0)-310(M) in the main data array 308 that is modified by a speculative data request 118 that may be flushed to processor 102 due to misprediction, which results in the cache state not being updated.

[0040] In another example, if a data request 118 issued from processor 102, non-speculative cache 114 is not contained in cache entry 310(0)-310(M) in main data array 308, but is contained in cache entry 320(0) )-320(B) buffers in the speculative buffer memory 318, the corresponding cache data 324(0)-324(B) for the data request 118 is returned to the requester in the processor 102 as a data response 302. However, the cache controller 300 may be configured to delay updating the cache state for the data request 118 by not storing the data in the speculative buffer memory 318 for the data request 118 in the cache entry 310(0)-310(M) in the main data array 308. so as not to pollute the main data set 308 with speculative data. When the data request 118 becomes non-speculative, as indicated by the instruction ID in the commit indicator 328 matching the instruction ID 326(0)-326(B) in the buffer entry 320(0)-320(B) in the speculative buffer memory 318, the controller 300 The cache may cause data for the data request 118 to be stored in an allocated cache entry 310(0)-310(M) in the main data array 308. Thus, as another example, if a further cache hit occurs in such an allocated cache entry 310(0)-310(M) for a new, subsequent data request 118, then the replacement state update 315(0)-315(M) cache entry 310(0)-310(M) in the main data array 308 that has cache data 314(0)-314(M) for data request 118 must be deferred until data request 118 becomes non-speculative , as explained above for successful cache access for the main data array 308.

[0041] FIG. 4 is a flowchart illustrating an example backoff process 400 by cache controller 300 in non-speculative cache 114 in FIG. 3, updates the data cache state for the received data request 118, which is speculative. Process 400 in FIG. 4 also includes updating a deferred cache state in the main data array 308 for data associated with the data request 118 in response to the data request 118 becoming non-speculative. The process 400 in FIG. is further explained. 4 in combination with the non-speculative cache 114 of FIG. 3 and processor 102 in FIG. 1 and 2. In this regard, the non-speculative cache 114 receives from the requester a data request 118 containing a target address and an instruction ID identifying a load instruction containing the target address processed by the processor 102 (step 402 in FIG. 4 ). Cache controller 300 searches tag array 311 for tag 312(0)-312(M) associated with the target address of data request 118 (step 404 in FIG. 4). The cache controller 300 also searches the speculative buffer memory 318 for a buffer tag 322(0)-322(B) associated with the target address of the data request 118 (step 406 in FIG. 4). The cache controller 300 sends a response 302 with data for a data request 118 to the requester in the processor 102 based on the tag 312(0)-312(M) in the cache entry 310(0)-310(M) in the main data array 308 associated with the target address. , and a buffer tag 322(0)-322(B) in a tag array 323 in the speculative buffer memory 318 associated with the target address of the data request 118 (step 408 in FIG. 4). Cache controller 300 receives a commit indicator 328 containing the instruction ID of the instruction itself, which is non-speculative (step 410 of FIG. 4). In response to a received instruction ID in the commit indicator 328 indicating that the load instruction of the data request 118 is non-speculative, the cache controller 300 updates the cache state for the cache entry 310(0)-310(M) in the main data array 308 associated with the target data request address 118 (step 412 in FIG. 4).

[0042] As also explained in more detail below, the non-speculative cache 114 may also include a speculative access registration (SAR) circuit 336 to keep track of whether or not data associated with a data request 118 is not yet known to be present. it is non-speculative, in the main data array 308 or in the speculative buffer memory 318. As explained above, the data for the received data request 118 may already be contained in the main data array 308, resulting in a cache hit, may already be contained in the speculative buffer memory 318, which also results in a cache hit, or may not be contained in any of them, which leads to a cache hit. In the event of a cache miss, a buffer entry 320(0)-320(B) that stores the data of the data request 118 is allocated in the speculative buffer memory 318. Thus, the data for the data request 118 may be stored in the main data array 308 or in speculative buffer memory 318. In response to receiving a commit indicator 328 indicating the instruction ID of the actual instruction that is being committed by processor 102, cache controller 300 requires a method for determining whether data associated with a data request 118 issued to as a result of an instruction match with an instruction identifier, in the main data array 308 or in the speculative buffer memory 318, so that the cache state can be updated. If data associated with a committed instruction identified by the instruction ID in the commit indicator 328 is stored in the main data array 308, the cache controller 300 must update the cache state for cache entries 310(0)-310(M) in the main data array 308 storing data for recorded request 118 data. If data associated with a committed instruction identified by the instruction ID in the commit indicator 328 is stored in the speculative buffer memory 318, the cache controller 300 must update the non-speculative indicator 330(0)-330(B) (NS) entries 320(0)-320 (B) buffer in speculative buffer memory 318. Cache controller 300 updates non-speculative indicator 330(0)-330(B) (NS) of buffer entry 320(0)-320(B) associated with the instruction ID as non-speculative, so that the data associated with the committed data request 118 is written to the main data array 308 as non-speculative data.

[0043] In this regard, as illustrated in FIG. 3, non-speculative cache 114 includes a SAR circuit 336 that is configured to store SAR entries 338(0)-338(S) associated with a corresponding instruction identifier 340(0)-340(S). When a data request 118 is received, the cache controller 300 allocates a SAR entry 338(0)-338(S) allocated in the SAR schema 336 associated with the instruction identifier for the instruction that issues the data request 118. If data associated with the instruction identified by the instruction ID of the received data request 118 is already stored in the cache entry 310(0)-310(M) in the main data array 308, the main data array index 342(0)-342(S) ( The MDA) for the allocated SAR entry 338(0)-338(S) is updated with an index in the cache entry 310(0)-310(M) in the main data array 308, which contains the data for the data request 118. If the data associated with the instruction identified by the instruction ID of the received data request 118 is not stored in the cache entry 310(0)-310(M) in the main data array 308, but is stored in the buffer entry 320(0)-320(B) in speculative buffer memory 318, speculative buffer (SB) index 344(0)-344(S) for allocated SAR entry 338(0)-338(S) is updated with index in buffer entry 320(0)-320(B) in a speculative buffer memory 318 that contains data for the data request 118. If the data associated with the instruction identified by the instruction ID of the received data request 118 is not stored in the cache entry 310(0)-310(M) in the main data array 308 or in the buffer entry 320(0)-320(B) in the speculative buffer memory 318 resulting in a cache miss, the speculative buffer (SB) index 344(0)-344(S) for the allocated SAR entry 338(0)-338(S) is updated with the index in entry 320(0) -320(B) of a buffer in the speculative buffer memory 318 that contains data for the data request 118 received from the fill response 306 from the high-level memory in response to the fill request 304. As explained above, allocating a SAR record 338(0)-338(S) for data requests 118 in the SAR circuit 336 allows the cache controller 300 to determine whether or not to update the cache state of the data associated with the data request 118 , which becomes non-speculative, in the main data array 308 or in the speculative buffer memory 318.

[0044] To illustrate an example of using the SAR circuit 336 through the non-speculative cache 114 to keep track of logged speculative data requests and to be able to delay updating the cache state in the non-speculative cache 114 until the data request becomes non-speculative, FIGS are provided. . 5A and 5B. Fig. 5A illustrates output by processor 102 of FIG. 1, a data request 118 containing an instruction ID and a target address that is received by the non-speculative cache 114, resulting in a cache hit in the main data array 308 of the non-speculative cache 114. In this example, the instruction ID in the data request 118 , identifying the processing instruction that instructs the data request 118 to be issued, is instruction identifier 1. The cache controller 300 in the non-speculative cache memory 114 is configured to search the main data array 308 and the speculative buffer memory 318 to search for data corresponding to the target address of the data request 118. In this example, data corresponding to the target address of data request 118 is contained in the main data array 308, resulting in a cache hit. The data for the data request 118 in the main data array 308 is returned as a data response 302 to the requester in the processor 102. However, the instruction identified by instruction identifier 1 that instructs the data request 118 to be issued is considered speculative until the indicator 328 commit is not received by non-speculative cache 114 indicating otherwise, as explained above. The cache controller 300 in the non-speculative cache 114 is configured to allocate a SAR entry 338(1) in the SAR circuit 336 shown in FIG. 5A associated with instruction ID 1 to register a cache state update deferral in the main data array 308 for data request 118. As shown in FIG. 5A, instruction ID 1 is stored in instruction ID 340(1) of SAR record 338(1). Because the data request 118 results in a cache hit for the main data array 308 in the non-speculative cache 114, the cache set/path "12/4" of the cache entry 310(0)-310(M) in the main data array 308 that contains data for data request 118 is stored in MDA index 342(1). In this regard, cache controller 300 may later locate cache entry 310(0)-310(M) in main data array 308 based on MDA index 342(1) to update its cache state when instruction ID 1 is indicated as committed according to the received fixation indicator 328. It should be noted that zero is stored in the SB index 344(1) for the SAR record 338(1) because the data for the data request 118 is in the main data array 308 and not in the speculative buffer memory 318. It should be noted that in this example, the SAR record 338(0) records the data location for the previous data request 118 in the SB index 344(0) corresponding to record 1 in the speculative buffer memory 318. It should also be noted that the allocated SAR record 338(0)- 338(S) may optionally be supplemented by cache controller 300 with information associated with a delayed update of the cache replacement policy. For example, the SAR entry 338(0)-338(S) may be marked as the least recently used (MRU) entry in a cache replacement policy based on the most recently used (LRU) principle.

[0045] FIG. 5B illustrates an example of reception by processor 102 of FIG. 5A, a latching indicator 328 identifying instruction ID 1 as latched. In response, cache controller 300 is configured to search SAR schema 336 to determine whether SAR entry 338 contains instruction identifier 1 in instruction identifier 340(0)-340(S) to indicate that the update The state of the data request cache 118 associated with instruction ID 1 is deferred. In this example, instruction ID 1 is contained in SAR record 338(1) in response to a received data request 118 caused by processing instruction ID 1, as illustrated in FIG. 5A and described above. The cache controller 300 is configured to, in response to determining that instruction ID 1 is contained in the SAR entry 338(1), update the cache replacement state 315(0)-315(M) in the entry 310(0)-310(M). ) cache in the main data array 308, indexed by MDA index 342(1). This is because the cache entry 310(0)-310(M) in the main data array 308 indexed by the instruction ID MDA index 342(1) is no longer speculative according to the received commit indicator 328. The cache controller 300 may de-allocate the SAR entry 338(1) in response to receiving a commit indicator 328 indicating that instruction ID 1 is committed to free up space to record the cache update status of future received data requests 118.

[0046] To illustrate an example of using SAR circuit 336 and speculative buffer memory 318 in non-speculative cache 114 to keep track of logged speculative data requests and be able to delay updating the cache state in non-speculative cache 114 until the data request is will become non-speculative, figs are provided. 6A and 6B. Fig. 6A illustrates output by processor 102 of FIG. 1, a data request 118 containing an instruction ID and a target address that is received by the non-speculative cache 114, resulting in a cache miss for the main data array 308 and the speculative buffer memory 318. In this example, the instruction ID in the data request 118 , identifying the processing instruction that instructs the data request 118 to be issued, is an instruction identifier 7. The cache controller 300 in the non-speculative cache memory 114 is configured to search the main data array 308 and the speculative buffer memory 318 to search for data corresponding to the target address of the data request 118. In this example, the data corresponding to the target address of data request 118 is not contained in the main data array 308 or in the speculative buffer memory 318 of the non-speculative cache 114. The instruction identified by instruction identifier 1 that instructs the data request 118 to be issued is considered speculative until until a commit indicator 328 is received by the non-speculative cache 114 indicating otherwise, as explained above.

[0047] The cache controller 300 in the non-speculative cache memory 114 is configured to allocate an available buffer entry 320(7) in the speculative buffer memory 318, as shown in FIG. 6A, which represents index 7 in this example. Thus, the data for data request 118 associated with instruction ID 1 and stored in the speculative buffer memory 318 in a speculative state in response to the received fill response 306 from the high-level memory can be retrieved and installed by the cache controller 300 in the main data array 308. when the data request 118 becomes non-speculative. The cache presence indicator 332(7) in the buffer entry 320(7) is set to "0" in this example, which means that the data associated with the received data request 118 is not contained in the main data array 308. The non-speculative indicator 330(7) for buffer entry 320(7) is set to "0" to indicate the speculative state in this example. The valid indicator 334(7) is set to "1" to indicate that the buffer entry 320(7) is valid in this example. If a buffer entry 320(0)-320(B) is not available in the speculative buffer memory 318, the cache controller 300 may be configured to send a retry indicator to the requester in the processor 102 as a data response 302 to indicate to the requester whether to retry attempts to request 118 data at a subsequent time. This provides more time for data requests 118 with registered deferred cache state updates stored in speculative buffer memory 318 to become non-speculative, which then causes their corresponding buffer entries 320(0)-320(B) to have the ability to be used and/or re-allocated, as discussed in more detail below with respect to FIG. 6B.

[0048] Again with reference to FIG. 6A, the cache controller 300 in the non-speculative cache 114 is also configured to allocate a SAR entry 338(0) in the SAR circuit 336 associated with instruction ID 1 to register a cache state refresh delay in the main data array 308 for data request 118 . As shown in FIG. 6A, instruction ID 1 is stored in instruction ID 340(0) of SAR record 338(0). Because the data request 118 results in a cache miss, a zero is contained in the MDA index 342(0) because the data for the data request 118 is not stored in the main data array 308. SB index "7" is stored in SB index 344(0) in this example to point to a buffer entry 320(7) allocated in the speculative buffer memory 318 that records the speculative state of the data request 118 associated with instruction ID 1. In this regard, cache controller 300 may later search SAR circuit 336 for instruction ID 1 when its request for associated data 118 becomes non-speculative to determine buffer entry 320(0)-320(B) to update its corresponding speculative indicator 330 (7) to a non-speculative state. It should be noted that zero is stored in the MDA index 342(0) for the SAR record 338(1) since the data for the data request 118 is not contained in the main data array 308. Cache controller 300 is configured to record data for data requests 118 associated with instruction identifiers contained in buffer entry 320(0)-320(B) in speculative buffer memory 318, which have speculative indicator 330(7) as a non-speculative state. . Fig. 6B illustrates an example of reception by processor 102 of FIG. 6A, a latching indicator 328 identifying instruction ID 1 as latched. In response, cache controller 300 is configured to search SAR schema 336 to determine whether SAR entry 338 contains instruction identifier 1 in instruction identifier 340(0)-340(S) to indicate that the update The state of the data request cache 118 associated with instruction ID 1 is deferred. In this example, instruction ID 1 is contained in SAR record 338(0) in response to a received data request 118 caused by processing instruction ID 1, as illustrated in FIG. 6A and described above. Cache controller 300 is configured to, in response to determining that instruction ID 1 is contained in SAR entry 338(0), access SB index 344(0) to determine buffer entry 320(0)-320(B). , associated with instruction ID 1. In this example, index "7" is stored in SB index 344(0) to point to buffer entry 320(7) in speculative buffer memory 318. Non-speculative indicator 330(7) is set as a non-speculative state that is "1" in this example. Thus, cache controller 300 may record data associated with data request 118 for instruction ID 1 registered in buffer entry 320(7) in main data array 308. The cache controller 300 may wait for a data entry associated with a data request 118 for instruction ID 1 registered in a buffer entry 320(7) in the main data array 308 until a new buffer entry 320(0)-320(B) must be allocated in speculative buffer memory 318, and there are no empty buffer entries 320(0)-320(B). Data associated with a data request 118 for instruction ID 1 may remain in the buffer entry 320(7) because a subsequent data request 118 for identical data based on its target address may be satisfied as a cache hit from the speculative buffer memory 318, as described above. When cache controller 300 writes data associated with data request 118 for instruction ID 1 registered in buffer entry 320(7) in main data array 308, cache presence indicator 332(7) must be set to indicate that the data are stored in the main data array 308 by means of an indicator "1". Thus, when the cache controller 300 needs to allocate a new buffer entry 320(0)-320(B) in the speculative buffer memory 318 for a new data request 118, the cache controller 300 may search the buffer entry 320(0)-320(B), which has a cache presence indicator set to "1" in this example. This means that the data for the buffer entry 320(0)-320(B) is written to the main data array 308 as non-speculative data, and therefore the associated buffer entry 320(0)-320(B) may be subject to de-allocation and /or re-allocate.

[0049] With respect to SAR circuit 336 and speculative buffer memory 318 in FIG. 3, as well as updating the speculative state of the monitored data request 118 to the non-speculative state in the example of FIG. 6B, the fact that the identifier becomes non-speculative ultimately triggers the cache controller 300 to write data for the data request 118 associated with the instruction identifier to the main data array 308. As explained above, a buffer entry 320(0)-320(B) in speculative buffer memory 318 for an instruction ID that becomes non-speculative and its converted associated SAR entry 338(0)-338(S) must be deallocated in the speculative buffer memory 318 so that they are available for another data request 118. However, other instruction identifiers may be allocated in SAR entries 338(0)-338(S) in SAR circuit 336, which are mapped to an identical buffer entry 320(0)-320(M) in speculative buffer memory 318. For example, , multiple data requests 118 may have an identical target address. If a buffer entry 320(0)-320(M) in the speculative buffer memory 318, mapped to multiple SAR entries 338(0)-338(S), is de-allocated, then the remaining SAR entries 338(0)-338( S) mapped to an identical buffer entry 320(0)-320(M) in speculative buffer memory 318 will have no knowledge of what the buffer entry 320(0)-320(M) is pointing to that has been canceled discharge. Thus, an instruction ID associated with such SAR entries 338(0)-338(S) that later becomes non-speculative will lose its mapping to the speculative buffer memory 318, causing it to fail to be updated, representing the associated cache state. As explained below, one way to resolve this problem is to provide another level of indirection for the conversion between the SAR circuit 336 and the speculative buffer memory 318.

[0050] The SAR circuit 336 explained above for tracking the speculative state of data requests 118 received through the non-speculative cache 114 may also be used in combination with a virtual fill buffer (VFB) circuit. As explained below, a virtual fill buffer (VFB) circuit may be used to map SAR entries 338(0)-338(S) to buffer entries 320(0)-320(B) in speculative buffer memory 318. VFB -circuitry may be used to keep track of whether data associated with a buffer entry 320(0)-320(B) in the speculative buffer memory 318 becomes non-speculative and written to the main data array 308 or not, so that other instruction identifiers may remain converted to VFB schema. The VFB circuit may monitor whether or not a buffer entry 320(0)-320(B) in the speculative buffer memory 318 associated with the instruction identifier remaining mapped from the SAR circuit 336 to the VFB circuit is written to the main data array 308. so the cache state update for such other mapped instruction IDs can be updated directly to the main data array 308 as its mapped associated buffer entry 320(0)-320(B) in the speculative buffer memory 318 must be deallocated.

[0051] It should be noted again with reference to the non-speculative cache 114 in FIG. 3 and in relation to FIG. 6A and 6B that when a cache entry 310(0)-310(M) is evicted from the main data array 308 by the cache controller 300, the cache controller 300 may also update the buffer entry 320(0)-320(B) in the speculative buffer memory 318 For example, if a particular cache entry 310(0)-310(M) (eg, by its set/path) in the main data array 308 is identified as a victim entry to be evicted by the cache controller 300, the cache controller 300 may be configured to search the buffer entries 320(0)-320(B) to determine whether or not there are buffer entries 320(0)-320(B) in the speculative buffer memory 318 that correspond to the evicted entry 310(0) -310(M) cache. If so, such corresponding buffer entry(s) 320(0)-320(B) may be invalidated by setting its corresponding valid indicator 334(0)-334(B) to an invalid state (eg, state "0"). Thus, if a new data request 118 is received in the non-speculative cache 114 having a target address corresponding to an evicted cache entry 310(0)-310(M) that results in a cache miss for the main data array 308, then a hit cache hits should not falsely occur in the speculative buffer memory 318. In this regard, FIG. 7A-7D illustrate an example of dispensing by processor 102 in FIG. 1, data requests 118 received by non-speculative cache 114 in cache system 106. In this example, the non-speculative cache memory includes an alternative SAR circuit 700 that can map to entries in a virtual fill buffer (VFB) circuit 708 that maps to a speculative buffer memory 318 for tracking speculative data requests 118 and updating the cache state of such queries in the main data set 308 when they become non-speculative. In this example, as shown in FIG. 7A, three (3) data requests 118 are made to non-speculative cache 114 identified by three (3) instruction IDs as instruction IDs 1, 4, and 8. The cache controller 300 in the non-speculative cache memory 114 is configured to search the main data array 308 and the speculative buffer memory 318 to search for data corresponding to the target address of these three data requests 118. In this example, the data corresponding to the data request target address 118 for instruction ID 1 is not contained in the main data array 308 or the speculative buffer memory 318 of the non-speculative cache 114, resulting in a cache miss. The cache controller 300 allocates a SAR entry 702(0) in the SAR circuit 700 shown in FIG. 7A, which is similar to SAR pattern 336 in FIG. 3. Instruction ID 1 is stored in instruction ID 704(0) in SAR record 702(0). The cache controller 300 also allocates a VFB entry 710(7) in the VFB circuit 708 shown in FIG. 7A. An index "7" corresponding to the allocated VFB record 710(7) is stored in a VFB index 706(0) in the SAR circuit 700 to convert the SAR record 702(0) for instruction ID 1 into a VFB record 710(7 ) in the VFB circuit 708. The cache presence indicator 714(7) in the SAR record 702(7) is set as data associated with the data request 118 initiated from instruction ID 1 as not being in the main data array 308 because the request 118 data associated with instruction ID 1 results in a cache miss. Thus, the MDA index 716(7) in the VFB record 710(7) is set to "0" or zero as not indicating a location in the main data array 308. However, the speculative buffer (SB) index 718(7) in the VFB circuit 708 is set as index "4" to map the VFB entry 710(7) to a buffer entry 320(4) in the speculative buffer memory 318, which contains data received from the fill response 306 to the allocated buffer entry 320(4) in the speculative buffer memory 318.

[0052] The cache controller 300 in the non-speculative cache memory 114 is also configured to search the main data array 308 and the speculative buffer memory 318 to search for data corresponding to the data request target address 118 for instruction IDs 4 and 8. In this example, both such lookups result in hits in speculative buffer memory 318 because these instructions are directed to a target address identical to the target address for data request 118 for instruction ID 1, and cache controller 300 populates this data into entry 320(4). buffers in speculative buffer memory 318 from response 306 to full. Thus, SAR records 702(0) and 702(2) with instruction IDs 1 and 7 in instruction IDs 704(0) and 704(2) are also converted to VFB index "7" in corresponding VFB indexes 706(0 ), 706(2). Thus, providing a VFB schema 708 allows multiple mappings of SAR records, which in this example are SAR records 702(1)-702(2), into an identical VFB index that can be mapped to record 320(0) -320(B) buffers in speculative buffer memory 318 to provide another level of conversion indirection.

[0053] It should also be noted that, as an option, when the current SAR record 702(0)-702(S) in the SAR circuit 700 is allocated in response to a new data request 118, if there is a stale SAR record 702(0 )-702(S) pointing to an identical VFB record 710 in VFB schema 708, the current SAR record 702(0)-702(S) may be collapsed into a legacy SAR record 702(0)-702(S). The current SAR record 702(0)-702(S) may replace the legacy SAR record 702(0)-702(S) or be ignored so that a new SAR record 702(0)-702(S) is not allocated. For example, in SAR circuit 700 in FIG. 7B, if SAR records 702(0) and 702(1) are associated with instruction ID 1, both SAR records 702(0), 702(1) may be provided as a single SAR record 702 since they both point to identical VFB record 710(7). As shown in FIG. 7B, the non-speculative cache 114 in this example receives a commit indicator 328 for instruction ID 1 to indicate that instruction ID 1 is committed to processor 102, and thereby data associated with the data request 118 for instruction ID 1 in entry 320 (4) the buffers in the speculative buffer memory 318 are now non-speculative. In this regard, cache controller 300 modifies NS indicator 330(4) for buffer entry 320(4) to "1" to indicate that the entry is non-speculative. Moreover, as shown in FIG. 7C, the cache controller 300 also changes the cache presence indicator 332(4) in the buffer entry 320(4) to "1" to indicate that the data associated with the data request 118 for instruction ID 1 is contained in the main data array 308 , in response to receiving data from the high-level memory in data response 302. Cache controller 300 may record data associated with data request 118 for instruction ID 1 registered in buffer entry 320(4) in main data array 308 based on NS indicator 330(4) indicating non-speculative state, as shown in FIG. 7C when buffer entry 320(4) is re-requested. As shown in FIG. 7D instruction identifiers 4 and 8 in SAR records 702(0), 702(1) mapped to VFB record 710(7), may use cache presence indicator 714(7) and MDA index 716(7) to know that the cache entry location 310(0)-310(M) is updated when instruction IDs 4 and 8 become non-speculative. Thus, if buffer entry 320(4) is de-allocated by cache controller 300 before instruction IDs 4 and 8 become non-speculative, VFB 708 stores information necessary for cache states for data request data 118 associated with IDs 4 and 8 instructions that must be updated in the main data array 308 using the cache presence indicator 714(7) and the MDA index 716(7).

[0054] It should be noted that for any of the above-described examples, the NS indicators 330(0)-330(B) in the speculative buffer memory 318 in the non-speculative cache memory 114 may further be used by the cache controller 300 to affect the order , in which buffer entries 320(0)-320(B) are evicted from speculative buffer memory 318. Recall that after evicting buffer entries 320(0)-320(B), if the NS indicator 330(0)-330(B ) is set as a non-speculative state for buffer write 320(0)-320(B), the corresponding data for buffer write 320(0)-320(B) is written to the main memory 108, otherwise, write 320(0)-320 (B) The buffer is discarded. Given a basic padding buffer replacement policy (eg, FIFO, LRU, PLRU, MRU, random, SRRIP, DRRIP, etc.), an optional advanced replacement policy may be used. If NS indicators 330(0)-330(B) for all buffer entries 320(0)-320(B) are marked in a non-speculative state, a basic replacement policy may be used by cache controller 300 to replace entries 320(0) -320(B) buffer. If the NS indicator 330(0)-330(B) for one buffer entry 320(0)-320(B) is marked in a non-speculative state, such buffer entry 320(0)-320(B) may be replaced first. If the NS indicator 330(0)-330(B) for more than one buffer entry 320(0)-320(B) is marked in a non-speculative state, the underlying replacement policy can be applied to all entries 320(0)-320(B) buffer having the NS indicator 330(0)-330(B) marked in the non-speculative state. If all buffer entries 320(0)-320(B) have NS indicator 330(0)-330(B) marked in the speculative state, any of the following replacement policies can be used as examples: basic replacement policy, entry selection 320 (0)-320(B) least recently used (MRU) buffer, select entry 320(0)-320(B) most recently used (LRU) buffer, select last inserted entry 320 (0)-320(B) buffer, selecting the first inserted 320(0)-320(B) buffer entry, and selecting a random 320(0)-320(B) buffer entry. A combination of the above replacement policies may be selected based on additional meta-information regarding the cache line requesters (eg, MRU if there is a possibility of a flush, or LRU if a flow is provided, etc.).

[0055] Additionally, in cases where the non-speculative cache 114 can receive data requests 118 from multiple CPU cores 110(1)-110(N), the SAR circuit 336, 700 may be implemented to maintain a record of all accesses to data for data requests 118, as well as identification data of the CPU core 110(0)-110(N) as a requester. VFB circuit 708 may be shared among multiple CPU cores 110(1)-110(N). In response to data requests 118, the non-speculative cache 114 may be configured to send commit identification data back to allow target commit messages to be sent by the CPU core 110(1)-110(N) to the non-speculative caches 114( 1)-114(X). This allows traffic to be reduced on interconnect bus 117 in FIG. 1 between the CPU core 110(0)-110(N) and cache memories 114(1)-114(X). In addition, instead of sending one commit message per non-speculative data request 118, processor 102 may also send an instruction commit information packet message to reduce traffic on interconnect bus 117. The instruction commit information packet may be explicit, with each instruction ID for request 118 data is specified in the packet message, or implicitly, with the instruction ID implying that all instruction identifiers below the non-speculative instruction ID are also non-speculative.

[0056] FIG. 8 is a block diagram of an exemplary processor system 800 that includes a processor 802 (eg, a microprocessor) that includes instruction processing circuitry 804. The processor system 800 may be the processor system 100 of FIG. 1 as an example. The instruction processing circuit 804 may be the instruction processing circuit 200 in FIG. 2 as an example. Processor system 800 may be circuitry or circuits included on an electronic circuit board, such as a printed circuit board (PCB), server, personal computer, desktop computer, laptop computer, personal digital assistant (PDA), tablet, mobile device, or any other device. , and can represent, for example, a server or a user's computer. In this example, processor system 800 includes a processor 802. Processor 802 represents one or more general purpose processing circuitry, such as a microprocessor, a central processing unit, and the like. More specifically, processor 802 may be an EDGE instruction set microprocessor or other processor implementing an instruction set that supports explicit consumer naming for data exchange of generated values resulting from execution of manufacturer instructions. The processor 802 is configured to execute processing logic in instructions to perform the operations and steps explained herein. In this example, processor 802 includes an instruction cache 808 for temporary storage in fast access memory of instructions accessible through instruction processing circuit 804. Instructions fetched or prefetched from memory, such as from main memory 810 on system bus 812, are stored in instruction cache 808. The instruction processing circuit 804 is configured to process instructions fetched into the instruction cache 808 and process the instructions for execution.

[0057] Processor 802 may include a local cache 814 to store cached data in main memory 810. A cache 816 outside of processor 802 between local cache 814 and main memory 810 may also be provided to provide system 818 cache memory. The caches 814, 816 in the cache system 818 may include any of the caches 114(1)-114(X) in FIG. 1, 3, 5A-5B, 6A-6B, and 7A-7D and are configured to delay updating the cache state in response to receiving a data request from processor 802 until the data request becomes non-speculative.

[0058] Processor 802 and main memory 810 are coupled to system bus 812 and may interconnect peripheral devices included in processor system 800. It is well known that processor 800 communicates with these other devices by exchanging address information, control information, and information in the form data on system bus 812. For example, processor 802 may transmit transaction requests via the bus to memory controller 819 in main memory 810 as an example of a slave device. Although not illustrated in FIG. 8, multiple system buses 812 may be provided, with each system bus being a separate structure. In this example, memory controller 819 is configured to provide memory access requests to memory array 820 in main memory 810. Memory array 820 consists of an array of bit storage cells for storing data. The main memory 810 may be read-only memory (ROM), flash memory, dynamic random access memory (DRAM), e.g., synchronous DRAM (SDRAM), etc., and static memory (e.g., flash memory, static random access memory (SRAM), etc.), as non-limiting examples.

[0059] Other devices may connect to system bus 812. As illustrated in FIG. 8, these devices may include main memory 810, one or more input devices 822, one or more output devices 824, a modem 826, and one or more display controllers 828, as examples. Input devices 822 may include any type of input device, including, but not limited to, keyboards, switches, voice processors, etc. Output devices 824 may include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. Modem 826 may be any device configured to communicate to/from network 830. Network 830 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, or a local area network. (LAN), wireless local area network (WLAN), wide area network (WAN), Bluetooth™ network and the Internet. Modem 826 may be configured to support any desired type of communication protocol. Processor 802 may also be configured to access display controller(s) 828 over system bus 812 to control information sent to one or more displays 832. Display(s) 832 may include any type of display, including including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, etc.

[0060] Processor system 800 in FIG. 8 may include a set of instructions 834 to be executed by processor 802 for any desired application as instructed. Instructions 834 may be stored in main memory 810, processor 802, and/or instruction cache 808 as examples of non-volatile computer-readable media 836. Instructions 834 may also reside, in whole or at least in part, in main memory 810 and/or in the 802 processor while they are executed. Instructions 834 may further be transmitted or received over network 830 via modem 826 such that network 830 includes computer-readable media 836.

[0061] Although computer-readable media 836 is shown in the exemplary embodiment as a single media, the term “computer-readable media” should be considered to include one media or multiple media (e.g., a centralized or distributed database and/or associated caches and servers), which store one or more sets of instructions. The term “machine-readable medium” should also be considered to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by a processing device and that instructs the processing device to perform any one or more of the technologies of the embodiments disclosed herein. The term "machine readable medium" should accordingly be considered to include, but not limited to, semiconductor memory devices, optical media, and magnetic media.

[0062] Embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in computer-executable instructions that can be used to instruct a general purpose or special purpose instruction programmable processor to execute the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0063] Embodiments disclosed herein may be provided as a computer program product or software, which may include a computer-readable medium (or computer-readable medium) storing instructions that can be used to program a computer system ( or other electronic devices) capable of performing the process according to the embodiments disclosed herein. Machine-readable media includes any mechanism for storing or transmitting information in a form readable by a machine (eg, a computer). For example, a computer-readable medium includes: a computer-readable storage medium (eg, ROM, random access memory (RAM), magnetic disk storage medium, optical storage medium, flash memory devices, etc.); and so on.

[0064] Unless otherwise expressly stated, and as is apparent from the preceding explanation, it should be appreciated that throughout the specification, explanations using terms such as “processing,” “calculation,” “determining,” “displaying,” and etc., mean the actions and processes of a computer system or similar electronic computing device that manipulates and converts data and memory blocks represented as physical (electronic) quantities in the registers of the computer system into other data similarly represented as physical quantities in computer system memory units or registers or other such devices for storing, transmitting or displaying information.

[0065] The algorithms and displays presented in this document are not inherently associated with any specific computer or other equipment. Various systems may be used with programs in accordance with the teachings herein, or it may be convenient to construct more specialized equipment capable of performing the required method steps. The required structure for a variety of these systems should be obvious from the above description. In addition, the embodiments described herein are not described with reference to specific programming languages. It should be appreciated that a variety of programming languages may be used to implement the ideas of the embodiments as described herein.

[0066] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in memory or in other machine-readable media and executed by a processor or other processing device or combinations thereof. The components of the distributed antenna systems described herein may be used in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. The memory disclosed herein may be any type and capacity of memory and may be configured to store any type of desired information. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps are described above generally in terms of their functionality. How such functionality is implemented depends on the specific application, design decisions, and/or design constraints imposed on the system as a whole. Those skilled in the art may implement the described functionality in different ways for each particular application, but such implementation decisions should not be interpreted as departing from the scope of the present embodiments.

[0067] Various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or executed by a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field programmable gate array ( FPGA) or other programmable logic device, discrete logic element or transistor logic, discrete hardware components, or any combination of the foregoing designed to perform the functions described in this document. Additionally, the controller may be a processor. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (eg, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors plus a DSP core, or any other such configuration).

[0068] Embodiments disclosed herein may be implemented in hardware and in instructions that are stored in hardware and may be permanently located in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from and write information from/to the storage medium. Alternatively, the storage medium may form an integral part of the processor. The processor and storage media can be permanently housed in the ASIC. The ASIC may be permanently located at the remote station. Alternatively, the processor and storage medium may be resident as discrete components in a remote station, base station, or server.

[0069] It should also be noted that the functional steps described in any of the exemplary embodiments herein are described to provide examples and explanation. The described operations may be performed in a variety of different sequences than those illustrated. In addition, operations described in one functional step may actually be performed in a number of different steps. Additionally, one or more of the functional steps explained in the exemplary embodiments may be combined. Those skilled in the art will also appreciate that information and signals may be represented using any of a variety of technologies. For example, the data, instructions, commands, information, signals, bits, symbols and chips that may be referred to throughout the foregoing description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. .

[0070] Unless expressly stated otherwise, it is not in any way intended that any method set forth herein should be construed as necessarily requiring that its steps be performed in a particular order. Accordingly, unless a method claim sets forth the actual order to be followed by its steps, or unless it is otherwise specifically stated in the claims or descriptions that the steps are to be limited to a particular order, it is not in any way intended that any particular order is logically inferred.

[0071] Those skilled in the art will appreciate that various modifications and changes may be made without departing from the spirit or scope of the invention. Since modifications, combinations, subcombinations and variations of the disclosed embodiments embodying the spirit and subject matter of the invention may be obvious to those skilled in the art, the invention should be construed to include everything within the scope of the appended claims and their equivalents.

Claims (77)

1. Non-speculative cache memory (114) in the processor system (100, 800), containing: - a main data array (308) containing a plurality of cache entries (310(0)-310(M)), each of which is configured to store cache data (314(0)-314(B)) associated with a memory address in memory system (104) of the processor system (100, 800); - a speculative buffer memory (318) containing a plurality of buffer entries (320(0)-320(B)), each of which contains a data entry configured to store cached data (324(0)-324(B)) associated with a memory address in the memory system (104), wherein the speculative buffer memory is configured to hold data retrieved from the high-level memory after a cache failure; And - cache controller (300), configured to: - receive from the requester a data request (118) containing a target address and an instruction identifier (ID) identifying a load instruction containing said target address processed by the processor (102, 802) in the processor system (100, 800); - search for a cache entry (310(0)-310(M)) in the main data array (308) associated with the target address of the data request (118); - search the speculative buffer memory (318) for a buffer entry (320(0)-320(B)) associated with the target address of the data request (118); - send to the requester a response (302) with data to a request (118) for data based on cache data in the main array (308) of data associated with the target address, and cache data in the buffer entry (320(0)-320(B)) in a speculative buffer memory (318) associated with the target address; - receive a commit indicator (328) containing the instruction ID of the instruction itself (202), which is non-speculative; And - in response to the received instruction ID in the commit indicator (328) indicating that the data request (118) load instruction is non-speculative: - update the cache state for a cache entry (310(0)-310(M)) in the main data array (308) associated with the target data request address (118), wherein cache state updates are based on a policy selected from additional metainformation about cache line requester; additionally comprising a “SAR” speculative access registration circuit (336), configured to store a SAR record containing an instruction ID record (340) and a main data record (342); - wherein the cache controller is additionally configured to: - in response to the fact that the cache entry in the main data array is associated with the target address of the data request, the cache controller is further configured to: - highlight the said SAR record in the SAR schema, wherein the SAR record contains an instruction ID record containing the instruction ID of the data request loading instruction itself, and a main data record containing the index of a cache record in the main data array associated with the target address of the data request ; And - in response to the received instruction ID in the commit indicator indicating that the data request load instruction is non-speculative: - determine whether or not the received instruction ID is contained in the instruction ID record in the SAR record in the SAR diagram; And - in response to determining that the received instruction ID is contained in a SAR entry in the SAR schema, update the cache replacement state of the cache entry itself in the main data set corresponding to said index in the main data record associated with the target data request address, in SAR record containing the received instruction ID. 2. Non-speculative cache memory according to claim 1, in which: - the cache controller is further configured to determine whether or not a cache entry in the main data array is associated with the target address of the data request; And - in response to the fact that a cache entry in the main data array is associated with a target address of a data request, the cache controller is configured to send to the requester a data response to the data request containing cache data in a cache entry in the main data array having a target address associated with the target address of the data request. 3. The non-speculative cache memory of claim 2, wherein the cache controller is configured, in response to the received instruction ID in the commit indicator indicating that the data request load instruction is non-speculative, to update a cache state containing the replacement state cache of the actual cache entry in the main data array associated with the target address of the data request. 4. The non-speculative cache memory of claim 2, wherein the cache controller is further configured to, in response to the fact that a cache entry in the main data array is not associated with a data request target address: - determine whether or not a buffer entry in the speculative buffer memory is associated with the target address of the data request; And - in response to the fact that a buffer entry in the speculative buffer memory is associated with a target address of a data request, the cache controller is configured to send to the requester a data response to the data request containing cache data in the buffer entry in the speculative buffer memory having a target address associated with the target address of the data request. 5. The non-speculative cache memory of claim 4, wherein the cache controller is further configured to, in response to the fact that a buffer entry in the speculative buffer memory is not associated with a data request target address: - send a data request to the next high-level memory in the processor system; - receive data to request data from the next high-level memory; - determine whether a buffer entry is available in the speculative buffer memory for storing cache data; And - in response to determining that a buffer entry in the speculative buffer memory is available for storing cache data, write the data request data received from the next higher-level memory in the available buffer entry in the speculative buffer memory and in the available buffer entry associated with the target address data request. 6. The non-speculative cache memory of claim 5, wherein the cache controller is configured to, in response to the received instruction ID in the commit indicator indicating that the data request load instruction is non-speculative: - update the cache state of the cache entry itself in the main data array associated with the target address of the data request, being configured to write data for the data request in a buffer entry in the speculative buffer memory associated with the target address of the data request, in the cache entry in the main data array , associated with the target address of the data request. 7. The non-speculative cache memory of claim 6, wherein the cache controller is further configured to select a buffer entry from the plurality of buffer entries in the speculative buffer memory to be evicted from the speculative buffer memory based on the speculative state in the non-speculative indicators of the corresponding buffer entries. 8. Non-speculative cache memory according to claim 5, in which: - each buffer entry in the speculative buffer memory further contains a non-speculative indicator indicating whether or not the buffer entry is non-speculative; And - the cache controller is additionally configured to: - in response to the fact that a buffer entry in the speculative buffer memory is associated with the target address of the data request: - set a non-speculative indicator in a buffer entry in the speculative buffer memory associated with the target address of the data request to a speculative state; - in response to the received instruction ID in the commit indicator indicating that the data request load instruction is non-speculative: - set the non-speculative indicator in the buffer entry in the speculative buffer memory associated with the target address of the data request to a non-speculative state; And - in response to the fact that the non-speculative indicator in the buffer entry in the speculative buffer memory associated with the target address of the data request is set to the non-speculative state: - update the cache state of the cache entry itself in the main data array associated with the target address of the data request, being configured to write data for the data request in a buffer entry in the speculative buffer memory associated with the target address of the data request, in the cache entry in the main data array , associated with the target address of the data request. 9. Non-speculative cache memory according to claim 8, additionally containing: - a SAR circuit configured to store a SAR record containing an instruction ID record and a virtual fill buffer “VFB” index record; And - a VFB circuit configured to store a VFB record containing an instruction ID record and a VFB index record; - the cache controller is additionally configured to: - in response to the fact that a buffer entry in the speculative buffer memory is not associated with the target address of the data request: - allocate a VFB record in the VFB circuit, wherein the VFB record contains an instruction ID record containing the instruction ID of the actual data request loading instruction, and a VFB index record containing the index of the buffer record in the speculative buffer memory associated with the target address of the data request; And - allocate a SAR record in the SAR circuit, wherein the SAR record contains an instruction ID record that stores the instruction ID of the data request loading instruction itself, and a VFB index record that stores the index of the VFB record in the VFB circuit that has an instruction ID record containing Instruction ID; And - in response to the received instruction ID in the commit indicator indicating that the data request load instruction is non-speculative: - determine a VFB entry in an associated VFB schema having an instruction ID entry containing the indexed instruction ID based on an index in the VFB index in a SAR entry in the SAR schema having an instruction ID entry containing the received instruction ID; And - determine a buffer entry in the speculative buffer memory associated with the target address of the data request set to the non-speculative state based on the index in the VFB index entry in the specific VFB entry in the VFB schema; - a cache controller configured to: - set the non-speculative indicator in a buffer entry in a specific buffer entry in the speculative buffer memory associated with the target address of the data request to a non-speculative state. 10. The non-speculative cache memory of claim 9, wherein the cache controller is further configured to, in response to allocation of a SAR entry in the SAR circuit: - determine whether or not another SAR record contained in the SAR diagram contains an instruction ID in its instruction ID record and a VFB index record in its VFB record; And - in response to a determination that the SAR schema contains another SAR record, de-allocate the SAR record in the SAR schema. 11. The non-speculative cache memory of claim 1, wherein the cache controller is further configured to evict a buffer entry in the speculative buffer memory in response to eviction of a cache entry in the main data array according to a memory address corresponding to the buffer entry. 12. A method for updating cache state in a non-speculative cache memory (114) in a processor system (100, 800), comprising the steps of: - receiving (402) from the requester a data request (118) containing a target address and an instruction identifier (ID) identifying a load instruction containing said target address processed by the processor (102, 802) in the processor system (100, 800); - perform a search (404) in the main data array (308) for a cache entry (310(0)-310(M)) associated with the target address of the data request from the plurality of entries (310(0)-310(M)) caches, each of which is configured to store cache data (314(0)-314(B)) associated with a memory address in the memory system (104) of the processor system (100, 800); - searching (406) in the speculative buffer memory (318) for a buffer entry (320(0)-320(B)) associated with the target address of the data request (118), from the plurality of entries (320(0)-320( B)) buffers, each of which is configured to store cache data (324(0)-324(B)) associated with a memory address in the memory system (104), wherein the speculative buffer memory is configured to hold data retrieved from higher-level memory after a cache failure; - send (408) to the requester a response (302) with data to a request (118) for data based on a cache entry (310(0)-310(M)) in the main data array (308) associated with the target address, and cache data in writing (320(0)-320(B)) a buffer in a speculative buffer memory (318) associated with the target address; - receive (410) a commit indicator (328) containing the instruction ID of the actual instruction (202), which is non-speculative; And - updating (412) the cache state of the actual cache entry (310(0)-310(M)) in the main data array (308) associated with the target address of the data request (118), in response to the received instruction ID in the indicator (328) commit indicates that the data request (118) load instruction is non-speculative, with cache state updates based on a policy selected by additional meta-information about the cache line requester; wherein the method further comprises storing the SAR record by the speculative access registration “SAR” circuit (336), the SAR record comprising an instruction ID record (340) and a main data record (342); - in response to the fact that the cache entry in the main data array is associated with the target address of the data request, the method further comprises: - highlighting said SAR record in the SAR circuit, wherein the SAR record contains an instruction ID record containing the instruction ID of the data request loading instruction itself, and a main data record containing the index of a cache record in the main data array associated with the target address of the data request ; And - in response to the received instruction ID in the commit indicator indicating that the data request load instruction is non-speculative: - determining whether or not the received instruction ID is contained in the instruction ID record in the SAR record in the SAR diagram; And - in response to determining that the received instruction ID is contained in a SAR entry in the SAR schema, updating the cache replacement state of the cache entry itself in the main data set corresponding to said index in the main data record associated with the target address of the data request, in SAR record containing the received instruction ID. 13. Method according to item 12: - further comprising a step of determining whether or not the cache entry in the main data array is associated with the target address of the data request; And - comprising the step of sending to the requester a data response to a data request containing cache data in a cache entry in the main data array having a target address associated with the target address of the data request, in response to a cache entry in the main data array associated with the target data request address. 14. The method of claim 13, further comprising, in response to the fact that the cache entry in the main data array is not associated with the target address of the data request, the steps of: - determining whether or not the buffer entry in the speculative buffer memory is associated with the target address of the data request; And - sending to the requester a data response to the data request containing cache data in a buffer entry in a speculative buffer memory having a target address associated with the target address of the data request.