RU2817560C1 - Hardware-accelerated generation of k-dimensional graph - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: invention relates to methods and systems for hardware-accelerated generation of K-dimensional graphs representing multiple sequencing reads for analysis of variant recognition. In one aspect, the method involves steps for obtaining a first set of nucleotide sequences generated by a nucleic acid sequencer, constructing a K-dimensional graph using the obtained first set of nucleotide sequences and using a plurality of non-pipelined hardware logic units of the programmable logic device, and periodic updating, by means of the data management device, of the graphical representation for the K-dimensional graph after performing one or more operations by each hardware logic unit.

EFFECT: faster generation of a K-dimensional graph, which leads to faster genome analysis as a whole.

34 cl, 5 dwg

Description

CROSS-REFERENCES TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63/006,668, filed April 7, 2020, which is incorporated herein by reference in its entirety.

PREREQUISITES FOR CREATION OF THE INVENTION

[0002] K-dimensional graphs can be used to represent multiple sequencing reads.

SUMMARY OF THE INVENTION

[0003] In accordance with one innovative aspect of the present disclosure, a method for hardware-accelerated K-dimensional graph generation using a programmable logic device is described. In one aspect, the method may include the steps of obtaining a first set of nucleotide sequences, wherein the first set of nucleotide sequences includes (i) a plurality of reads corresponding to an active region of a reference sequence, and (ii) a portion of the reference sequence generated using a plurality of non-pipelined hardware logic blocks of a programmable logic device, a K-dimensional graph using the resulting first set of nucleotide sequences, each hardware logic unit comprising another hardware logic unit configured to perform one or more operations, each node of the K-dimensional graph representing a K-mer, each edge of a K-mer graph represents the connection between a pair of K-mers, and each mass of each edge of a K-mer graph represents the number of occurrences of a sequence of K-mers represented by a pair of K-mers, and in the process of generating a K-mer graph: periodic updating , at the control device, graph description data for the K-dimensional graph after performing one or more operations by each hardware logical unit, which is used to generate at least a portion of the K-dimensional graph, wherein the graph description data is (i) a K-dimensional identifier graph and (ii) K-dimensional graph state information, wherein the control device creates a workflow of operations using the non-pipelined hardware logic blocks by triggering execution of one or more operations of each corresponding hardware logic block during generation of the K-dimensional graph.

[0004] Other embodiments include corresponding systems and apparatus that have been configured to perform the actions of the above methods determined by the hardware logic circuits of the hardware-accelerated graph generation unit.

[0005] These and other versions may optionally include one or more of the following features. For example, in some embodiments, the output of each hardware logical block of a plurality of hardware logical blocks is stored by a hash table buffer capacity.

[0006] In some embodiments, the control device is implemented using a hardware programmable logic device logic block.

[0007] In some embodiments, the control device is implemented using one or more CPUs or GPUs to execute software instructions to implement the functions of the control device.

[0008] In some embodiments, the operations may further include providing the generated K-dimensional graph to a variant recognition unit, wherein the variant recognition unit processes the K-dimensional graph to determine potential variants between one or more of the plurality of reads and a reference sequence.

[0009] In some embodiments, software instructions may be executed by one or more CPUs or GPUs to implement one or more functions of the variant recognition unit.

[0010] In some embodiments, a programmable logic device is used to accelerate one or more functions of the variant recognition unit.

[0011] In some embodiments, the graph description data further includes (iii) data representing the last hardware logic block of a plurality of hardware logic blocks performing hardware logic on the K-dimensional graph or nucleotide sequences associated with a K-dimensional graph identifier.

[0012] In accordance with another innovative aspect of the present disclosure, a hardware-accelerated K-dimensional graph generation system using a programmable logic device is described. In one aspect, the system may include a hardware-accelerated graph generation unit that includes hardware-based digital logic circuits that have been arranged to perform operations. In some embodiments, the operation may include: obtaining a first set of nucleotide sequences, wherein the first set of nucleotide sequences includes (i) a plurality of reads corresponding to an active region of a reference sequence, and (ii) a portion of the reference sequence generated using a plurality of non-pipelined hardware logical blocks of a programmable logic device, a K-dimensional graph using the resulting first set of nucleotide sequences, each hardware logic unit comprising another hardware logic circuit configured to perform one or more operations, wherein each node of the K-dimensional graph represents a K-mer , each edge of a K-mer graph represents the connection between a pair of K-mers, and each mass of each edge of a K-mer graph represents the number of occurrences of a sequence of K-mers represented by a pair of K-mers, and in the process of generating a K-mer graph: periodic updating, on the control device, the graph description data for the K-dimensional graph after performing one or more operations by each hardware logical unit that is used to generate at least a portion of the K-dimensional graph, wherein the graph description data is (i) a K-dimensional identifier graph and (ii) K-dimensional graph state information, wherein the control device creates a workflow of operations using the non-pipelined hardware logic blocks by triggering execution of one or more operations of each corresponding hardware logic block during generation of the K-dimensional graph.

[0013] Other embodiments include suitable methods and apparatus for performing the above operations.

[0014] These and other versions may optionally include one or more of the following features. For example, in some embodiments, the output of each hardware logical block of a plurality of hardware logical blocks is stored by a hash table buffer capacity.

[0015] In some embodiments, the operations may further include providing the generated K-dimensional graph to a variant recognition unit, wherein the variant recognition unit is configured to process the K-dimensional graph to determine potential variants between one or more of the plurality of reads and a reference sequence.

[0016] In some embodiments, the system may further include one or more computers and one or more storage devices that store instructions that, when executed by one or more computers, cause the one or more computers to execute second variant recognition unit operations. In some embodiments, the second operations of the variant recognition block may include, using the variant recognition block, retrieving a generated K-dimensional graph and, based on processing of the variant recognizing block of the generated K-dimensional graph, identifying one or more candidate variants, wherein the candidate variant is a difference between recognizing the bases of one or more reads in a set of reads and a reference genome nucleotide at a specific location in the reference genome.

[0017] In some embodiments, the operations may further include, by a variant recognition block, obtaining a generated K-dimensional graph and, based on the variant recognition block's processing of the generated K-dimensional graph, identifying one or more candidate variants, wherein a candidate variant is a difference between recognizing the bases of one or more reads in a set of reads and a reference genome nucleotide at a specific location in the reference genome.

[0018] In some embodiments, the graph description data may further include (iii) data representing the last hardware logic block of a plurality of hardware logic blocks performing hardware logic on the K-dimensional graph or nucleotide sequences associated with a K-dimensional graph identifier .

[0019] In accordance with another innovative aspect of the present disclosure, a hardware-accelerated graph generation unit is described. In one aspect, a hardware-accelerated graph generating unit may include hardware-based digital logic circuits that have been arranged to perform operations. In some embodiments, operations may include obtaining a first set of nucleotide sequences, wherein the first set of nucleotide sequences includes (i) a plurality of reads corresponding to the active region of a reference sequence, and (ii) a portion of the reference sequence generated using a plurality of non-pipelined hardware logic blocks of a programmable logic device, a K-dimensional graph using the resulting first set of nucleotide sequences, each hardware logic unit comprising another hardware logic unit configured to perform one or more operations, each node of the K-dimensional graph representing a K-mer, each edge of a K-mer graph represents the connection between a pair of K-mers, and each mass of each edge of a K-mer graph represents the number of occurrences of a sequence of K-mers represented by a pair of K-mers, and in the process of generating a K-mer graph: periodic updating , at the control device, graph description data for the K-dimensional graph after performing one or more operations by each hardware logical unit, which is used to generate at least a portion of the K-dimensional graph, wherein the graph description data is (i) a K-dimensional identifier graph and (ii) K-dimensional graph state information, wherein the control device creates a workflow of operations using the non-pipelined hardware logic blocks by triggering execution of one or more operations of each corresponding hardware logic block during generation of the K-dimensional graph.

[0020] Other embodiments may include methods and systems configured to operate hardware circuits of a hardware-accelerated graph generation unit.

[0021] These and other versions may optionally include one or more of the following features. For example, in some embodiments, the output of each hardware logical block of a plurality of hardware logical blocks is stored by a hash table buffer capacity.

[0022] In some embodiments, the operations may further include providing the generated K-dimensional graph to a variant recognition unit, wherein the variant recognition unit is configured to process the K-dimensional graph to determine potential variants between one or more of the plurality of reads and a reference sequence.

[0023] In some embodiments, the operations may further include, using the variant recognition block, obtaining a generated K-dimensional graph and identifying, based on the variant recognition block's processing of the generated K-dimensional graph, one or more candidate variants, wherein the candidate variant is a difference between recognizing the bases of one or more reads in a set of reads and a reference genome nucleotide at a specific location in the reference genome.

[0024] In some embodiments, the graph description data may further include (iii) data representing the last hardware logic block of a plurality of hardware logic blocks performing hardware logic on the K-dimensional graph or nucleotide sequences associated with a K-dimensional graph identifier .

[0025] In accordance with another innovative aspect of the present disclosure, a method for hardware-accelerated generation of a K-dimensional graph in a programmable logic device is described. In one aspect, the method may include the steps of obtaining a first set of nucleotide sequences, the first set of nucleotide sequences including (i) a plurality of reads corresponding to an active region of a reference sequence, and (ii) a portion of the reference sequence for each specific nucleotide sequence from the first set of nucleotide sequences : generating for storage in a buffer capacity a hash table and the first hardware logical unit of data representing a graph node for each K-mer of a particular nucleotide sequence, detecting by the control device that the first hardware logical unit has completed generating a graph node for each K-mer of a particular nucleotide sequences, configuring by the control device of a second hardware logic unit to perform graph edge generation for the generated graphs and for one or more pairs of generated node graphs: generated by the second hardware logic unit and for storing in a graph hash table, data representing graph boundaries between one or more pairs of generated graph nodes generated by the first hardware logic unit, wherein data representing a graph node for each K-mer stored in a hash table buffer and data representing graph edges stored in a hash table buffer constitute graph K -measure of the first set of nucleotide sequences.

[0026] Other embodiments include corresponding systems and apparatus that have been configured to perform the actions of the above methods determined by the hardware logic circuits of the hardware-accelerated graph generation unit.

[0027] These and other versions may optionally include one or more of the following features. For example, in some embodiments, the method may further include periodically storing, by the control device and in a memory unit accessible to the control device, graph description data for a K-dimensional graph instance, wherein the graph description data is (i) a K-dimensional graph identifier and (ii) K-dimensional information about the state of the graph.

[0028] In some embodiments, the first hardware logic block may be further configured to: determine whether one or more particular K-mers of a particular nucleotide sequence are the same as another K-mer of a particular nucleotide sequence, and based on the determination that one or more specific K-mers of a particular nucleotide sequence match another K-mer of a particular nucleotide sequence, storing data that marks one or more specific K-mers as non-unique K-mers.

[0029] In some embodiments, the second hardware logic is further configured to: assign an edge mass to each edge of the K-dimensional graph.

[0030] In some embodiments, the method may further include instructing a third hardware logic block of the programmable logic device to execute hardware logic configured to: obtain data representing a K-dimensional graph from a hash table buffer capacity and provide the resulting data, representing the K-dimensional graph into the variant recognition block.

[0031] In some embodiments, the method may further include instructing a third hardware logic unit of the programmable logic device to execute hardware logic configured to: selectively remove data representing graph nodes and data representing edges of a K-dimensional graph from a buffer capacity hash tables.

[0032] In some embodiments, the control device is implemented using a third hardware logic block of a programmable logic device.

[0033] In some implementations, the hash table buffer capacity is implemented using a third hardware logic block of a programmable logic device.

[0034] In some embodiments, the control device is implemented using one or more CPUs or GPUs that execute software instructions to implement the functions of the control device.

[0035] In some embodiments, the graph description data further includes (iii) data representing the last hardware logic block of a plurality of hardware logic blocks performing hardware logic on the K-dimensional graph or nucleotide sequences associated with a K-dimensional graph identifier.

[0036] In some embodiments, the method may further include evaluating a K-dimensional graph to check for the presence of cycles in the graph. In such embodiments, if a graph cycle is detected during evaluation: the process may include stopping generation of the K-dimensional graph. In an alternative implementation, if no graph cycle is detected during evaluation: the method may include obtaining data from a hash table buffer that describes the structure of the K-dimensional graph, and providing the recognition module with variants of the resulting data that describe the structure of the K-dimensional graph.

[0037] In accordance with another innovative aspect of the present disclosure, a hardware-accelerated K-dimensional graph generation system using a programmable logic device is described. The system may include a hardware-accelerated graph generation unit that includes hardware-based digital logic circuits that have been positioned to perform the operations. In one aspect, the operations may include obtaining a first set of nucleotide sequences, wherein the first set of nucleotide sequences includes (i) a plurality of reads corresponding to the active region of a reference sequence, and (ii) a portion of the reference sequence for each specific nucleotide sequence from the first set of nucleotide sequences sequences: generation for storage in a buffer capacity of a hash table and the first hardware logical block of data representing a graph node for each K-mer of a specific nucleotide sequence, detection by the control device that the first hardware logical block has completed generating a graph node for each K-mer of a specific nucleotide sequence, configuring by the control device of a second hardware logic unit to perform graph edge generation for the generated graphs and for one or more pairs of generated node graphs: generated by the second hardware logic unit and for storing in a graph hash table, data representing the graph boundaries between one or more than pairs of generated graph nodes generated by the first hardware logic unit, wherein data representing a graph node for each K-mer stored in a hash table buffer capacity and data representing graph edges stored in a hash table buffer capacity constitute a graph K-mer of the first set of nucleotide sequences.

[0038] Other embodiments include suitable methods and apparatus for performing the above operations.

[0039] These and other versions may optionally include one or more of the following features. For example, in some embodiments, the operations may further include periodically storing, by the control device and in a memory unit accessible to the control device, graph description data for a K-dimensional graph instance, wherein the graph description data is (i) a K-dimensional graph identifier and (ii) K-dimensional information about the state of the graph.

[0040] In some embodiments, the first hardware logic block is further configured to: determine whether one or more particular K-mers of a particular nucleotide sequence are the same as another K-mer of a particular nucleotide sequence, and based on the determination that one or more specific K-mers of a particular nucleotide sequence match another K-mer of a particular nucleotide sequence, storing data that marks one or more specific K-mers as non-unique K-mers.

[0041] In some embodiments, the second hardware logic is further configured to: assign an edge mass to each edge of the K-dimensional graph.

[0042] In some embodiments, the operations may further include instructing a third hardware logic block of the programmable logic device to execute hardware logic configured to: obtain data representing the K-dimensional graph from the hash table buffer capacity and provide the resulting data, representing the K-dimensional graph into the variant recognition block.

[0043] In some embodiments, the operations may further include instructing a third hardware logic unit of the programmable logic device to execute hardware logic configured to: selectively remove data representing graph nodes and data representing edges of the K-dimensional graph from the buffer capacity hash tables.

[0044] In some implementations, the hash table buffer capacity is implemented using a third hardware logic block of a programmable logic device.

[0045] In some embodiments, the graph description data further includes (iii) data representing the last hardware logic block of a plurality of hardware logic blocks performing hardware logic on the K-dimensional graph or nucleotide sequences associated with a K-dimensional graph identifier.

[0046] In some embodiments, the method may further include evaluating a K-dimensional graph to check for the presence of cycles in the graph. In such embodiments, if a graph cycle is detected during evaluation: the process may include stopping generation of the K-dimensional graph. In an alternative implementation, if no graph cycle is detected during evaluation: the method may include obtaining data from a hash table buffer that describes the structure of the K-dimensional graph, and providing the recognition module with variants of the resulting data that describe the structure of the K-dimensional graph.

[0047] In accordance with another innovative aspect of the present disclosure, a hardware-accelerated graph generation unit is described. The hardware-accelerated graph generation unit may include hardware-based digital logic circuits that have been positioned to perform the operations. In one aspect, the operations may include obtaining a first set of nucleotide sequences, wherein the first set of nucleotide sequences includes (i) a plurality of reads corresponding to the active region of a reference sequence, and (ii) a portion of the reference sequence for each specific nucleotide sequence from the first set of nucleotide sequences sequences: generation for storage in a buffer capacity of a hash table and the first hardware logical block of data representing a graph node for each K-mer of a specific nucleotide sequence, detection by the control device that the first hardware logical block has completed generating a graph node for each K-mer of a specific nucleotide sequence, configuring by the control device of a second hardware logic unit to perform graph edge generation for the generated graphs and for one or more pairs of generated node graphs: generated by the second hardware logic unit and for storing in a graph hash table, data representing the graph boundaries between one or more than pairs of generated graph nodes generated by the first hardware logic unit, wherein data representing a graph node for each K-mer stored in a hash table buffer capacity and data representing graph edges stored in a hash table buffer capacity constitute a graph K-mer of the first set of nucleotide sequences.

[0048] Other embodiments may include methods and systems configured to operate hardware circuits of a hardware-accelerated graph generation unit.

[0049] These and other versions may optionally include one or more of the following features. For example, in some embodiments, the operations may further include periodically storing, by the control device and in a memory unit accessible to the control device, graph description data for a K-dimensional graph instance, wherein the graph description data is (i) a K-dimensional graph identifier and (ii) K-dimensional information about the state of the graph.

[0050] In some embodiments, the first hardware logic block may be configured to determine whether one or more specific K-mers of a particular nucleotide sequence are the same as another K-mer of a particular nucleotide sequence, and based on the determination that one or more specific K-mers of a particular nucleotide sequence match another K-mer of a particular nucleotide sequence, storing data that marks one or more specific K-mers as non-unique K-mers.

[0051] In some embodiments, the second hardware logic is further configured to: assign an edge mass to each edge of the K-dimensional graph.

[0052] In some embodiments, the operations may further include instructing a third hardware logic block of the programmable logic device to execute hardware logic configured to: obtain data representing the K-dimensional graph from the hash table buffer capacity and provide the resulting data, representing the K-dimensional graph into the variant recognition block.

[0053] In some embodiments, the operations may further include instructing a third hardware logic unit of the programmable logic device to execute hardware logic configured to: selectively remove data representing graph nodes and data representing edges of the K-dimensional graph from the buffer capacity hash tables.

[0054] In some implementations, the hash table buffer capacity is implemented using a third hardware logic block of a programmable logic device.

[0055] In some embodiments, the graph description data may further include (iii) data representing the last hardware logic block of a plurality of hardware logic blocks performing hardware logic on the K-dimensional graph or nucleotide sequences associated with a K-dimensional graph identifier .

[0056] In some embodiments, the operations may further include evaluating the K-dimensional graph to check for the presence of graph cycles, if a graph is detected during evaluation: stop generating the K-dimensional graph, or if no graph cycle is detected during evaluation: obtain data from the buffer capacity of the hash table describing the structure of the k-dimensional graph, and providing the recognition module with variants of the received data that describe the structure of the k-dimensional graph.

[0057] These and other aspects of the present specification are described in more detail below with reference to the accompanying drawings.

BRIEF DESCRIPTION OF GRAPHIC MATERIALS

[0058] In FIG. Figure 1 shows an example of a system for hardware-accelerated generation of a K-dimensional graph.

[0059] In FIG. Figure 2 shows a block diagram of an example of a method for hardware-accelerated generation of a K-dimensional graph.

[0060] In FIG. Figure 3 shows a block diagram of another example of a method for hardware-accelerated K-dimensional graph generation.

[0061] In FIG. Figure 4 shows an example of a K-dimensional graph.

[0062] In FIG. Figure 5 shows a block diagram of an example of system components that can be used for a hardware-accelerated K-dimensional graph.

DETAILED DESCRIPTION

[0063] The present description relates to hardware-accelerated K-dimensional graph generation. Generating a K-dimensional graph using hardware circuits significantly reduces the time required to generate a K-dimensional graph and offloads the process of generating a K-dimensional graph using a software processor to integrated circuit hardware logic such as a field programmable gate array or ASIC. This frees up software processor resources that can be used to perform other genomic data processing tasks.

[0064] Hardware-accelerated generation of K-dimensional graphs can be achieved using a control device that is configured to control the workflow of operations performed by a plurality of non-pipelined hardware logic units. In particular, the control device may abstractly provide high-level pipelined functionality using multiple non-pipeline hardware logic blocks. The management device may provide this functionality by storing and updating graph description data that includes (i) a K-mer graph identifier that identifies an instance of the K-mer graph, and (ii) information about the state of the K-mer graph. K-dimensional graph state information may include, for example, data indicating the last hardware logic that ran on the source graphs for a particular K-dimensional graph instance, data indicating whether the last block of hardware logic terminated operation, data , indicating the length of the K-mer, data indicating a list of K-mer nodes, data indicating a list of pointers that can be used to identify K-mer nodes in the buffer capacity, the length of a list of K-mer nodes, data including a list of non-unique K-mers measures, or any subset or combination thereof. The control device controls the generation of K-dimensional graphs by calling a specific hardware logic block, which must perform an operation on the original graph data and provide an updated set of graph description data to the called hardware logic block.

[0065] This storage and updating of the graph description data allows the control device to control parallel processing of the non-pipeline hardware logic units in a manner that allows each of the non-pipeline hardware logic units to operate on data corresponding to a separate K-dimensional graph. Accordingly, in addition to the increased speed benefits achieved by using hardware logic instead of executing software instructions to generate K-dimensional graphs, the present disclosure provides further speedup through increased throughput by generating segments of different K-dimensional graphs simultaneously using different hardware logical blocks controlled by a control device.

[0066] In FIG. 1 shows an example system 100 for hardware-accelerated K-dimensional graph generation. In some embodiments, system 100 may include a nucleic acid sequencer 110, a reference sequence database 120, a hardware-accelerated graph generation unit 130, a plurality of hardware logic units 131, 132, 133, 134, 135, 136, 137, 138, a device control 140, hash table buffer capacity 150, DRAM 160, and variant recognizer 180. In some implementations, hardware-accelerated graph generation unit 130 may be implemented using programmable logic circuitry, such as a field programmable gate array (FPGA). In other implementations, the hardware-accelerated graph generation unit 130 may be implemented using an application specific circuit (ASIC). In any scenario, the functionality described with respect to the hardware-accelerated graph generation unit 130 and each of the components implemented thereon is implemented using hardware logic designed to implement the functionality described herein without executing software instructions to implementation of functionality.

[0067] As used herein, the term “block” is used to describe a software module, a hardware module, or a combination thereof that is used to perform a specified function. Determination of whether a particular "block" described herein is hardware, software, or a combination thereof can be made based on the context of its use. For example, an "input block" 131, a "graphics node block" 132, a "graph edge block" 133, etc., in a hardware-accelerated graph generation block 130, which is implemented using an FPGA or ASIC, is a hardware block that functions the capabilities of which are implemented by hardware digital logic gates or hardware digital logic blocks that are arranged to implement the functionality described herein with respect to a particular “block.” As another example, a "variant recognition block 180" that is not implemented using the hardware-accelerated graph generation block 130 shown in FIG. 1 is a software module whose functionality is implemented by one or more computers executing software instructions that define the functionality of the “variant recognition unit 180.” As another example, a computer or processing unit may be a hardware device that implements functionality by processing software instructions, and thus the functionality of the computer or processing unit is a combination of hardware and software.

[0068] Although examples of one or more components shown in FIG. 1 are represented herein as hardware implementations such as "control device" 140, as "control device" is shown in FIG. 1 as implemented in a hardware-accelerated graph generation unit 130, the present description is not limited to such examples. Instead, other embodiments may be used in which the "control device" 140 is implemented in software as a software module or a combination of hardware and software with a computer or processing unit executing software instructions to implement the functionality of the "control device" described herein. 140. Likewise, embodiments of the present disclosure are possible in which certain components described as software with reference to FIG. 1, such as the “variant recognition unit 180” are implemented as a hardware implementation.

[0069] The nucleic acid sequencer 110 is a device configured to perform primary analysis. The primary analysis may include placing in the nucleic acid sequencer 110 a biological sample 105, such as a blood sample, tissue sample, sputum, or nucleic acid, and the nucleic acid sequencer 110 generating an output, such as one or more reads 112, each of which represents an order nucleotides of the nucleotide sequence of the obtained biological sample. In some embodiments, sequencing by the nucleic acid sequencer 110 can be performed over multiple read cycles, wherein a first read cycle generates one or more first reads comprising a base recognition sequence representing the order of nucleotides from the first end of the nucleotide sequence fragment, and a second the read cycle generates one or more corresponding second reads including a base recognition sequence representing the order of nucleotides at other ends of one of the nucleotide sequence fragments. In some embodiments, reads can be generated using clonal amplification. In the example shown in FIG. 1, one or more reads 112 may include a set of reads for a particular reference genome location, wherein the reference genome location consists of a plurality of sequential reference genome locations.

[0070] Thus, each read represents data that represents part of a nucleic acid genome for an organism such as an animal, insect, plant, or the like. Assuming that short fragments of nucleotide sequence have approximately 600 base recognitions, the first read may represent 150 ordered nucleotides for the first end of the fragment of nucleotide sequence, and the second read may represent 150 ordered nucleotides of the other end of the fragment of nucleotide sequence. However, these numbers are just examples, and any nucleic acid sequencer 110 may be configured to generate reads that can be performed by a hardware-accelerated graph generation unit as described herein using any sequencing methods. Such reads may have a length different from the lengths mentioned herein. For example, in some embodiments, the present disclosure can be used to generate hardware-accelerated K-mer graphs for reads obtained by nucleotide sequence fragments having up to 1000 nucleotides or more, with each read having, for example, 50 base recognition, 75 base recognition, 150 base recognition, 200 base recognition, 300 base recognition, 500 base recognition or more from the end of each fragment. Each base recognition can correspond to a nucleotide. The present description can also be used to construct hardware-accelerated K-dimensional graphs for long reads. Accordingly, hardware-accelerated graph generation unit 130 can be used to generate K-mer graphs for any reads generated in any manner by any type of nucleic acid sequencer.[0071] In some embodiments, the biological sample 105 may include a DNA sample, and the nucleic acid sequencer 110 may include a DNA sequencer. In such embodiments, the order of sequenced nucleotides in the read produced by the nucleic acid sequencer may include one or more of guanine (G), cytosine (C), adenine (A), and thymine (T) in any combination. In some embodiments, the nucleic acid sequencer 110 can be used to sequence RNA samples. In some embodiments, this may occur using RNA-seq protocols. As an example, an RNA sample can be preprocessed using reverse transcription to form complementary DNA (cDNA) using the enzyme reverse transcriptase. In other embodiments, the nucleic acid sequencer 110 may include an RNA sequencer, and the biological sample may include an RNA sample. Accordingly, although in the example shown in FIG. 1 describes a nucleic acid sequencer that produces reads consisting of G, C, A and T generated by the DNA sequencer from a DNA sample, the present description is not limited to this. Instead, in other embodiments, the process may process reads consisting of C, G, A, and Y that are produced by an RNA sequencer from an RNA sample. In some embodiments, the DNA reads or RNA reads generated by the nucleic acid sequencer may include a base recognition N, wherein N indicates an unknown base recognition generated by the nucleic acid sequencer.

[0072] In some embodiments, nucleic acid sequencer 110 may include a next generation sequencer (NGS) that is configured to generate sequence reads, such as read 112, for a given sample in a manner that provides ultra-high throughput, scalability, and speed through the use of massively parallel sequencing technologies. NGS allows the rapid sequencing of entire genomes, the ability to study sequenced target regions in depth, the use of RNA sequencing (RNA-Seq) to discover new RNA variants and splice sites or quantify mRNA for gene expression analysis, and the analysis of epigenetic factors such as DNA methylation in genomic scales and DNA-protein interactions, sequencing tumor samples to study rare somatic variants and tumor subclones, and studying microbial diversity in humans or the environment.

[0073] The nucleic acid sequencer 110 may obtain the reference genome 122 from the reference genome database 122. In some embodiments, only a portion of the reference genome 122 is obtained. The obtained portion of the reference genome 122 may correspond to reference locations of the reference genome 122 to which the set of reads 112 is mapped and aligned. The reference genome database 122 may include a data store that organizes storage of many different reference genomes. In some embodiments, a particular reference genome 122 selected from a database of reference genomes may be based on the type of DNA sample 105. In some embodiments, the type of selected reference genome 122 selected from the reference genome database 120 may be selected based on input from the user of the nucleic acid sequencer 110. In such embodiments, the user may, for example, select a reference genome identifier 120, which can be used by the nucleic acid sequencer 110 to select a specific reference genome 122 from the reference genome database 120. Reference genome 122 may include, for example, a nucleotide sequence assembled as a representative example of a set of genes for a particular species.

[0074] A combination of the set of reads 112 generated by the nucleic acid sequencer 110 and the resulting reference genome 122 may be provided as input to a hardware-accelerated graph generation unit 130 . These input data may be processed by one or more hardware logic blocks 131-138 of the hardware-accelerated graph generation unit 130 to generate a K-dimensional graph instance. For example, each hardware logic block of the hardware logic blocks 131-138 may be configured to perform corresponding operations for each read from the set of reads 112 included as input to the hardware-accelerated graph generation block 130.

[0075] Described herein is the system 100 shown in FIG. 1, including a nucleic acid sequencer. In some embodiments, such as those described with reference to FIGS. 1, the system may include a sequencer 110, a hardware-accelerated graph generation unit 130, and other components of the system 100 may be integrated into the nucleic acid sequencer 110. However, the present description is not limited to the integration of 110 nucleic acids into the sequencer. Instead, in some embodiments, the hardware-accelerated graph generation unit 130 may be implemented in a programmable logic device or ASIC integrated or housed in a computer remote from the nucleic acid sequencer 110 and communicatively coupled to the nucleic acid sequencer 110, e.g. one or more wired or wireless networks. Likewise, database 120, variant recognition unit 180, or both may be implemented outside of the nucleic acid sequencer. 110. Likewise, the system 100 does not need to include a nucleic acid sequencer 110 at all. Instead, in some embodiments, the hardware-accelerated graph generation unit 130 and other components shown in FIG. 1 may be implemented on a computer system that does not include a nucleic acid sequencer 110. In such embodiments, the hardware-accelerated graph generating unit may obtain a set of reads 112, reference sequence 122, or both via a network from the storage location(s) of one or more storage devices or the like. Accordingly, system 100 depicts an example of the present description, but does not limit the present description to any particular configuration of system components.

[0076] One or more hardware logic blocks of the hardware-accelerated graph generation block 130 may include an input block 131, a graph node block 132, a graph edge block 133, a backpropagation block 134, a loop block 135, a pruning block 136, a block 137 graph output and destruction block 138. In some implementations, generating a K-dimensional graph using a hardware-accelerated graph generation block 130 may include a control device 140 activating and configuring each of the hardware logic blocks 131-138 to perform corresponding hardware logic operations on a set of data stored in the buffer. capacity 150 or DRAM 160. In other implementations, control device 140 may activate and configure only a subset of hardware logic blocks 131-138 to perform their respective hardware logic operation on a set of raw graphics data stored in buffer capacity 150 or DRAM 160.

[0077] As an example, in some embodiments, hardware-accelerated graph generation unit 130 may be used to generate a specialized form of the de Bruijn graph. This specialized form of the de Bruijn graph can be optimized such that the graph represents non-unique K-mers using a set of corresponding nodes, each with one edge, rather than being represented by a single node with many edges. This can be achieved in part by using a graphics block 132 to identify non-unique K-mers and mark non-unique K-mers for further processing. A non-unique K-mer can be defined as a sequence of K-mers that occurs at least twice in any one read or at least twice in a reference sequence. Unique K-mer in the same

reading occurs at most once, but can still occur on multiple reads.

[0078] However, in other implementations it is possible to create de Bruijn graphs without distinguishing between unique and non-unique K-mers. Thus, in some implementations, a graph node block 132 that can identify non-unique K-mers need not be implemented. In yet another example, backpropagation unit 134 does not need to be used to generate all K-dimensional graphs. Instead, backpropagation unit 134 may be limited to implementations in which it may improve performance. As an example, backpropagation block 134 can be used to improve the quality of edge masses in future transformation of the generated K-dimensional graph into a sequence graph.

[0079] An example of K-dimensional graph generation described in relation to the example shown in FIG. 1 shows each hardware logical block 131-138 that can be activated and configured by control device 140. In the present description, each hardware logical block 131-138 is essentially described as being activated by the control device 140, configured by the control device 140 using, for example, graph-describing data stored in the control device 140, obtaining source graphs, executing one or more specific the operations of processing the received source graphs or other data and then updating the source graphs, graph description data, or both embodiments of the present invention have no such limitations. However, the present description is not limited to such embodiments. Instead, in some embodiments, each hardware logical block 131-138 may be configured to execute multiple instances of its corresponding functionality. For example, graph node block 132 may be configured to accept up to 3 separate sets of source graphics data and execute their operations on it simultaneously, loop hardware logic block 135 may be configured to accept up to 3 separate sets of source graphics data and execute them simultaneously on operations, and the PRU can be configured to accept up to 2 separate sets of raw graphics data and perform operations on it simultaneously. The number of distinct sets or raw graphics data, each corresponding to a different K-dimensional graph, that can be received and processed by a particular hardware logic unit 131-138 is limited only by the available hardware resources for the system 100. For example, assuming that sufficient levels are available for use logic units of DRAM and FPGA, the number of separate sets of raw graphics data that can be received and simultaneously processed by hardware logic blocks 131-138 can be more than 3. Likewise, one or more hardware logic blocks 131-138 can be configured to accepting and processing fewer sets of graphics input data simultaneously if such resources are not available or if a particular hardware logic unit is not expected to be significantly used.

[0080] Other implementations do not require only one instance of each hardware logic block 131-138, each configured to simultaneously process separate sets of raw graphics data, each corresponding to a different K-dimensional graph. Instead, in some embodiments, multiple instances of each hardware-accelerated graph generation block 130 may be configured to include multiple instances of one or more hardware logic blocks 131-138. In such cases, control device 140 may be configured to monitor the state and availability of each hardware logic block 131-138, and then activate and configure each hardware logic block to balance processing operations with load on each corresponding hardware logic block. For example, in some implementations, the hardware-accelerated graph generation block 130 may be configured to have 3 instances of the graph node block 132, each configured to receive up to 3 separate sets of raw graph data and perform their operations on them simultaneously, 3 instances graph edge block 133, each of which is configured to receive up to 3 separate sets of source graphics data and simultaneously perform their operations on them, 2 signal backpropagation blocks 134, each of which is configured to receive up to 2 separate sets of source graphics data and simultaneously performing its operations on them, and 3 cyclic blocks 135, each of which is configured to receive up to 2 separate sets of initial graphic data and simultaneously perform its operations on them. The activation/deactivation of each hardware logic block, the configuration of each hardware logic block, the input data for each hardware logic block, the output data from each hardware logic block, and the update of graph description data by each hardware logic block are controlled and directed by the control device 140.

[0081] Input block

[0082] Input block 131 may receive input data that includes a generated set of reads 112 and a selected reference genome 122, which may be referred to herein as raw graphics data. The selected reference genome 122 may include a region of the reference genome. The raw graphics data may include, for example, data processed by one or more hardware logic units 131-138 during generation of a K-dimensional graph instance. While the source graph data includes, for example, generated reads 112 and the selected reference genome 122, the source graph data may also include, for example, K-dimensional nodes generated by graph node block 132, edges generated by graph edge block 133, and etc. Input unit 131 may format the generated reads 112 and the resulting reference genome 122 for storage in DRAM 160. Formatting the generated reads may include, for example, encoding the reads for storage in DRAM 160. In some implementations, encoding the read may include encoding each base recognition, the corresponding nucleotide read, into 4-bit values. For example, A could be coded as 0000, C could be coded as 0001, G could be coded as 0010, T could be coded as 0011, and N could be coded as 0100, where N represents recognition of an unknown base. In some embodiments, the encoded data may also include data that is a MAPQ score, read count, sequence length, SAM tags, base recognition or read nucleotides, one or more read quality indicators other than the MAPQ score, or any combination thereof . The encoded read data can range from a 16-bit value to a 64-bit value or more that describes the read value. The input unit 131 may write the generated reads to the DRAM 160 .

[0083] The control device 140 may detect receipt of the original input data, activate the input block 131, and initialize the graph description data that corresponds to the K-dimensional graph instance to be generated based on the original input data. Activation of input block 131 may include control device 140 sending one or more control messages to input block 131 that cause input block 131 to perform operations determined by the hardware logic of input block 131 with respect to source data provided as input to the block. 131 inputs. In some embodiments, activation of a hardware logic block, such as input block 131, may also include a control device that provides the hardware logic block with graph description data that can be used to configure the hardware logic block to perform its operations. Configuring the hardware logic block may include, for example, providing pointers to buffer storage locations where K-mers are stored, K-mer nodes providing information describing the length of the K-mer, etc., on which the hardware is to operate. logical block.

[0084] Initializing the graph description data may include, for example, the control device 140 generating a K-dimensional graph identifier for the original input data, generating a graph state information data structure, or a combination thereof. A K-dimensional graph identifier includes a data string of one or more characters, one or more numbers, or a combination thereof, which can be used to identify an instance of the K-dimensional graph during the K-dimensional graph generation process from the time the initial graph data is received by the block 131 input until at least the time of using the destroy block 138 to remove data related to the K-dimensional graph identifier from the buffer capacity 150, DRAM 160, or both after the K-dimensional graph has been completely created for a particular set of source graphics data. In some implementations, the K-dimensional graph identifier may include a number, such as a 6-bit number having a value in the range 0-63. In some implementations, the K-dimensional graph identifier may even be used to reference the K-dimensional graph after using a kill block to remove the aforementioned data from buffer capacity 150, DRAM 160, or both. A graph state data structure is a data structure having one or more fields that store data describing the current state of a K-dimensional graph instance to be generated for a particular set of original input data. The status information may include, for example, data indicating the last hardware logic that operates on the source graphs for a particular case of a K-dimensional graph, data indicating whether the last block of hardware logic has terminated operation, data indicating the length of K -measure, data indicating a list of K-mer nodes, data indicating a list of pointers that can be used to identify K-mer nodes in a buffer capacity, length of a list of K-mer nodes, data including a list of non-unique K-mers, data, indicating the locations of the original input data in the buffer capacity or DRAM, data indicating the base address in DRAM for nodes of the K-dimensional graph instance, or any subset or combination thereof.

[0085] Input block 131 may format input reads 112 and reference genome 122 and write input reads 112 and reference genome to DRAM 160. Control device 140 may determine when input block 131 has completed formatting and writing input reads 112 and reference genome 122 to DRAM. 160. Upon detection by control unit 140 that formatting has completed and writing of input reads 112 and reference genome 122 to DRAM, control device 140 may update graph state information to indicate that input unit 131 has completed operations on the first raw graph data for the first instance of the K-dimensional graph.

[0086] After the first raw graphics data has been entered, formatted, and stored in DRAM 160, control device 140 may determine the next hardware logic unit to be enabled and configured next. For example, control device 140 may activate and configure graph node block 132 to generate K-mer nodes based on a portion of the reference genome 122 and a set of reads formatted and stored in DRAM 160 .

[0087] Graph node block

[0088] Controller 140 may activate and configure graph node block 132 to continue generating the first instance of the K-dimensional graph by processing formatted reads 112 and reference genome 122 stored in DRAM. This may include, for example, sending a control signal to graph node block 132, providing graph description data to graph node block 132, or a combination thereof. The graph description data may be used to configure the graph node block 132 for operation. For example, providing graph description data to and from graph node block 132 from control device 140 may result in configuring graph node block 132 to identify K-mers of a certain size that is determined by the graph description data. Likewise, other graph description data fields described herein can be used to configure a hardware logic block, such as graph node block 132.

[0089] Moreover, in substantially parallel manner, the control device 140 may detect that the input unit 131 has received the second original graphics data as input data. The control device 140 may then activate the input block 131, instruct the block 131 to format the reads and the reference genome of the second raw graphics data, and generate a second graphical description data for a second instance of the K-dimensional graph to be generated based on the second raw graphics data. Thus, the control device 140 can provide high levels of throughput by simultaneously controlling the performance of various hardware logic units 131, 132 that perform K-dimensional graph generation processes for different sets of raw graphics data at different stages of processing. The control device 140 is configured to control this parallel function of each of the hardware logic blocks 131, 132, 133, 134, 135, 136, 137, 138, for example, at any given time there may be eight hardware logic blocks that operate with eight different sets of source graphics data, and the hardware-accelerated graph generation unit 130 operates with the ability to simultaneously generate eight different K-dimensional graphs. The control device 140, using the graphical description data, controls this process at all times by activating and configuring each respective hardware logic block to achieve the abstract high-level pipelined functionality of the non-pipeline hardware logic blocks 131, 132, 133, 134, 135, 136, 137. 138, which do not have a direct and physical I/O connection between each corresponding hardware logical block. Although an example of eight simultaneous K-dimensional graph generation running simultaneously is illustrated, the present disclosure may be capable of achieving many more simultaneous K-dimensional graph generation, for example, by implementing multiple hardware-accelerated graphs 130 simultaneously, multiple instances of multiple hardware logic blocks on one or more hardware-accelerated graph generation units 130 or combinations thereof.

[0090] The graph node block 132 may analyze each read of the read set 112 to identify each of the K-mers of the read. This may include, for example, sliding the K-mer access window along each position of each read to identify each specific K-mer of the corresponding read. Graph node block 132 may store data representing a K-dimensional graph node for each identified K-mer of each read in buffer capacity 150. Likewise, graph node block 132 may also generate and store in DRAM a list of node pointers in a node pointer data structure. , with each node pointer pointing to the location of a buffer capacity in a K-dimensional node. The graph node unit 132 may also generate and store information indicating the location and length of the node list for each K-dimensional graph in the graph description data stored by the control device. These pointers may be used as graph state information by control device 140 to configure another hardware logic block during a subsequent portion of the K-dimensional graph generation process. Buffer capacity 150 may employ one or more buffer capacity coherence policies, such as an LRU buffer capacity coherence policy configured to take advantage of the oldest objects of buffer capacity 150, with the oldest objects being determined based on the time the object was written to buffer capacity 150.

[0091] An example of data generated by graph node block 132 and stored in buffer capacity 150, DRAM 160, or both is shown with reference to FIG. 4. In FIG. Figure 4 shows part of the reference genome 410, read 420 and de Bruijn graph 400. The de Bruijn graph 400, which is described in more detail below, includes a node for each K-mer in a region of the genome 410 and a read 420 and an edge between each pair of K-mer nodes connecting a pair of nodes having k-1 overlapping nucleotides.

[0092] As shown in the example of FIG. 4, the graph node block 132 may generate, based on receiving part of the reference genome 410 and reading 420, data representing nodes 431, 432, 433, 434, 435, 436, 437, 438 of the first path 430 of the de Bruijn graph 400 and nodes 441, 442, 443, 444. First, the graph node block 132 may align overlapping regions of the reference genome 410a, 410b and overlapping read regions 420a, 420b to identify overlapping regions, as shown in FIG. 4. The graph node block 132 can identify each of the K-mers of the genome region 410 and reads 420. This can be achieved using an access window of length k, which is 4 in this example, at the first position of the reference genome region 410 spanning the K-mers. identified by the access window, generating data representing a graph node that includes the captured K-mer, storing data representing the node in buffer capacity 150, advancing the access window one nucleotide, and then repeating this process iteratively. In this example, the graphical node block 132 can identify the K-mers ATCG, TCGC, CGSSSS, GCCT, CCTA, CTAG, TAGA and AGAAA for the reference genome region 410 and generate the corresponding node 431, 432, 433, 434, 435, 436, 437, 438, with one of these nodes corresponding to the corresponding K-measure. Each node is created such that it has a length k, which in this example is 4, and has a number of k-1 overlapping K-mers with the next neighboring node. The graph node block 132 may store the generated nodes in a buffer capacity 150, a DRAM 160, or both. In some embodiments, the buffer capacity may include a hash table buffer capacity. In such implementations, nodes may be stored as hash table keys. The graph node block 132 may store data describing the locations of K-dimensional nodes in the graph description data stored by the control device 140.

[0093] The graph node block 132 may perform the same operations for the read 420. With respect to the read 420, the graph node block 132 may identify the K-mers ATCG, TCGS, CGSG, GCTG, CGTA, GTAG, TAGA, and AGAA. Similarly, this can be achieved by using an access window of length k, which in this example is 4, at the first position of the read portion 420, capturing the K-mer identified by the access window, and then advancing the access window and repeating the process. The graph node block 132 may begin by identifying each K-mer for a region of the genome 410. In some implementations, the graph node block 132 may generate a corresponding node for each of the K-mers. In other embodiments, graph node block 132 may generate only 431, 432, 433, 434, 435, 436, 437, 438 corresponding to identified K-mers that are different from the K-mer nodes of the reference genome region 410. In each scenario, each node is created such that it has length k, which in this example is 4, and has a number of overlapping k-1 K-mers with the next neighbor node. This may continue until a node for each K-mer region of the reference genome 410 is created and stored in buffer capacity 150 or DRAM 160.

[0094] In some implementations, graph node block 132 may also be configured to identify non-unique K-mers. In such embodiments, graph node block 132 may, for each particular read of the first set of reads, determine whether the identified K-mer is a unique K-mer or a non-unique K-mer. If graph node block 132 determines that a particular K-mer is a unique K-mer, then graph node block 132 may advance the access window one nucleotide to evaluate the next K-mer. Alternatively, if the graph node block 132 determines that a particular K-mer is a non-unique K-mer, then the graph node block 132 may store data indicating that the particular K-mer is a non-unique K-mer. For example, graph node block 132 may store a data label in graph description data stored by a management device for a particular K-dimensional graph instance indicating that the K-mer is a non-unique K-mer. However, such data may be stored in any other component of the hardware-accelerated graph generation unit 130, stored in any other memory unit of the hardware-accelerated graph generation unit 130, or a combination thereof. Subsequent hardware logic units can then perform operations that affect the non-unique K-mer to reduce or eliminate cycles in the K-dimensional graph instance.

[0095] At this point in the process, graph node block 132 stores data representing a K-dimensional graph node for each K-mer in buffer capacity 150, DRAM 160, or both. Thus, the hardware-accelerated graph generation unit 130 has not yet generated the edges 431a, 432a, 433a, 434a, 435a, 436a, 437a, 432b, 441a, 442a, 443a, 444a, graph edge masses, or the like. These features of a given K-dimensional graph instance may be generated using one or more other hardware logic blocks of the hardware-accelerated graph generation unit 130.

[0096] The control device 140 may monitor the operation of the graph node block 132. After graph node block 132 generates data representing a K-mer node for each K-mer of each read of the first raw graph data for that first K-dimensional graph instance, the control device may update the graph description data to indicate that the hardware-accelerated The graph generating unit 130 has completed the operations of the graph unit 132 on the first raw graph data. In addition, manager 140 may also store graph description data, which includes, for example, a label identifying each of the non-unique K-mers, storage locations for K-dimensional graph nodes, and data indicating completion of operations by graph node block 132 .

[0097] After generating and storing 150 K-dimensional graph nodes in the buffer capacity, control device 140 can determine the next hardware logic block to be activated and configured next. For example, control device 140 may activate and configure graph edge block 133 to generate, weight, or both graph edges between pairs of nodes.

[0098] Graph edge block

[0099] The graph edge block 133 may generate graph edges between pairs of K-dimensional nodes generated by the graph node block 132. The control device 140 may activate the graph edge block 133 after determining that the graph node block 132 for the first instance of the K-dimensional graph is completed and that the graph edge block 133 is available. In some embodiments, control device 140 may provide or otherwise provide access to graph edge block 133 locations storing K-dimensional graph nodes generated by graph node block 132 for a particular K-dimensional graph instance. For example, control device 140 may access K-dimensional graph description data generated and stored by graph node block 132 during the process of generating K-dimensional nodes for a K-dimensional graph instance. Available K-mer graph data may specify or otherwise describe a list of K-mers.

[000100] After edge block 133 receives a K-dimensional graph node location graph for the first instance of the K-dimensional graph, the graph edge block may begin generating one or more graph edges between the data representing the K-dimensional nodes. In some embodiments, graph edge block 133 may access data representing a graph node for each of the K-mers of a particular read from the hash table buffer capacity. The graph edge block 133 may generate data representing a graph edge between graph nodes for K-mers for storage in a hash table buffer. For example, data representing a graph edge may be stored in a hash table buffer as part of the graph node entry for the source edge node. In some embodiments, graph edge block 133 may assign a mass to each edge of the K-dimensional graph. For example, graph edge block 133 may add +1 or another mass for each instance of a graph edge connecting a corresponding pair of K-mers.

[000101] As an example, graph edge block 133 may identify nodes using graph description data received from control device 140 that are neighboring nodes. Nodes can be determined to be neighboring nodes based on various factors, including determining that the nodes share k-1 overlapping nucleotides and that the nodes are observed at two consecutive positions of the sliding K-mer access window. For example, graph edge block 133 may move the K-mer access window along each position of each read of the original graph data. In some implementations, the graph edge block 133 may create an edge or increase the edge mass upon determining that two consecutive K-mers are observed in the read, overlapping all but one base. Graph node 133 creates an edge or increases edge mass in such a scenario, since this scenario involves an edge between graph nodes corresponding to these two consecutive K-mers.

[000102] In some implementations, data representing the nodes of the graph may be stored as hash keys of a hash table. In such embodiments, graph edge block 133 may generate an edge from a first node (or hash key) to a second node (or hash key) by accessing the hash position from which the first node (or hash key) is mapped and generating a pointer to store at a hash location that points to the second node (or hash key). Subsequent edges can be generated in the same manner, creating a path 430 or 440 through the graph that can be traversed using one or more graph traversal algorithms.

[000103] As shown in the example of FIG. 4, graph edge block 133 may generate data representing one or more edges between pairs of nodes 431, 432, 433, 434, 435, 436, 437, 438 of the first path 430, pairs of nodes 441, 442, 443, 444 of the second path 440, or one or more pairs of nodes in the first path 430 and the second path 440. An example of these edges is shown in FIG. 4 in the form of edges 431a, 432a, 433a, 434a, 435a, 436a, 437a, 432b, 441a, 442a, 443a, 444a.

[000104] In this example, the sequence of nucleotides 420 is called a read. However, in some embodiments, low-quality base removal may occur such that nucleotide sequence 420 constitutes a contig, or read region. In such implementations, the graph edges connecting a pair of nodes will create a path for only one or more connections within a particular contig, rather than from a K-mer node of the first contig to a K-mer node of the second contig. A contig may include a nucleotide sequence resulting from the removal of a low-quality base.

[000105] Backpropagation block

[000106] The hardware-accelerated graph generation unit 130 may include a signal backpropagator 134 . However, in certain embodiments, control device 140 may activate and configure only backpropagation unit 134. For example, control device 140 may activate backpropagation unit 134 when control device 140 determines that the K-dimensional graph generated by the current set of source graphs will subsequently be converted to a sequence graph. When activated, backpropagation module 134 can receive graph description data from control device 140. In such an implementation, adjustments to the edge masses of the graph can make the masses more reliable when the graph inherits a sequence.

[000107] The graph edge block 133 can create edges between K-mer nodes of contigs by identifying corresponding K-mer nodes in buffer capacity 150, forming an edge connecting the K-mer nodes, and then increasing the edge mass +1 for each case. In some implementations, after adding contig and weighting nodes to the K-mer graph using the graph edge block 134, the signal backpropagation block 134 can be used to backpropagate a +1 increment of k-1 edge mass through a linear chain of graph edges "to the left" of the starting node. contig in a K-dimensional graph. In this context, "to the left" of the start node of a contig in a K-dimensional graph represents the direction of the K-dimensional graph opposite the directional edge of the K-dimensional graph. To illustrate this concept, the “left” of node 434 in de Bruijn graph 400 would be nodes 433, 432, and 431.

[000108] For example, in some embodiments, backpropagation module 134 may access, in a hash table buffer, data representing a K-dimensional graph, including its K-dimensional nodes, corresponding graph edges, or the like, and then adjust edge masses for K-1 nodes that occur before the start of the new contig. Backpropagation unit 135 may determine appropriate K-dimensional nodes and edges for adjustment based on graph description data received from control device 160, which includes pointers to buffer locations storing this information. The graph description data can be updated with any changes that occur during signal backpropagation.

[000109] In some embodiments, it may be useful to perform the above signal backpropagation since the N-base contig may only increase the series of edge masses (N-K). However, if this K-dimensional graph is later transformed into a sequence graph with (N-1) inner edges corresponding to this contig, then the first (K-1) edge masses do not inherit the incremented edge masses properly. The above backpropagation solves most cases of this problem. Thus, backpropagation can be used to solve this problem to improve the reliability of inherited edge masses when transforming a K-dimensional graph into a sequence graph.

[000110] Cyclic block

[000111] The hardware-accelerated graph generation unit 130 may include a loop block 135. In some embodiments, the loop unit 135 may be enabled and configured by the control device 140 to detect loops in the case of a K-dimensional graph. For example, loop block 135 may evaluate K-dimensional nodes and K-dimensional edges of the raw graphics data of a K-dimensional graph instance generated by one or more of input block 131, graph node block 132, graph edge block 133, and backpropagation block 134. The cyclic block 135 is configured to receive graph description data from the control device 140. Loop block 135 may iteratively mark header nodes for removal. The top node may include a node that does not include any inner edges. Where the inner edge is the edge that is directed from the first node to the very first node. After each cap node is marked for deletion, loop block 135 may determine whether any nodes that are directed toward the outer edge become cap nodes as a result of the node being deleted. If such nodes are identified, they are marked for deletion. An outer edge is an edge of the graph that points from the first node to another node. The loop block 135 may continue this process until there are no header nodes left.

[000112] After determining that there are no header nodes remaining, loop block 135 may determine whether the graph is empty, where an empty graph means that all nodes in the graph are marked for deletion. If the graph without a header is empty, then there is no cycle. Alternatively, if the unheaded graph is not empty, then the graph must contain a cycle. Loops are resistant to this type of deletion because no node in the loop becomes a head node by deleting nodes outside the loop.

[000113] After making any of these determinations, loop block 135 may provide control device 140 with an indication of whether a loop has been detected. Then, based on the indication provided by the cyclic block 135, the control device 140 can determine which hardware logic block should then be activated and configured. For example, if a loop has been detected and generation of a K-dimensional graph instance needs to be aborted, then control device 140 may activate and configure kill block 138. In such cases, the destroy unit may remove raw graphics data from buffer capacity 150 and DRAM 160 corresponding to the interrupted K-dimensional graph instance. If, in an alternative embodiment, it is necessary to continue generating the K-dimensional graph instance, then control device 140 may activate and configure another hardware logic block to perform subsequent operations on the original graphics data to generate the K-dimensional graph instance. For example, if it is necessary to continue generating a K-dimensional graph, the control device 140 can either activate or configure the pruning unit 136 or the graph output unit 137.

[000114] Although hardware-accelerated graph generation block 130 may use round-robin block 135 to detect cycles in the case of a K-dimensional graph being generated, round-robin block 135 can be selectively enabled and implemented similarly to backpropagation block 134. This is because some kinds of K-dimensional graphs may include cycles. However, for certain types of K-dimensional graphs, it may be useful to not have graphs with cycles. Accordingly, hardware-accelerated graph generation block 130 may be configured, for example, to receive input from control device 140 indicating whether loop block 135 should be executed for a particular graph instance.

[000115] Cut block

[000116] The hardware-accelerated graph generation unit 130 may include a pruning unit 135. Like backpropagation block 134 and cyclic block 135, cutoff block 136 can be selectively activated and configured by control device 160. When activated and configured, the pruning unit 135 can estimate the mass of each graph edge in the raw graph data for the K-dimensional graph instance generated at that time by the hardware-accelerated graph generation unit 130. In some implementations, if pruning block 136 determines that the mass value of a graph edge does not satisfy a predetermined threshold, pruning block 136 may remove the graph edge and any K-dimensional node that occurs after the identified graph edges. Alternatively, if pruning block 136 determines that the mass value of a graph edge satisfies a given threshold, then pruning block 136 will leave the graph edge untouched.

[000117] In other implementations, pruning unit 136 may identify linear chains, wherein linear chains represent maximal paths through the graph such that all internal nodes between a start node and an end node have exactly one inside edge and one outside edge. In such embodiments, pruning unit 136 may determine whether each inner edge of the linear circuit fails to satisfy a pruning threshold. If such a scenario occurs, pruning block 136 may remove the entire linear chain, including all internal edges and all internal nodes, except for the start node and/or end node of the chain, which pruning block 136 may retain if they have any non-internal edges.

[000118] Graph output block

[000119] The hardware accelerated graph generation unit 130 may include a graph output unit 137 . The graph inference block 137 may be used by the hardware-accelerated graph generation block 130 to generate the final version 170 of a K-dimensional graph instance since the K-dimensional graph instance is described by graph and buffer capacity data. For example, graph output unit 137 may obtain data representing a K-dimensional graph from hash table buffer 150 using graph description data that includes, for example, location indicators in hash table buffer 150 that store K data. -dimensional graph. The graph output unit 137 may then pass the data obtained from the hash table buffer 150 describing the final version of the K-dimensional graph 170 to the variant recognition unit 180 . The variant recognition unit 180 may perform variant recognition analysis on the final version of the K-dimensional graph 170 to create a set of variants 190. The set of variants 190 may include one or more candidate variants. A variant is a change in the genomic data of an organism. The candidate is determined by the variant recognition block, which is inferred by the variant recognition block based on processing of the K-dimensional graph 170. In some implementations, the candidate may have a threshold level of error in determining the variant.

[000120] Variant recognition block 180 may identify potential variants by processing the K-dimensional graph 180. In some embodiments, for example, variant recognition block 180 may identify a potential variant when the base recognition or nucleotide of one or more reads in a read set and the nucleotide of the reference genomes differ at a specific location in the reference genome. Data describing the set of options 190 may be generated or determined in any number of ways. For example, some implementations may perform variant recognition operations as described in more detail in, for example, US Publication No. 2016/0180019, US Publication No. 2016/0306922, and US Publication No. 2019/-0259468, the contents of each of which are incorporated herein in their entirety. document by reference. Data describing the set of options 190 may be provided for output in several different ways. For example, data describing the set of variants 190 may be displayed on the display of the nucleic acid sequencer 110, displayed on the display of another computer, output as audio through one or more speakers of the computing device, output through a printer, or any combination thereof.

[000121] Kill block

[000122] The destroy block 138 can be used to perform memory recovery tasks upon completion and output of the K-dimensional graph instance by the hardware-accelerated graph generation block 130 . For example, the destroy block may delete all original graphics data associated with a particular K-dimensional graph instance that is completed and output by the hardware-accelerated graph generation block 130. In an alternative or additional embodiment, the destroy unit 138 may delete all data related to a particular instance of the graphics block 130 that is stored by the control device, delete all data related to a specific instance of the graphics block 130 that is stored in the DRAM 160, or the like. Accordingly, the destroy unit 138 may selectively remove data representing graph nodes and data representing edges of the K-dimensional graph from the hash table buffer capacity. This removal is selective because only part of the contents of the buffer, control device, or DRAM needs to be removed. Moreover, when the graph is stored as a hash table, the hash table can often be sparsely populated, and for kill block 138 it is faster to selectively destroy only busy hash table entries than to clear the entire hash table, resulting in improved performance.

[000123] However, in some implementations, the non-hash table data associated with the graph need not be removed one at a time. In such embodiments, destroy block 138 may specify a list length of zero in the graph description data, or the allocated memory space may simply be freed for reuse without deleting the contents.

[000124] In FIG. 2 is a block diagram of an example method 200 for hardware-accelerated K-dimensional graph generation. Typically, method 200 may include obtaining a first set of nucleotide sequences, wherein the first set of nucleotide sequences includes (i) a plurality of reads corresponding to the active region of a reference sequence, and (ii) a portion of the reference sequence (210) generating a K-mer a graph using the resulting first set of nucleotide sequences and using a plurality of non-pipelined hardware logic blocks of a programmable logic device, each hardware logic block comprising a separate hardware logic circuit configured to perform one or more operations, each node of the K-dimensional graph representing K -mer, each edge of the graph represents the relationship between a pair of K-mers, and each mass of each edge of the K-mer graph represents the number of occurrences of the sequence of K-mers represented by a pair of K-mers (220) during K-mer graph generation: periodic updating, by the control device, graph description data for the K-dimensional graph after performing one or more operations by each hardware logic unit that is used to generate at least a portion of the K-dimensional graph, wherein the graph description data is (i) an identifier K -dimensional graph and (ii) K-dimensional graph state information, wherein the control device creates a workflow of operations using the non-pipelined hardware logic blocks by causing execution of one or more operations of each corresponding hardware logic block during generation of the K-dimensional graph (230) and providing the K-dimensional graph to a variant recognition module, wherein the variant recognition module processes the K-dimensional graph to determine one or more potential variants between one or more of the plurality of reads and a reference sequence.

[000125] In FIG. 3 is a block diagram of another example of a hardware-accelerated K-dimensional graph generation method 300. Typically, process 300 may include obtaining a first set of nucleotide sequences, wherein the first set of nucleotide sequences includes (i) a plurality of reads corresponding to the active region of a reference sequence, and (ii) a portion of the reference sequence (310) for each specific nucleotide sequence from the first set of nucleotide sequences: generating for storage in a buffer capacity a hash table and the first hardware logical block of data representing a graph node for each K-mer of a particular nucleotide sequence (320), detecting by the control device that the first hardware logical block has completed generating the node graph for each K-mer of a particular nucleotide sequence (330), the control device configuring a second hardware logic unit to perform graph edge generation for the generated graph nodes (340) and for one or more pairs of generated node graphs: generation by the second hardware logic units and for storage in a graph hash table, data representing graph boundaries between one or more pairs of generated graph nodes generated by the first hardware logic unit, wherein data representing a graph node for each K-mer stored in a buffer capacity of the hash table, and data representing the edges of the graph, stored in the buffer capacity of the hash table, represent the K-mer graph of the first set of nucleotide sequences (350).

[000126] In FIG. 4 shows an example of a K-dimensional graph 400. In this example, the K-dimensional graph is a graph 400 generated based on at least a portion of the reference genome 410 and a read 420. In this example, the K-dimensional graph 400 is a de Bruijn graph.

[000127] A K-dimensional graph 400 is generated using a plurality of nodes and one or more edges between pairs of nodes. Each node represents a K-mer of length k, with k=4 in this example. Each edge provides an indication of the presence of k-1 nucleotide overlap of the K-mers connected by the edge. In K-mer graph 400, path 430 includes a plurality of nodes and edges representing each K-mer region of the reference sequence 410. Path 440 also includes a plurality of nodes and edges representing read regions 420 that differ from the region of the reference genome 410.

[000128] In FIG. 5 is a block diagram of an example of system components 500 that may be used for a hardware-accelerated K-dimensional graph.

[000129] The computing device 500 should be various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blades, mainframes, and other suitable computers. The computing device 550 should be various forms of mobile devices, such as personal digital assistants, cell phones, smartphones, and other similar computing devices. Additionally, computing device 500 or 550 may include universal serial bus (USB) flash drives. USB flash drives can store operating systems and other applications. USB flash drives may include I/O components, such as a wireless transmitter or a USB connector that can be inserted into a USB port on another computing device. The components, their connections and relationships, and their functions presented herein are examples only and are not intended to limit the embodiments described and/or claimed herein.

[000130] Computing device 500 includes a processor 502, memory 504, storage device 506, a high-speed interface 508 coupled to memory 504 and high-speed expansion ports 510, and a low-speed interface 512 coupled to low-speed bus 514 and storage device 506. Components 502, 504, 506, 508, 510 and 512 are all connected to each other using various buses, and can be mounted on a common motherboard or in other ways if necessary. Processor 502 may process instructions intended to be executed on computing device 500, including instructions stored in memory device 504 or storage device 506, to display graphical user interface information on an external input/output device, such as display 516 coupled to a high-speed interface 508. In other embodiments, multiple processors and/or multiple buses may be used, along with multiple storage devices and memory types, as needed. Additionally, multiple computing devices 500 may be connected, with each device providing a site of required operations, such as a bank of servers, a bank of blade servers, or a multiprocessor system.

[000131] Information in memory 504 is stored in computing device 500. In one embodiment, memory 504 is a block or blocks of volatile memory. In another embodiment, memory 504 is a block or blocks of non-volatile memory. Memory 504 may also be another form of computer-readable media, such as a magnetic or optical disk.

[000132] Storage device 506 is configured to provide large storage capacity for computing device 500. In one embodiment, storage device 506 may be or comprise computer-readable media, such as a floppy disk device, a hard disk device, an optical disk device, or a tape device, flash memory, or other similar solid-state storage device or array of devices, including devices in a storage area network or other configurations. The computer program product may be practically implemented on a storage medium. The computer program product may also contain instructions that, when executed, perform one or more methods such as those described above. The storage medium is a computer-readable or machine-readable medium, such as memory 504, storage device 506, or memory on processor 502.

[000133] A high-speed controller 508 manages high-bandwidth operations for computing device 500, and a low-speed controller 512 manages lower-bandwidth operations. This distribution of functions is just an example. In one embodiment, high-speed controller 508 is coupled to memory 504, display 516, such as through a graphics processor or accelerator, and high-speed expansion ports 510 into which various expansion cards (not shown) can be installed. In an embodiment, low-speed controller 512 is coupled to storage device 506 and low-speed expansion port 514. The low-speed expansion port, which may include various communications ports, such as USB, Bluetooth, Ethernet, wireless Ethernet, may be connected to one or more input/output devices, such as a keyboard, pointing device, microphone/speaker pair, scanner, or a network device such as a switch or router, such as a network adapter. Computing device 500 may be implemented in several different forms, as shown in the figure. For example, it may be implemented as a standard server 520 or multiple times as a group of such servers. It may also be implemented as part of a rack server system 524. Additionally, it may be implemented on a personal computer such as a laptop 522. In an alternative embodiment, components of the computing device 500 may be combined with other components in a mobile device (not shown) such as device 550. Each of such devices may contain one or more computing devices 500, 550, and the entire system may consist of a plurality of computing devices 500, 550 communicating with each other.

[000134] Computing device 500 may be implemented in several different forms, as shown in the figure. For example, it may be implemented as a standard server 520 or multiple times as a group of such servers. It may also be implemented as part of a rack server system 524. Additionally, it may be implemented on a personal computer such as a laptop 522. In an alternative embodiment, components of the computing device 500 may be combined with other components in a mobile device (not shown) such as device 550. Each of such devices may contain one or more computing devices 500, 550, and the entire system may consist of a plurality of computing devices 500, 550 communicating with each other.

[000135] Computing device 550 includes a processor 552, a memory 564, and an input/output device such as, but not limited to, a display 554, a communications interface 566, and a transceiver 568. The device 550 may also be provided with a storage device such as a microdrive or other device to provide additional storage capacity. The components 550, 552, 564, 554, 566, and 568 are all connected to each other using various buses, and some of the components may be mounted on a common motherboard or in other ways, as appropriate.

[000136] Processor 552 may execute instructions contained in computing device 550, including instructions stored in storage device 564. The processor may be implemented as a chipset, including individual and multi-component analog and digital processors. In addition, the processor may be implemented using any of a number of architectures. For example, processor 510 may be a CISC (full instruction set computing) processor, a RISC (reduced instruction set computing) processor, or a MISC (minimum instruction set computing) processor. The processor may provide, for example, coordination of other components of device 550, such as managing user interfaces, running applications by device 550, and communicating wirelessly with device 550.

[000137] The processor 552 may communicate with the user through a control interface 558 and a display interface 556 coupled to the display 554. The display 554 may be, for example, a TFT (thin film transistor) display or an OLED (organic light emitting diode) display. ), or other suitable display technologies. The display interface 556 may include suitable circuitry for driving the display 554 and for presenting graphical and other information to the user. The control interface 558 may receive commands from the user and convert them for transmission to the processor 552. Additionally, an external interface 562 may be provided in communication with the processor 552 to provide the device 550 with near-field communications with other devices. In some embodiments, external interface 562 may provide, for example, wired communications, or in other embodiments, wireless communications, and a variety of interfaces may also be used.

[000138] Information in storage device 564 is stored in computing device 550. Storage device 564 may be implemented as one or more computer-readable media or media, a block or blocks of volatile memory, or a block or blocks of non-volatile memory. Additionally, expansion memory 574 may be provided coupled to device 550 via expansion interface 572, which may include, for example, a SIMM (single inline memory module) card interface. Such expansion memory 574 may provide device 550 with additional storage space or may also store applications or other information for device 550. In particular, expansion memory 574 may include instructions to perform or supplement the processes described above, and may also include secure information. Thus, for example, expansion memory 574 may be provided as a secure module for device 550 and may be programmed with instructions that allow device 550 to be used in a secure manner. In addition, SIMM cards can transfer secure applications as well as additional information, such as placing identification information on the SIMM card without the possibility of compromise.

[000139] The memory may include, for example, flash memory and/or NVRAM memory, as described below. In one embodiment, the computer program product is practically implemented on a storage medium. The computer program product contains instructions that, when executed, perform one or more methods such as those described above. The information medium is a computer-readable or machine-readable medium, such as a storage device 564, expansion memory 574, or memory on a processor 552, where the information may be received, for example, through a transceiver 568 or an external interface 562.

[000140] Device 550 may communicate wirelessly through a communications interface 566, which may include circuitry for digital signal processing if desired. The communication communications interface 566 may provide communications in various modes or protocols, such as, but not limited to, GSM voice calls, SMS, EMS or MMS messages, CDMA, TDMA, PDC, WCDMA, CDMA2000, or GPRS. Such data transmission can be accomplished, for example, using radio frequency transceiver 568. In addition, short-range communication is possible, for example, using Bluetooth, Wi-Fi, or another similar transceiver (not shown). In addition, GPS (Global Positioning System) receiver module 570 may transmit additional navigation and location-related wireless data to device 550 that can be used as needed by applications running on device 550.

[000141] Device 550 may also transmit an audio signal using an audio codec 560, which can receive speech information from a user and convert it into usable digital information. Audio codec 560 may also generate an audio signal for the user, for example, through a speaker, such as through the headset of device 550. Such audio signal may be audio from voice telephone calls, may be recorded audio, such as voice messages, music files, and the like. , and may also include audio generated by applications running on device 550.

[000142] Computing device 550 may be implemented in several different forms, as shown in the figure. For example, it may be implemented as a cellular telephone 580. It may also be implemented as part of a smartphone 582, a personal digital assistant, or other similar mobile device.

[000143] Various implementations of the systems and methods described herein may be implemented in the form of a digital electronic circuit, an integrated circuit, custom ASICs (application integrated circuits), computer hardware, firmware, software, and/or as a combination of such implementation options. These various implementations may include implementation in one or more computer programs configured to be executed and/or interpreted on a programmable system including at least one programmable processor, which may be specialized or general purpose, coupled to a storage system to receive data from it. and commands and transmitting data and commands thereto, at least one input device and at least one output device.

[000144] These computer programs (also referred to as programs, software, software applications or code) include machine instructions for a programmable processor and may be implemented in a high-level procedural and/or object-oriented programming language, and/or assembly/machine language . As used herein, the terms “machine readable medium”, “computer readable medium” refer to any computer program product, apparatus and/or device, such as magnetic disks, optical disks, storage media, programmable logic devices (PLDs) used to transmit computer data. instructions and/or data to a programmable processor, including a computer-readable medium, that receives the machine instructions as a computer-readable signal. The term "machine-readable signal" refers to any signal used to convey machine instructions and/or data to a programmable processor.

[000145] To provide user interaction, the systems and methods described herein may be implemented on a computer having a display device, such as a CRT (cathode ray tube) or LCD (liquid crystal) monitor, to display information to the user, and a keyboard and A pointing device, such as a mouse or trackball, that allows the user to provide input to a computer. Other types of devices can also be used to provide user interaction; the feedback provided to the user can be in any tangible form, such as visual feedback, auditory feedback, or haptic feedback; and input from the user may come in any form, including audio, speech, or tactile input.

[000146] The systems and methods described herein may be implemented in a computer system that includes a server component, such as a data server, or includes an intermediate component, such as an application server, or includes a client component (for example, a client computer with a graphical user interface or web browser through which a user can interact with an implementation of the systems and methods described herein), or any combination of such server, middleware, and client components. System components can be interconnected by any form or medium of digital data exchange, such as a communications network. Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.[000147] A computer system may include clients and servers. The client and server are essentially remote from each other and typically communicate through a communications network. The functional dependence of the client and server arises due to computer programs running on the respective computers and having a client-server functional dependence on each other.

[000148] OTHER EMBODIMENTS

[000149] A number of embodiments are described. However, it will be appreciated that various modifications are possible without departing from the spirit and scope of the invention. Additionally, the logical flows depicted in the figures do not require the specific or sequential order shown to achieve the desired results. In addition, other steps may be provided or omitted from the described flows, and other components may be added to or removed from the described systems. Accordingly, the following claims cover other embodiments.

Claims (98)

1. A method for hardware-accelerated generation of a K-dimensional graph representing a set of sequencing reads for variant recognition analysis, including: obtaining a first set of nucleotide sequences generated by the nucleic acid sequencer, the first set of nucleotide sequences including (i) a plurality of reads corresponding to the active region of the reference sequence, and (ii) a portion of the reference sequence; generating, using a plurality of non-pipeline hardware logic blocks of a programmable logic device, a K-dimensional graph using the obtained first set of nucleotide sequences, each hardware logic block comprising another hardware logic circuit configured to perform one or more operations, wherein each node of the K-dimensional graph represents a K-mer, each edge of the K-mer graph represents a connection between a pair of K-mers, and each mass of each edge of the K-mer graph represents the number of occurrences of the sequence of K-mers represented by the pair of K-mers; And in the process of generating a K-dimensional graph: periodically updating, by a manager, graph description data for the K-dimensional graph after one or more operations have been performed by each hardware logic unit that is used to generate at least a portion of the K-dimensional graph, wherein the graph description data is (i) a K-identifier dimensional graph and (ii) K-dimensional graph state information, wherein the control device creates a workflow of operations using the non-pipelined hardware logic blocks by triggering execution of one or more operations of each corresponding hardware logic block during generation of the K-dimensional graph. 2. The method of claim 1, wherein the output data of each hardware logical block of the plurality of hardware logical blocks is stored by a hash table buffer capacity. 3. The method according to claim 1, in which the control device is implemented using a hardware logic block of a programmable logic device. 4. The method of claim 1, wherein the control device is implemented using one or more CPUs or GPUs to execute software instructions to implement the functions of the control device. 5. The method according to claim 1, in which the operations further include: providing a generated K-dimensional graph to the variant recognition unit, wherein the variant recognition unit processes the K-dimensional graph to determine potential variants between one or more of the plurality of reads and a reference sequence. 6. The method of claim 5, wherein the software instructions are executed by one or more CPUs or GPUs to implement one or more functions of the variant recognition unit. 7. The method of claim 5, wherein the programmable logic device is used to accelerate one or more functions of the variant recognition unit. 8. The method of claim 1, wherein the graph description data further includes (iii) data representing the last hardware logic block of a plurality of hardware logic blocks performing hardware logic on the K-dimensional graph or nucleotide sequences associated with the K-identifier dimensional graph. 9. A system for hardware-accelerated generation of a K-dimensional graph representing many sequencing reads for variant recognition analysis, including: nucleic acid sequencer; a hardware-accelerated graph generation unit that includes hardware digital logic circuits configured to perform operations, the operations including: obtaining a first set of nucleotide sequences, the first set of nucleotide sequences including (i) a plurality of reads corresponding to the active region of the reference sequence, and (ii) a portion of the reference sequence; generating, using a plurality of non-pipeline hardware logic blocks of a programmable logic device, a K-dimensional graph using the obtained first set of nucleotide sequences, each hardware logic block comprising another hardware logic circuit configured to perform one or more operations, wherein each node of the K-dimensional graph represents a K-mer, each edge of a K-mer graph represents a connection between a pair of K-mers, and each mass of each edge of a K-mer graph represents the occurrence number of a sequence of K-mers represented by a pair of K-mers; And in the process of generating a K-dimensional graph: periodically updating, by a data manager, a graph description for the K-dimensional graph after one or more operations have been performed by each hardware logic unit that is used to generate at least a portion of the K-dimensional graph, wherein the graph description data is (i) an identifier a K-dimensional graph and (ii) information about the state of the K-dimensional graph, wherein the control device creates a workflow of operations using the non-pipelined hardware logic blocks by triggering execution of one or more operations of each corresponding hardware logic block during generation of the K-dimensional graph. 10. The system of claim 9, wherein the output data of each hardware logical block of the plurality of hardware logical blocks is stored by a hash table buffer capacity. 11. The system according to claim 9, in which the operations additionally include: providing a generated K-dimensional graph to the variant recognition unit, wherein the variant recognition unit is configured to process the K-dimensional graph to determine potential variants between one or more of the plurality of reads and a reference sequence. 12. The system according to claim 9, additionally including: one or more computers; And one or more storage devices storing instructions, the execution of which by one or more computers causes the one or more computers to perform second operations of the variant recognition unit, the second operations comprising obtaining a generated K-dimensional graph by the variant recognition unit; And identifying, based on processing of the variant recognition block of the generated K-mer graph, one or more candidate variants, wherein the potential variant is the difference between a base recognition of one or more reads in the set of reads and a nucleotide of the reference genome at a particular location of the reference genome. 13. The system according to claim 9, in which the operations additionally include: obtaining a generated K-dimensional graph using a variant recognition block; And identifying, based on processing of the variant recognition block of the generated K-mer graph, one or more candidate variants, wherein the potential variant is the difference between a base recognition of one or more reads in the set of reads and a nucleotide of the reference genome at a particular location of the reference genome. 14. The system of claim 9, wherein the graph description data further includes (iii) data representing the last hardware logic block of a plurality of hardware logic blocks performing hardware logic on the K-dimensional graph or nucleotide sequences associated with the K-identifier dimensional graph. 15. A method for hardware-accelerated generation of a K-dimensional graph representing multiple sequencing reads for variant recognition analysis in a programmable logic device, including: obtaining a first set of nucleotide sequences generated by the nucleic acid sequencer, the first set of nucleotide sequences including (i) a plurality of reads corresponding to the active region of the reference sequence, and (ii) a portion of the reference sequence; for each specific nucleotide sequence from the first set of nucleotide sequences: generating a hash table for storage in a buffer capacity and a first hardware logical block of data representing a graph node for each K-mer of a specific nucleotide sequence; detecting by the control device that the first hardware logic unit has completed generating a graph node for each K-mer of the particular nucleotide sequence; configuring, by the control device, a second hardware logic unit to perform graph edge generation for the generated graph nodes; and for one or more pairs of generated graph nodes: generating by the second hardware logic unit and storing in a hash table graphs of data representing graph edges between one or more pairs of generated graph nodes generated by the first hardware logic unit, the data representing a graph node for each K-mer stored in the hash buffer capacity -tables, and the data representing the edges of the graph stored in the buffer capacity of the hash table is a K-dimensional graph of the first set of nucleotide sequences. 16. The method according to claim 15, additionally including: periodically storing, by the control device and in a memory unit accessible to the control device, graph description data for an instance of the K-dimensional graph, the graph description data being (i) a K-dimensional graph identifier and (ii) K-dimensional graph state information. 17. Method according to paragraph 15, wherein the first hardware logical block is further configured to: determining whether one or more particular K-mers of a particular nucleotide sequence correspond to another K-mer of a particular nucleotide sequence; And based on determining that one or more particular K-mers of a particular nucleotide sequence match another K-mer of a particular nucleotide sequence, storing data that marks the one or more particular K-mers as non-unique K-mers. 18. The method according to claim 15, in which the second hardware logic is further configured to: assign an edge mass to each edge of a K-dimensional graph. 19. The method according to claim 15, additionally including: issuing a command to the third hardware logical block of the programmable logic device to execute hardware logic configured to: obtaining data representing the K-dimensional graph from the hash table buffer capacity; And providing the received data representing the K-dimensional graph to the variant recognition unit. 20. The method according to claim 15, additionally including: issuing a command to the third hardware logical block of the programmable logic device to execute hardware logic configured to: selectively removing data representing graph nodes and data representing edges of the K-dimensional graph from the buffer capacity of the hash table. 21. The method of claim 15, wherein the control device is implemented using a third hardware logic block of the programmable logic device. 22. The method of claim 15, wherein the hash table buffer capacity is implemented using a third hardware logic block of the programmable logic device. 23. The method of claim 15, wherein the control device is implemented using one or more CPUs or GPUs executing software instructions to implement the functions of the control device. 24. The method of claim 15, wherein the graph description data further includes (iii) data representing the last hardware logic block of a plurality of hardware logic blocks performing hardware logic on the K-dimensional graph or nucleotide sequences associated with the K-identifier dimensional graph. 25. The method according to claim 15, additionally including: K-dimensional graph evaluation to check for cycles in the graph; if a graph cycle was detected during evaluation: termination of K-dimensional graph construction; or if no graph cycle is detected during evaluation: obtaining data from the buffer capacity of the hash table describing the structure of the K-dimensional graph; And providing the recognition module with variants of the received data that describe the structure of the K-dimensional graph. 26. A system for hardware-accelerated generation of a K-dimensional graph representing multiple sequencing reads for variant recognition analysis, using a programmable logic device, including: nucleic acid sequencer; a hardware-accelerated graph generation unit that includes hardware digital logic circuits configured to perform operations, the operations including: obtaining a first set of nucleotide sequences, the first set of nucleotide sequences including (i) a plurality of reads corresponding to the active region of the reference sequence, and (ii) a portion of the reference sequence; for each specific nucleotide sequence from the first set of nucleotide sequences: generating a hash table for storage in a buffer capacity and a first hardware logical block of data representing a graph node for each K-mer of a specific nucleotide sequence; detecting by the control device that the first hardware logic unit has completed generating a graph node for each K-mer of the particular nucleotide sequence; configuring, by the control device, a second hardware logic unit to perform graph edge generation for the generated graph nodes; And for one or more pairs of generated graph nodes: generating by the second hardware logic unit and storing in a hash table graphs of data representing graph edges between one or more pairs of generated graph nodes generated by the first hardware logic unit, the data representing a graph node for each K-mer stored in the hash buffer capacity -tables, and the data representing the edges of the graph stored in the buffer capacity of the hash table is a K-dimensional graph of the first set of nucleotide sequences. 27. The system according to claim 26, in which the operations additionally include: periodically storing, by the control device and in a memory unit accessible to the control device, graph description data for an instance of the K-dimensional graph, the graph description data being (i) a K-dimensional graph identifier and (ii) K-dimensional graph state information. 28. System according to clause 26, wherein the first hardware logical block is further configured to: determining whether one or more particular K-mers of a particular nucleotide sequence correspond to another K-mer of a particular nucleotide sequence; And based on determining that one or more particular K-mers of a particular nucleotide sequence match another K-mer of a particular nucleotide sequence, storing data that marks the one or more particular K-mers as non-unique K-mers. 29. The system according to claim 26, in which the second hardware logic is additionally configured to: assigning an edge mass to each edge of a K-dimensional graph. 30. The system according to claim 26, in which the operations additionally include: issuing a command to the third hardware logical block of the programmable logic device to execute hardware logic configured to: obtaining data representing the K-dimensional graph from the hash table buffer capacity; And providing the received data representing the K-dimensional graph to the variant recognition unit. 31. The system according to claim 26, in which the operations additionally include: issuing a command to the third hardware logical block of the programmable logic device to execute hardware logic configured to: selectively removing data representing graph nodes and data representing edges of a K-dimensional graph from the hash table buffer capacity. 32. The system of claim 26, wherein the hash table buffer capacity is implemented using a third hardware logic block of the programmable logic device. 33. The system of claim 26, wherein the graph description data further includes (iii) data representing the last hardware logic block of a plurality of hardware logic blocks performing hardware logic on the K-dimensional graph or nucleotide sequences associated with the K-identifier dimensional graph. 34. The system according to claim 26, in which the operations additionally include: K-dimensional graph evaluation to check for cycles in the graph; if a graph cycle was detected during evaluation: termination of K-dimensional graph construction; or if no graph cycle is detected during evaluation: obtaining data from the buffer capacity of the hash table describing the structure of the K-dimensional graph; And providing the recognition module with variants of the received data that describe the structure of the K-dimensional graph.