RU2807324C1 - Single-phase five-level current inverter - Google Patents

Abstract

FIELD: electrical engineering.

SUBSTANCE: invention can be used in variable AC electric drive systems and in secondary and autonomous power supply systems. A five-level current inverter contains two current sources, a typical single-phase bridge current inverter, four unidirectional fully controlled switches of which are a series connection of a transistor and a diode, as well as one similar additional unidirectional fully controlled switch and an additional diode. The load of the current inverter, to which a capacitor is connected in parallel, is connected between the middle points of the bridge arms, both current sources are connected with their negative pole to the negative bus of a single-phase bridge directly, and with their positive pole to the positive bus of the bridge, the second source is directly, and the first source is through an additional diode, the positive terminal of which is connected to the positive terminal of an additional unidirectional switch connected with its negative terminal to the common negative bus of the circuit, characterized in that a transistor is connected in series with the additional diode, converting this circuit into a unidirectional and fully controllable one.

EFFECT: ensuring the quality of the load current shape of a single-phase five-level current inverter over the entire range of changes in the parameters of the equivalent load.

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Description

The invention relates to electrical engineering and can be used in variable AC electric drive systems and in secondary and autonomous power supply systems.

A five-level single-phase current inverter is known [Malnev A.I., Bakhovtsev I.A., Zinoviev G.S. Review of multi-level current inverters for wind power stations. - News of Tomsk Polytechnic University. - 2015. - T. 326. - No. 7. - Page. 15-26]. The circuit contains a current source connected to two single-phase bridges operating in parallel on one load, which is connected between the common midpoints of the bridge racks (arms). In single-phase bridges, a transistor with a diode connected in series is used as a unidirectional fully controlled switch. One bridge is connected directly to the positive and negative buses of the power source, and the second - through the corresponding two inductances, which act as a current divider of the current source. Thus, half the current from the current source flows through the open switches of the diagonals of each bridge. With appropriate control, 5 current levels can be obtained in the load: I, I/2, 0, - I/2, -I, where I is the current source current. In particular, zero current in the load is ensured by unlocking the keys of one of the racks of single-phase bridges, ensuring that the current source current flows through the circuit, bypassing the load.

The disadvantage of this five-level single-phase current inverter is the large number of switches, which leads to a complex control system and high switching losses.

The closest solution to the claimed invention (prototype) is a five-level single-phase current inverter [Noguchi S. New H-Bridge Multilevel Current-Source PWM Inverter with Reduced Switching Device Count / S. Noguchi, T. Noguchi // The 2010 International Power Electronics Conference. - P. 103-107.], which contains two current sources connected to a single-phase bridge, the unidirectional fully controlled switches of which are a series connection of a transistor and a diode, as well as an additional unidirectional fully controlled switch. The load of the current inverter, to which the capacitor is connected in parallel, is connected between the midpoints of the bridge arms. Both current sources are connected directly with their negative pole to the negative bus of a single-phase bridge, and with their positive pole the second source is connected directly to the positive bus of the bridge, and the first through an additional diode. In addition, the anode of the said diode is also connected to the positive terminal of an additional unidirectional switch, connected with its second negative terminal to the common negative bus of the circuit.

The disadvantage of the mentioned five-level single-phase bridge current inverter is that the circuit operates adequately only when the load equivalent to the current inverter is active. This is ensured by compensating reactive power, in the general case, of an active-inductive load in parallel with a capacitor connected to it. In the case of undercompensation or overcompensation, there is a distorted shape of the inverter output current and, accordingly, the shape of the load voltage and current. The reason for this is an uncontrolled circuit with an additional diode, through which the current of the first current source can flow spontaneously into the load at phase shift intervals between the inverter output current and the load voltage. The envelope of the pulse voltage in the DC link (between the bridge buses), to which an additional diode is connected as the cathode, is determined by the voltage on the capacitor connected in parallel with the active-inductive load. Since the voltage on it lags behind the output current of the inverter during overcompensation (advances during undercompensation), then at the beginning (at the end), for example, of a negative half-wave of the output current, it (voltage) remains positive for a time interval equal to the phase shift. But in the DC link, since another diagonal of the bridge is already working, this section of the capacitor voltage becomes negative and the additional diode naturally opens, which leads to the mentioned distortions in this interval.

The technical result of the proposed invention is to ensure the quality of the load current shape of a single-phase five-level current inverter over the entire range of changes in the parameters of the equivalent load.

This is achieved by the fact that in a five-level current inverter containing two current sources, a typical single-phase bridge current inverter, four unidirectional fully controlled switches of which are a series connection of a transistor and a diode, as well as one similar additional unidirectional fully controlled switch and an additional diode, and, the load of the current inverter, to which the capacitor is connected in parallel, is connected between the middle points of the bridge arms, both current sources are connected with their minus pole to the minus bus of the single-phase bridge directly, and with their positive pole, the second source is directly connected to the positive bus of the bridge, and the first source is connected through an additional diode, the positive terminal of which is connected to the positive terminal of an additional unidirectional switch, connected with its negative terminal to the common negative bus of the circuit; a transistor is connected in series with the additional diode, converting this circuit into a unidirectional and fully controllable one.

In fig. 1 shows a diagram of the proposed five-level single-phase current inverter; in fig. Figure 2 shows diagrams of current conduction through an equivalent load depending on the state of the keys; in fig. 3 and fig. Figure 4 shows oscillograms of the output current and voltage of the inverter and control system signals, respectively, for a five- and three-level form of the inverter output current; in fig. 5 shows the control system of the proposed current inverter; in fig. 6 and fig. Figure 7 shows oscillograms of current and voltage on the load and control system signals, explaining the operation of the prototype device, respectively, with overcompensation and undercompensation of the active-inductive load of the current inverter with a capacitor connected in parallel to it.

In fig. 1 and fig. 2 shows current sources 1 and 2, transistor fully controlled switches 4, 6, 8, 10, 13, 16, diodes 3, 5, 7, 9, 14, 15, load 11 and capacitor 12. Also in FIG. Figure 1 shows control signals y4, y6, y8, y10, y13, y16 by transistors of the same name with keys. In fig. Figure 5 shows a modulating signal generator (MSG) 17, a reference voltage generator (RPG) 18 and a square pulse generator (RPG) 21, the first comparator (K1) 19 and the second comparator (K2) 28, the first logical element “2I” (I1) 20 and the second logical element “2I” (I2) 22, four logical elements “NOT” 23, 24, 29 and 30, adder 26, source of constant voltage Egon 27, equal to the amplitude of the reference signal.

The proposed device (Fig. 1) is a five-level current inverter and contains two current sources 1 and 2, a typical single-phase bridge current inverter, four unidirectional fully controlled switches of which are a series connection of diodes and transistors, 3 and 4, 5 and 6, respectively, 7 and 8, 9 and 10, as well as two similar additional unidirectional fully controllable switches, 14 and 13, 15 and 16, respectively, moreover, the load of the current inverter 11, to which the capacitor 12 is connected in parallel, is connected between the midpoints of the bridge arms, both sources current with its negative pole are connected to the negative bus of a single-phase bridge directly, and with its positive pole to the positive bus of the bridge, source 2 is directly connected, and source 1 is connected through the first additional controlled switch 14-13, the positive terminal of which is connected to the positive terminal of the second additional unidirectional switch 15-16 , connected with its negative terminal to the common negative bus of the circuit.

The proposed five-level current inverter circuit works as follows. During the period of the output current, the circuit can be in five different states, which correspond to five different levels of current on the equivalent load and which correspond to the 5 current conduction circuits presented in Fig. 2. It is assumed that the current value of each current source is equal to I/2. In the mode when the load current is equal to I (Fig. 2 a), the current flows from current source 2 (dashed line with arrows) directly, and from source 1 (thin solid line with arrows) through the first additional switch 14-13. Summing up on the positive bus of the current inverter, current I then flows through switch 3-4, through equivalent load 11, 12 and through switch 9-10, closing at the negative pole of the current sources. In the mode when the load current is equal to I/2 (Fig. 2 b), the current from source 1 does not flow into the load, since the circuit through the switch 15-16 is closed, and the second additional switch 14-13 is open. The current of current source 2, as in the previous mode, passes through switch 3-4, equivalent load 11, 12, switch 9-10 and then to the negative pole of the current sources. In the mode when the load current is 0 (Fig. 2 d), the current from source 1 is closed through switch 15-16 and returned to source 1, the current from source 2 passes (two options are possible) through switch 3-4 (5-6 ), key 7-8 (9-10) and returns to source 2. In the mode when the current is -I/2 (Fig. 2 c), the current from source 1 passes through key 15-16 and returns to source 1, the current from source 2 passes through switch 5-6, equivalent load 11, 12, switch 7-8 and returns to source 2. In the mode when the load current is -I (Fig. 2d), current flows from current source 1 through the first additional switch 14-13, and from source 2 directly. Summing up on the positive bus of the current inverter, current I then flows through switch 5-6, then it passes through the equivalent load 11, 12 (in the opposite direction) and through switch 7-8 closes to the negative pole of current sources 1 and 2. When through the equivalent load 11, 12 currents I/2 and I flow, the voltage on the capacitor 12 is charged in positive polarity. When the opposite currents -I/2 and -I flow through the equivalent load 11, 12, the voltage across the capacitor 12 is recharged in negative polarity. In this case, in the initial section of the new half-wave, the voltage on the capacitor remains for some time in the opposite polarity and then, as it recharges, it changes to a new polarity.

Operation of the device in steady state, in addition to FIG. 2 is supplemented by the oscillograms shown in Fig. 3 and fig. 4 obtained in the PSIM modeling environment, where:

Vcarry - sawtooth reference signal;

Vma - modulating sinusoidal signal;

Ia is the output current of the current inverter (see Fig. 1);

U_load - voltage across the load (or parallel capacitor);

Ud is the voltage between the positive and negative buses of the bridge current inverter;

Y4 - control pulse for transistor 4, its inversion is supplied to transistor 6;

Y13 is a control pulse for transistor 13, its inversion is supplied to transistor 16.

In steady state (Fig. 2), the capacitor 12 is charged and discharged so that an almost sinusoidal voltage U_load is obtained at the load (see Fig. 3). The process of increasing the voltage (charging the capacitor) occurs while the pulse load current Ia is greater than zero, and decreasing the voltage (recharging the capacitor) occurs when the load current flows in the opposite direction.

In fig. Figure 3 shows the timing diagrams of the power circuit and the control system when the modulation depth (the ratio of the amplitudes of the modulating Vma and reference Vcarry signals) is greater than 1. In this case, the output current has a five-level form and during the period of the output voltage there are 36 changes in current flow modes, this is realized by the control system for PWM counting: 6 times the current is zero, 9 times the current is I/2, 9 times the current is -I/2, 6 times the current is I, 6 times the current is -I. In the power circuit model, I/2 = 50 A.

In fig. Figure 4 shows the timing diagrams of the power circuit and the control system with a modulation depth of less than 1. In this case, the output current has a three-level form and during the period of the output voltage there are 32 changes in current flow modes, this is realized by the control system due to PWM: 16 times the current (see Fig. 4) is equal to zero, 8 times the current is equal to I/2, 8 times the current is equal to -I/2.

The control pulses of transistor 4 (y4) for the case of a modulation depth greater than 1 are formed as follows (see Fig. 5): the modulating and reference signals, respectively, from the modulating voltage generator (VMG) 17 and from the reference voltage generator (GON) 18 are supplied to the first comparator (K1) 19, the output signal from the comparator 19 is supplied to one of the inputs of the first logical element “AND” (I1) 20, the second input of which receives a rectangular signal from the rectangular pulse generator (RPU) 21, at the same time this signal as signal y10 is supplied to transistor 10. Inversion of signal y10, generated by logic element “NOT” 24, is supplied as signal y8 to transistor 8. Signals y8 and y10 ensure switching of the bridge diagonals and, accordingly, transition from one direction of current to another, or transition from one polarity to opposite. The second logical element “AND” (I2) 22 receives signals from the comparator 19, inverted by the logical element “NOT” 23, and from the rectangular pulse generator 21, inverted by the logical element “NOT” 24. Output signals from both logical elements “AND” 20 and 22 are supplied to the inputs of the logical element “OR” 25. The output signal of this element y4 is supplied to transistor 4, and the signal y6, inverted by the logical element “NOT” 29, is supplied to transistor 6.

The control pulse of transistor 13 is formed as follows: the modulating signal from the GMN 17 is supplied to the adder 26, the subtractive input of which receives a signal equal to the amplitude of the reference signal from the Egon block 27. The difference signal (i.e. that part of the modulating signal that exceeds the amplitude of the reference signal) and the reference signal from GON 18 are supplied to the second comparator (K2) 28. The output signal y13 of the second comparator (K2) 28 is supplied to transistor 13, and the signal y16, inverted by the logic element “NOT” 30, is supplied to transistor 16. Thus, the transistor 13 starts to work only when a five-level form of the inverter output current is formed, when the modulation depth is greater than unity and the load must receive a current ± I.

At the same time, with a three-level form of the output current (see Fig. 4), transistor 16 is always turned on, closing the current of the current source 1 through itself, and transistor 13 is always closed, preventing the diode 14 from turning on at the initial (final) section of the new half-wave and the flow of current current source 1 to the load, which distorts the output signals of the current inverter, which is what happens in the prototype device, in which there is no transistor 13. Timing diagrams for the prototype device in the overcompensation and undercompensation modes, respectively, are shown in Fig. 6 and fig. 7.

Thus, the technical result of the proposed device is to ensure the quality of the output current of the inverter over the entire range of changes in the parameters of the equivalent load, as shown in Fig. 3 and fig. 4, in contrast to the prototype device, in the DC link of which there is an uncontrolled flow of pulsed current at the beginning (end) of the period, as shown in FIG. 6 and fig. 7.

Claims (1)

A five-level current inverter containing two current sources, a typical single-phase bridge current inverter, four unidirectional fully controlled switches of which are a series connection of a transistor and a diode, as well as one similar additional unidirectional fully controlled switch and an additional diode, and the load of the current inverter to which a capacitor is connected in parallel, connected between the middle points of the bridge arms, both current sources are connected with their negative pole to the negative bus of a single-phase bridge directly, and with their positive pole to the positive bus of the bridge, the second source is direct, and the first source is through an additional diode, the positive terminal of which is connected to the positive terminal of an additional unidirectional switch, connected with its negative terminal to the common negative bus of the circuit, characterized in that a transistor is connected in series with the additional diode, converting this circuit into a unidirectional and fully controllable one.