RU2806533C1 - Optical-electronic shooting target of modular type - Google Patents

Abstract

FIELD: sports equipment.

SUBSTANCE: method for constructing sports targets for training and competitions using firearms and airguns. A significant difference between this technical solution and the existing ones is the ability to build electronic targets with the required working field size using basic modules of the same type. Each of these modules contains a limited set of photodetectors placed optically in conjunction with two radiation sources, and contains input and output serial ports for receiving and transmitting information, as well as a control interface. The control interface signals of each fixation module are connected to the computing device, and when at least one photodetector of any of the fixation modules is shaded, a signal is generated on the interrupt line and sent to the input of the computing device. Next, control pulses generated by the computing device produce a bit-by-bit shift of the information recorded in the modules from the furthest module in the chain to the input to the computing device. After the information is completely entered into the memory of the computing device, it determines the coordinates of the point where the bullet hits the registration zone.

EFFECT: simplification of the electronic circuit of the device, exclusion of expensive high-speed LSIs with a large number of contacts, as well as possibility of manufacturing electronic targets of various sizes using the same type of basic photodetector modules, sequentially connected to each other and covering the perimeter of the hit detection plane.

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Description

The proposed optical-electronic shooting target is intended for use during training and competitions in relevant sports, as well as for entertainment purposes.

This invention relates to the technology of stationary and moving targets with a hit detection system using the photoelectric method, as well as using infrared radiation, and in addition to the technology of using the properties of optical projection of physical objects to determine their spatial position in real time.

A number of optical-electronic targets are known, for example, LS25/50 LASERSCORE ^® from SIUS, which contains two vertical rows of photodetector arrays, made in the form of printed circuit boards with 280 discrete photodetectors each, and located on the sides of the target plane [1]. The target equipment records the position of the shadows cast by the bullet on the surfaces of the photodetecting arrays for each of the six emitters (three on each side), which requires continuous switching of the radiation sources. As follows from the material from SIUS, the target equipment produces 160,000 switching cycles per second. This makes it possible to obtain six measurements of the coordinates of shadows cast by a bullet on photodetector arrays, recorded from 6 angles, i.e. from each of the 6 radiation sources during the time the bullet passes the target area [2]. The disadvantage of this technical solution compared to the proposed one is its high cost associated with the use of large photodetector lines. This, in turn, requires the use of multilayer printed circuit boards due to the large number of signal conductors connecting the photodetectors to the computer. It is significant that this design uses six, three on each side, FPGA - programmable logic integrated circuits that act as a computer, and which had to be distributed on separate printed circuit boards. In addition, in such a measuring circuit, the measurement accuracy directly depends on the number of discrete photodetectors, and as a consequence of this, is limited by the size of the printed circuit boards and the minimum step of placing electronic components on it.

Megalink AS has presented a technical solution in which a bullet intersects a number of light strips located in the target body. Photodetecting arrays, optically coupled with each of the stripes, detect the shadows cast by the bullet. The measured time intervals between the intersection of the stripes are used to calculate the speed of the bullet and its position [3]. The disadvantage of this technical solution is the increased size of the electronic target body required to accommodate rows of light strips and photodetecting lines.

There is a well-known target proposed by the Institute of Applied Mechanics of the Ural Branch of the Russian Academy of Sciences. The essence of this invention is that the light target contains from four to six light screens, each of which is installed in a certain way in relation to the target plane and is formed using one linearly extended source - an emitter and one optically connected optical-electronic converter - receiver [4]. As in the previous technical solution, a significant drawback of this one is the large depth size of the target, which limits it to special applications not related to sports.

US patent No. 5637866 dated June 10, 1997, “Equipment and method for optical detection and electronic analysis of the location of a projectile in the target plane,” proposes the presence of two light sources, forming two light zones that pass between them at a certain angle. The light zones span the target plane, illuminating the projectile crossing the target plane, and casting the shadow of the projectile on a screen, preferably a diffuse ground glass screen. The shadow or image on the screen is detected by a spatially resolved photodetector, and the signals thus obtained are then analyzed as follows: the individual test signals from the individual elements of the photodetector are integrated during one measurement cycle, and the summed signals from the individual elements thus obtained are added to the final total. The final sum is compared with the reference value, and in case of deviation from the reference value, the possibly darkened element of the photodetector is determined, and based on this, a conclusion is made about the location of the projectile in the target plane [5].

The disadvantage of this technical solution is the need to use high-speed matrix image sensors as a photodetector with spatial resolution. Unfortunately, to obtain a blur-free image of a weapon bullet, high frame rates and processing power are required to process the digital stream coming from the image sensor. The complexity and cost of such a technical solution is too high for widespread use in sports targets.

By Dynetics, Inc. An electronic target is proposed that contains two high-speed image sensors optically coupled with reflective surfaces, illuminated in turn by two radiation sources. The appearance of shadows on the surface of diffuse reflectors, formed when a bullet passes, is recorded by image sensors connected to a computing device, which determines its position [6]. The disadvantage of this technical solution is the same as the previous one - the high price of the high-speed image sensors used in it and a wide range of data that must be processed by a computing device in real time, and, consequently, the high complexity and cost of this target.

The optical-electronic target of the above-mentioned manufacturer - SIUS (Switzerland) - LS10/LASERSCORE ^® [7], has two photodetecting lines, illuminated by two radiation sources, respectively, and the intersection of their light fluxes forms a hit detection plane, sensitive to the passage of this plane by a bullet . There is no need for switching emitters in this design, but, as in the previous technical solution, high-sized printed circuit boards are used, which increases the cost of the electronic target and complicates the construction of targets with a large size of the hit detection plane. This technical solution is closest to the invention proposed by the authors and is its prototype.

The purpose of the present invention is to simplify the electronic circuit of the device, to exclude expensive high-speed LSIs with a large number of contacts, as well as the possibility of manufacturing electronic targets of various sizes using the same type of basic photodetector modules, sequentially connected to each other and covering the perimeter of the hit detection plane. And what is significant, increasing the size of the impact plane does not entail the need to change the dimensions of signal processing printed circuit boards, but only a change in their number.

The operation of the proposed device is illustrated by the following figures:

Fig. 1. Functional diagram of the device, where:

1 - fixation module;

2 - linear array of photodetectors;

3 - one-bit data input;

4 - one-bit data output;

5 - input-output of control signals;

6 - communication wire of adjacent fixation modules 1;

7 - common control interface bus;

8 - first emitter;

9 - second emitter;

10 - sensory area;

11 - bullet;

12 - shadow sector of the first emitter 8;

13 - shadow sector of the second emitter 9;

14 - computing device.

In fig. Figure 2 shows the electrical circuit diagram of the module for fixing and transmitting the state of local photodetectors, where:

15 - phototransistors forming a linear array of photodetectors;

16 - comparator microcircuits;

17 - programmable logic integrated circuit (FPGA);

ph[0], ph[1]...ph[31], Din, clk, rst, load - FPGA input signals;

Dout, inter_n - FPGA output signals.

In fig. 3 provides a description of the operation of FPGA 17, in Verilog language.

In fig. Figure 4 shows a timing diagram of the operation of the fixation module 1 and the computing device 14, where:

11 _t1 , 11 _t2 , 11 _t3 , 11 _t4 , 11 _t5 - bullet (11) in flight at times t1, t2, t3, t4, t5;

U _k is the signal at the collector terminal of the phototransistor and the same at the non-inverting input of the comparator DA;

U _r - reference voltage of comparator DA;

load - signal for loading comparator states into the DTrig register [31:0];

clk - register shift pulse reg_s[31:0];

rst - register reset pulse DTrig[31:0];

inter_n - interrupt pulse;

t _H is the moment of operation of the comparator 16;

t _K is the moment of return to the initial state of the comparator 16.

In fig. Figure 5 shows an example of the arrangement of six fixation and transmission modules for constructing an optical-electronic target.

In fig. Figure 6 shows a 3D model of the practical implementation of fixation module 1 (obtained in the Altium Designer design environment).

The operating principle of an optical-electronic shooting target, the functional diagram of which is shown in Fig. 1, is based on determining the coordinates of the intersection point of shadow segments 12 and 13, formed when the bullet 11 passes the sensor plane 10 and intersects the light fluxes ψ ₈ and ψ ₉ . Considering that the linear arrays of photodetectors 2 are optically coupled with the emitters 8 and 9, at the points of intersection of the linear arrays 2 with the shadow segments 12 and 13, the photosensitive surfaces of the corresponding photodetectors are shaded.

In fig. Figure 2 shows a functional diagram of fixation modules 1, the number of which and their location ensure the intersection of light fluxes ψ ₈ and ψ ₉ with the surface of linear arrays of photodetectors 2. In addition, light fluxes ψ ₈ and ψ ₉ must cover the sensor area

10, i.e. the area in which the coordinate of the point of impact of the bullet 11 is determined. The appearance of shading 12 and 13 causes a decrease in the collector currents of the corresponding phototransistors, and accordingly an increase in the voltage levels at the corresponding non-inertizing inputs of the comparators 16 associated with the inputs of the FPGA 17. When these levels of the reference voltage Ur are exceeded, the output signals change comparators 16, In Fig. 3 provides a description of the functioning of FPGA 17 in the Verilog hardware description language. In this program, as an example, 32 asynchronous input signals ph[0]...ph[31] (input[31:0]ph) are processed, the unit state of which corresponds to the shading of the corresponding phototransistor, and the zero state corresponds to their illumination. These signals are sent to the input of FPGA 17.

Moreover, their change from 0 to 1 causes a corresponding change in the state of the 32-bit register DTrig[31.0], which is described in the following fragment:

In addition, the rst signal resets the DTrig[i] register to its original state.

The following fragment describes the hardware generation of the inter_n interrupt signal:

The active low level of the signal inter_n is an “editing OR”, it combines all the signals of the same name from the fixation modules 1 and forms one of the signals included in the common bus of the control interface 7 and is supplied to the interrupt generation input of the computing device 14. Namely, the appearance of a low level inter_n at least at the output of one fixation module 1, causes an interruption in the operation of the computing device 14 and its transition to inputting information accumulated by all fixation modules 1 that are part of the optical-electronic target.

To ensure the operation of the “wiring OR”, the inter_n signal output must be configured in the FPGA as an “open collector” / “Open_Drain” output.

Bitwise input of information into the computing device 14 is carried out from output 4 of the fixation device 1 via signal line 6.

In fig. Figure 4 shows a time diagram of the interaction of the computing device 14 with the fixation modules 1. Namely, the entry of a moving bullet into the sensor area 10 causes a change in the illumination of the corresponding photodetectors 15 and a change in the signal Uk (diagram A). When the signal Uk exceeds the threshold voltage level Ur, a high level of the signal ph[i] appears and, accordingly, the generation of an interrupt signal inter_n (diagram F). During interrupt processing, the computing device 14 generates a load signal (diagram C), which writes the state of the register DTrig[31:0] to the shift register reg_s[31:0], implemented by the following fragment:

Next, from the computing device 14, a signal sequence of pulses clk (diagram D) is sent to the common bus of the control interface 7, clocking the data input from the output of the last module 1 in the chain, with a simultaneous shift of information in the shift registers reg_s of all fixation modules 1 of the optical target.

The total number N of pulses clk is equal to:

N=m*l,

where: m - number of modules 1 in the target,

l is the number of photodetectors in fixation module 1 (set by the length of the DTrig and reg_s registers).

So, with each clk pulse, the data is shifted in the shift register reg_s[31:0] with the state of the input signal Din (connected to the Dout output of the adjacent clamping module by wire 6) being simultaneously written to it, and the Dout signal is issued (connected to the Din input of the second adjacent module fixing with wire 6), which is described by the following fragment of hardware implementation:

After completing data entry, the computing device 14 generates an rst pulse that resets the DTrig [31:0] registers, preparing it for the next hardware operation cycle:

Thus, the common bus of control interface 7 includes four signals:

1st: load - by which information is written from the DTrig register to the reg_s register;

2nd: clk - which carries out a clockwise shift of information in the reg_s register, with the simultaneous assignment of the Din state to reg_s[31], and the reg_s[0] state to Dout;

3rd: inter_n - an active low level of which (“open collector”), informs about the presence of shading of at least one photodetector (and initiates interrupt processing of the computing device 14);

4th: rst - clearing the DTrig register.

Thus, as part of the common bus of the control interface 7, there are four signals distributed over separate physical wires and connected to the parallel interface of the computing device 14. And the one-bit data output 4 of the last fixation module 1, closest to the computing device 14, is supplied via line 6 to its serial entrance. In this case, the synchronization signal, by which the computing device 14 enters the signal value at its serial input, is the clk signal, common to all fixation modules 1.

In fig. Figure 5 shows an example of an optical-electronic target containing 6 data recording modules 1 and made in the form of a U-shaped structure.

In fig. Figure 6 shows an example of the practical implementation of a fixation module 1 containing 32 KP-3216Р3С phototransistors, 8 four-channel comparators LM232DR and FPGA type XC9572XL-10VQ64 (CPLD from XILINX [8]). To increase the resolution, the fixation module 1 contains two linear arrays of photodetectors 2, located in parallel and offset relative to each other by half the step between the phototransistors.

The computing device can be made on the basis of a microcontroller having a hardware SPI interface, for example, ATmega328AU.

Information sources

1. LS25/50 LASERSCORE. The fully optical target for 25m and 50m pistol and small bore rifle.

https://sius.com/en/product/ls25-50-laserscore-11/ (last accessed 10/07/2022)

2. https://www.swissdis.ch/fileadmin/media/pdf-dokumente-2017/Polyscope_Bericht.pdf (last accessed 10/07/2022)

3. US Patent No. 10175033 dated January 8, 2019

4. RF Patent No. 2213320 dated June 24, 2002

5. US Patent No. 5637866 dated June 10, 1997

6. US Patent No. 6717684 dated April 6, 2004

7. US Patent No. 8570499 B2 dated January 8, 2013

8. XC9572XL High Performance CPLD Product Specification

https://docs.xilinx.com/v/u/en-US/ds057 (last accessed 10/07/2022)

Claims (4)

1. An optical-electronic shooting target of a modular type, containing two spatially separated radiation sources, the intersection of whose optical flows covers the area of registration of bullet impact points and optically coupled with a linear array of photodetectors, as well as a computing device, characterized in that the linear array of photodetectors is located on separate fixation modules, each of which contains a limited set of photodetectors, optically coupled with two spatially separated radiation sources, and contains input and output serial ports for receiving and transmitting information, as well as a set of input-output control signals, and the control signals of all fixation modules are connected by a common control interface bus and connected to the parallel interface of the computing device, while when at least one photodetector of any of the fixation modules is shaded, an active level of one of the control interface signals is formed, through which the computing device generates a signal sequence on the common control interface bus, which causes a shift in the accumulated information fixation modules from the serial output of each fixation module to the serial input of the fixation module adjacent to it, and the output of the fixation module closest to the computing device is connected to the serial data input of the computing device, and then, after entering the information accumulated in the fixation modules into the computing device, the computing device determines the coordinates of the point where the bullet hits the registration zone. 2. An optical-electronic shooting target of a modular type according to claim 1, in which photodetectors located in the fixation module are connected to the inputs of comparators, the outputs of which are in turn connected to the inputs of a data register that records the change in the illumination of the photodetectors from illuminated to dark, and, in addition, it contains a logical OR circuit for input signals from the outputs of the comparators, which generates an active low logical level with at least one darkened photodetector, and this signal is combined by “mounting OR” with similar signals of the other fixation modules, and then in the form of one of the signals common bus of the control interface is supplied to the interrupt input of the computing device, which in turn, in the interrupt handler, generates a signal for writing the contents of the data registers to the shift registers, arriving simultaneously to all fixation modules, and then the computing device generates shift clock signals, also arriving simultaneously to all fixation modules that bit-by-bit shift the contents of the shift register in the direction of the serial data input of the computing device, while the illumination states of the photodetectors fixed in the fixation modules are entered into the memory of the computing device, and after entering the last bit, the computing device sets the fixation modules to their initial state with a reset signal. 3. An optical-electronic shooting target of a modular type according to claim 1 or 2, the fixation modules of which contain a programmable logic integrated circuit (FPGA), in which an element of logical OR input signals from the outputs of the comparators and coming from it to the interrupt input of the computing device is implemented, implemented a data register that records changes in the input signals of the comparators when the illumination of photodetectors changes and is reset to its original state by a signal from a computing device, and a shift register is implemented, which is written to from the data register by an external signal from a computing device, and a bit shift is carried out by clock signals coming from the computing device. 4. An optical-electronic shooting target of a modular type according to claim 1 or 3, in which the interrupt signal, the data register reset signal, the write signal from the data register to the shift register, as well as the shift register clock signal form the control signals of the fixation modules and are connected to a common a bus connecting the fixation modules with the parallel interface of the computing device.

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