RU2804997C1 - Single-phase voltage inverter with multi-phase pulse-width modulation - Google Patents

Abstract

FIELD: power converter technology.

SUBSTANCE: invention can be used in construction of voltage inverters (VI) of a centralized type, both in single-phase (SPVI) and three-phase (TPVI) versions. A known single-phase voltage inverter with multiphase pulse-width modulation (M-SPVI with MPPWM), containing M+1 number of transistor-diode racks mounted between the power buses to connect them to a DC voltage source. Each of the racks is made in the form of two series-connected transistors, shunted by reverse diodes, each consisting of M connection points of transistors in the main group of M racks, is connected to the same polarity end of one of M windings of the main transfilter, which are located on the rods of its common M-rod magnetic circuit. The other ends of these windings are combined and form the first power output terminal of M-SPVI. A control unit (CU), which includes a high-frequency master oscillator (HFMO), a frequency divider unit (FDU) connected in series with it, and a paraphase signal generator (PSG) generating rectangular P ₀ and ₀ signals with a duty ratio of 2 and output frequency f ₂, M-channel pulse width modulator (PWM-j) with each channel made with output paraphase PWM signals , (j=1, 2.., M - channel number, k =1, 2, 3,.., 4 M – transistor number) and includes logical elements 2AND and 2OR. The paraphase outputs of the MSHI-j are intended for connecting them to the control inputs of the corresponding transistors of M main racks, equipped with M-1 additional racks, which, together with one of the above-mentioned racks, form an additional group of M racks, as well as an additional transfilter made similarly to the main transfilter, the windings of which are connected on one end to the corresponding connection points of transistors of the additional group of M racks, the control inputs of 2M transistors of which are intended for connecting them to the corresponding outputs of its control unit, which is equipped with a distributor of M paraphase pulses P _j and _j (RP _j ) with repetition frequency f _RP=f _t/2, sequentially shifted in phase by an angle δ₁=2π/M, M unipolar saw-tooth voltage generators (SVG-j) with output signals (t) with clock frequency f _t>>f ₂, shifted in phase by an angle δ₂=2π/M, a unipolar signal shaper u _z0(t) (USS) of a given, for example, sinusoidal frequency shape 2f ₂, M comparators (K _j ) with clock and control inputs and output signal , 2M number of logical nodes, each containing three two-input logical elements 2OR and two two-input logical elements 2AND.

EFFECT: expanding functionality of the M-SPVI and its scope of application by increasing the power range.

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Description

The invention relates to the field of power converter technology and can be used in the construction of voltage inverters (IN) of a centralized type, both in single-phase (SPV) and three-phase (TIN) versions in those areas where increased power and improved electromagnetic compatibility (EMC) are required ) and improved weight and size indicators. One of these areas is solar energy and wind energy, as well as mobile objects with an increased level of energy consumption.

In principle, a solution is known for a multi-level three-phase voltage inverter (TIN), in which the power part of each phase module is made according to a half-bridge circuit (see Author's certificate SU No. 381144 “Adjustable DC-AC converter with an improved output voltage curve” // Authors: A V. Ivanov, V. I. Klimov, V. I. Levin, published May 15, 1973, IPC N02M7/52). In it, each phase module (representing an SPV) is made in the form of M number of half-bridge circuits (forming channels), the output terminals of which, through M number of transformer windings, are connected to one phase output terminal, and the other phase output terminal is formed by the midpoint of the power source. In its absence, use the middle point of the capacitor divider in the form of two series-connected capacitors connected to the power supply buses. The control unit (CU) of this PWM is an M number of pulse width modulators (PWM), which form an M number of signals with pulse width modulation according to a sinusoidal law, which are shifted among themselves at the PWM clock frequency by an angle of 2π/ M . Control of key elements ( CE) EIN is produced using these signals. In the simplest case, with the number of channels M = 1, the output voltage of one phase has the form of bipolar PWM (BPWM). As the number M increases, the number of additional levels appears in the output voltage, and its shape improves.

The disadvantages of this technical solution are the low supply voltage utilization factor (about 0.6 instead of 1), as well as the low quality of the output voltage, which ultimately does not allow achieving high efficiency and obtaining acceptable weight and size indicators of the output filter, which is necessary in this class of SPE be used. When applying this solution in a single-phase version, a midpoint in the power source is required, which limits its use and is also one of its disadvantages.

It is these disadvantages mentioned above that can be eliminated by the OIN solution described in the Author's Certificate SU No. 1793523 “Converter with multiphase pulse-width modulation”, authors: V.V., Mikheev, G.S. Mytsyk, A.V. Chesnokov et al. publ. 02/07/1993, IPC N02M7/48. This converter solution with multiphase pulse width modulation (MPWM) is the closest in technical essence to the proposed invention and therefore it was chosen as a prototype. This converter belongs to the class of single-phase inverters (SPI) with MSWM and contains M +1 number of transistor-diode racks, M number of which are high-frequency (HF), and one rack is low-frequency (LF). All racks are connected between power rails to connect them to a DC voltage source. Each rack is made in the form of two series-connected transistors, shunted by reverse diodes, and M number of points of their connection in M number of RF racks are connected to one end of the same polarity of M number of transfilter (TF) windings, the other ends of these windings are combined and form the first power output pin of the SIN, its second power output pin is formed by the connection point of two transistors ( M +1) of the LF rack, which is also connected between the power buses. The transistors of the power part of the SPP receive control from a control unit (CU), which contains a frequency setter with a high output frequency that synchronizes (through the corresponding frequency dividers) the algorithms of all nodes of the multiphase pulse width modulator (MF-MPW), which includes shift registers, shapers narrow pulses, triggers RCS and RCK type logical elements 2OR, 2AND, NOT. A distinctive feature of the MF-MSHI design proposed here is its purely digital design. In this case, only one task is solved - the formation of an output voltage with a rigidly specified shape (with amplitude-pulse-width modulation - AWM). This means that the voltage regulation function is not included in it.

The disadvantages of this technical solution include the limited scope of its application - only in those converter structures where the problem of voltage regulation is solved along the power circuit. Another disadvantage of this solution is that the operating current of the LF stand transistors is 2 times greater than that of the HF stand transistors. From the standpoint of unifying the standard sizes of transistors, this complicates the manufacturing technology and reduces the power range of application.

The technical objective of the proposed invention is to provide regulation of the output voltage of the M -OIN.

The technical result consists in expanding the functionality of the M -SPE and its scope of application by increasing the power range of application.

This is achieved by the fact that the known single-phase voltage inverter with multiphase pulse-width modulation ( M -OIN with ASWM), containing M +1 number of transistor-diode racks connected between the power buses to connect them to a DC voltage source, each of the racks made in the form of two series-connected transistors, shunted by reverse diodes, each of the M number of connection points of transistors in the main group of M number of racks is connected to the end of one of the M windings of the main transfilter, which are located on the rods of its common M core magnetic circuit, of the same polarity, others the ends of these windings are combined and form the first power output terminal M -OIN, as well as a control unit (CU), which includes a high-frequency master oscillator (HFO), a frequency divider unit (UDF) connected in series with it, and a paraphase signal generator P ₀ And ₀ rectangular shape (FPS) with a duty cycle of 2 and an output frequency f ₂ , M channel pulse width modulator (MPW- j ), each channel of which is made with output paraphase PWM signals , ( j =1, 2.., M - channel number, k =1, 2, 3,.., 4 M - transistor number) and includes logical elements 2I and 2OR, and the paraphase outputs of the MSHI- j are intended for connecting them to the control inputs of the corresponding transistors M number of main racks, equipped with M -1 number of additional racks, which, together with one of the above-mentioned racks form an additional group of M number of racks, as well as an additional transfilter, made similarly to the main transfilter, the windings of which are connected at one end to the corresponding connection points of transistors of an additional group of M racks, the control inputs of 2 M number of transistors of which are intended to connect them to the corresponding outputs of it control unit, which is equipped with a distributor M for the number of paraphase pulses P _j And _j (RI _j ) with a repetition frequency f _RI = f _t /2, sequentially shifted in phase with each other by an angle δ ₁ = 2π/ M , M number of unipolar sawtooth voltage generators (GPN- j ) with output signals ( t ) with a clock frequency f _t >> f ₂ , shifted in phase by an angle δ ₂ = 2π/ M , a unipolar signal generator u _z0 ( t ) (FZS) of a given, for example, sinusoidal frequency shape 2 f ₂ , M number of comparators ( K _j with clock and control inputs and output signal , 2 M number of logical nodes, each of which contains three two-input logical elements 2OR and two two-input logical elements 2I, and the relationship of these logical elements with the outputs of the comparator K _j , RI _j and the FPS node at M = 2 is determined by the following logical expressions:

Where - algorithms for switching transistors of 4 racks of 2-OIN with PWM, with transistors 1÷4 forming the 1st bridge inverter cell (1st channel), and transistors 5÷8 forming the 2nd bridge inverter cell (2nd channel ).

The essence of the invention is illustrated by drawings, where in Fig. Figure 1 shows a schematic electrical diagram of the power part of a single-phase two-channel voltage inverter (2-OPWM) with OPSWM in the channels that jointly form a two-level output voltage with APSWM (2-APSWM); in fig. Figure 2 shows a simplified list of oscillograms that explain the principle of output voltage formation; in fig. Figure 3 shows detailed oscillograms that explain the logic of the operation of the control unit that forms the control algorithms for the 2-OIN transistors in Fig. 1; in fig. 4 shows an embodiment of the control unit.

The power part of the two-channel version of the OIN (2-OIN) contains 4 inverter racks, each of which is made in the form of two series-connected key elements - CE (transistors): 1, 2 (- 1st rack); 3, 4 (- 2nd); 5, 6 (- 3rd); 7, 8 (- 4th rack), shunted with freewheeling diodes). All 4 racks are connected between power buses 9, 10, designed to connect them to a power source (PS) 11 with DC voltage. With one-way conductivity of the power supply, a capacitor 12 is connected between power buses 9, 10. The first two (1st and 2nd) racks (with EC 1, 2 and 3, 4) form the 1st bridge inverter cell (MIYA-1). The second two (3rd and 4th) racks (with CE 5, 6 and 7, 8) form the 2nd bridge inverter cell (MIYA-2). The connection points a and b of the FE in the 1st 3rd racks are connected to the same opposite polarity ends of 2 windings 13.1 and 13.2 of the 1st two-winding transfilter TF-2(1) 13, located on the rods of a common magnetic circuit. The other ends of the TF-2(1) 13 windings are combined and form one intermediate power output terminal 13.3 2-OIN. Connection points c and d of the FE of the 2nd and 4th racks, by analogy with TF-2(1), are connected to the same opposite polarity ends of 2 windings 14.1 and 14.2 of the 2nd similarly designed two-winding transfilter TF-2(2) 14. The other ends of the TF-2(2) windings are combined and form the second intermediate power output terminal 14.3 2-OIN. This device belongs to the class of centralized type inverters, therefore, at its output, an LC filter (usually L-shaped type) 15 is connected to the intermediate power output terminals 13.3 and 14.3 in the form of an inductance choke 15.1 and a capacitor 15.2, the plates of which form the power output terminals 16, 17 for connecting loads to them.

CE control is carried out using pulse width modulators MSHI-1 and MSHI-2, located in the control unit (CU) 18 (see Fig . 4). The CE of the 1st bridge inverter cell (MIYA-1) is designed to be controlled by the 1st pulse width modulator (MSHI-1), located in BU 18. The CE of the 2nd bridge inverter cell (MIYA-2) is designed to be controlled through the 2nd pulse width modulator (MSHI-2), also located in BU 18.

An example of a control unit (CU) 18 with the number of inversion channels M = 2, shown in Fig. 4, contains a frequency setting unit 19 (which are necessary for its operation), including a high frequency setter (HFS) 19.1 and a unit of frequency dividers (UDCh) 19.2, multiples of the clock frequency f _t of sweeping signals of a triangular shape (frequencies f _t , where j = 1, 2,,.. M is the number of GPN- j ). It ensures synchronization of all nodes of BU 18. One of the outputs of UDC 19.2 is connected to the input of the paraphase output signal generator P ₀ and ₀ rectangular shape (FPS) 20 frequency f ₂ , the second output of the UDC 19.2 is connected to the input of the pulse distributor RI ^j 21, at the j -th paraphase outputs of which (with the number M = 2) the j -th number of paraphase signals P ^j are formed And The third and fourth outputs of UDC 19.2 are connected to one of the inputs of GPN-1 23.1 and GPN-2 24.1, respectively. Several outputs of ZGVCH 19.1 (in Fig. 4 there are 2 shown, but depending on the design, there may actually be more) with the corresponding frequencies are connected to the inputs of a (unipolar) master signal generator (FZSsin) 22 of a given, for example, sinusoidal shape - frequency f ₂ . To modulate the reference signal use M number of pulse width modulators (PWM- j ) according to a given law - 23, 24. Each of them at M = 2 contains a sawtooth voltage generator GPN-1 (23.1) and GPN-2 (24.1), the outputs of which are connected to the clock inputs of comparators ( K _j ) 23.2 and 24.2, respectively, and the control inputs of these comparators are combined and connected to the output of FZSsin 22. Signals are generated at the output of MSH- j (see Fig. 3, Fig. 4). CU 18 also contains 2 M number of identically designed logical devices (LU) 25, 26, 27, 28. Each of them contains three two-input logical elements (LE) 2OR:

- LU 25 contains the first LE 2OR 25.1, the second LE 2OR 25.2, the first LE 2I 25.3, the second LE 2I 25.4 and the third LE 2OR 25.5;

- LU 26 contains the first LE 2OR 26.1, the second LE 2OR 26.2, the first LE 2I 26.3, the second LE 2I 26.4 and the third LE 2OR 26.5;

- LU 27 contains the first LE 2OR 27.1, the second LE 2OR 27.2, the first LE 2I 27.3, the second LE 2I 27.4 and the third LE 2OR 27.5;

- LU 28 contains the first LE 2OR 28.1, the second LE 2OR 28.2, the first LE 2I 28.3, the second LE 2I 28.4 and the third LE 2OR 28.5.

The relationships between the inputs of LU 25÷28 with FPS 20, RI ^j 21, MSHI- j 23, 24 are determined by the following logical expressions:

From the presented description of the relationships between the nodes of BU 18, the pattern of synthesis of BU with values of the parameter M≥2 follows.

A single-phase voltage inverter with multi-phase pulse width modulation works as follows.

It is advisable to begin the description of the work with a description of the principle of generating the output voltages of the channels. BU 18 generates pulse sequences (the superscript denotes the channel number) to control transistors (CE) 1, 2 and 3, 4 of the first two racks, respectively, forming the 1st channel (see Fig. 1, Fig. 2). For this purpose, MSHI-1 23 is used, which includes GPN-1 23.1 and a comparatorTO ₁ 23.2 (Fig. 4). As a result of comparison in the comparatorTO ₁ 23.2 two signals (from units FZSsin 22 and GPN-1 23.1) a PWM signal is generated at its output (Fig. 3), arriving at the input of logical unit (LU) 25 (Fig. 4), which has 6 inputs: signal arrives at one of the two inputs of two logical elements (LE) 25.1 and 25.2, and the remaining 4 inputs of LU 25 receive signalsR ¹,,R ₀, ₀ according to RI¹ 21 and with FPS 20. After logical processing of five signals in accordance with the above logical algorithms (1), (2), pulse sequences are formed at the output of LU 25 to control transistors 1, 2 of the first rack 2-OIN.

A similar process of logical signal processing is carried out in LU 26 with the only difference that at the same inputs of its two LEs 26.1 and 26.2 signalsR ¹,change places. Pulse sequences are formed at its output to control transistors 3, 4 of the second rack.

LUs 27, 28 are synthesized by analogy with LUs 25, 26 with the difference that signals are supplied to the inputs of LE 27.1, 27.2, 28.1, 28.2 from the second GPN-2 24.1 (and not from the first GPN-1 23.1). At the outputs of LU 27, 28, pulse sequences are formed (in accordance with logical expressions (1÷4)) to control transistors 5, 6 and 7, 8 of the 3rd and 4th racks, respectively.

Four racks (on transistors 1÷8 - Fig. 1) form 2 bridge inverter cells (MIC): MIYA -1 on transistors 1÷4 represents the 1st channel (with the 1st and 2nd racks), and MIYA -2 on transistors 5÷8 - 2nd channel (with 3rd and 4th racks). In this case, windings TF-1 13.1 and 13.2 work together with the 1st rack of the 1st MIYA-1 and with the 3rd rack of the 2nd MIYA-2, and windings TF-2 14.1 and 14.2 work together with the 2nd rack 1st MIYA-1 and with the 4th stand 2nd MIYA-2. Control signals are supplied to those transistors, for example, 1, 5, of those racks (1st and 3rd) that are connected to one TF (in this example, TF-1) so that the currents in its windings flow in one direction (spatially, for example, in TF-1 from top to bottom). Taking into account the different polarity of switching on these windings relative to these currents, the resulting magnetic flux from the main harmonics of the current of these windings in the TF-1 magnetic circuit will be equal to zero. When control signals are applied in a similar way to transistors 4, 8, the currents in the TF-2 windings will flow from bottom to top. As a result, the fundamental current harmonic (with load current content in the channel) passes through each winding of TF-1 and TF-2 unhindered. When, for example, a positive half-wave of the output voltage is formed, currents flow (through part of the load current) through transistor 1 of the 1st rack and transistor 5 of the 3rd rack, then the current flows in full through the load, then through load current through two windings of TF-2 and through transistors 4, 8 (2nd and 4th racks, respectively). Thus, during the considered period of time, the load current begins its path from the positive terminal of the power source and ends at its negative terminal. At the same time, passing through a pair of odd transistors and through a pair of even transistors at M = 2, it is divided strictly in half between the transistors of each pair. In the general case, it is divided into M parts. Thanks to this property, M -OIN can be built on transistors whose operating current is M times less than the load current. When a negative half-wave of the output voltage is formed, transistors 3, 2 and transistors 7, 6 operate. As a result of interaction with TF-1 and TF-2, a two-level voltage with amplitude-pulse-width modulation 2-ASWM is formed at the output of 2-OIN (Fig. 2 ).

Thus, the above processes can be formulated in a more generalized form as follows: common-mode voltage harmonics in these 2 channels and the total current created by them in the load pass through the TF windings 13 and 14 without hindrance, being evenly distributed between the channels. According to the design concept, these (in-phase) harmonics (including, first of all, the 1st harmonic) in the channels should already have the same content, but even in the case of some violation of this condition (for technological reasons), electromagnetic connections between the TF windings provide: first, equalization of current values between channels; and, secondly, their subsequent summation. This is the first remarkable and useful property of TF. The second useful property is filtering. It lies in the fact that those higher voltage harmonics in the channels, which form symmetrical M phase systems in the channels, are completely delayed by the TF, so they do not pass into the load. Taking into account the operation of the TF as a blocking filter (for certain harmonics), two voltages with an OPWM form are formed at the output of MIYA-1 and MIYA-2, shifted from each other at the clock frequency by an angle π, and in phase with respect to the fundamental harmonic. Thanks to the properties of TF-1 and TF-2, at the output of the 2-OIN, from 2 voltages with PWM, shifted among themselves at the clock frequency by an angle of 2π/ M , the resulting voltage is formed with a new two-level form - with amplitude-pulse-width modulation (2 -ASWM at M = 2, Fig. 2, 3), which is characterized by significantly lower distortion and, accordingly, lower resource costs for filtering (compared, for example, with a single-channel SPI with output voltage PWM).

In general, the number of channels M can be increased according to need. In this case, the number of quantization levels in the output voltage per its period will always be equal to the number M (not counting zero pauses at the beginning and end of each half-cycle).

When using transistors of limited power to build M -OIN with M -ASWM, thanks to the present invention, the possibility of obtaining increased inverting powers increases significantly. At the same time, the function of voltage regulation is performed and resource costs for filtering are reduced.

This invention can be classified as a non-obvious solution. This conclusion can be confirmed by the following points. An analysis of available sources of information has shown that the use of known means of synthesizing BU 18 PWM based on two pulse width modulators (PWM) allows one to obtain only a lower quality form - only with PWM, but not with 2-PWM, which is obtained in this invention. The positive effect is achieved by special (quite simple in hardware implementation) logical processing of signals from the LWB.

The goal set in the invention is achieved by the fact that each of the M number of used continuous sweep signals (sweeps), shifted among themselves at a clock frequency by an angle of 2π/ M, after comparing them in the M number of LSBs with the task signal, from the M number of obtained comparison results ( in the form of M number of corresponding pulse sequences) after a certain logical processing, 2 M number of pulse sequences are formed to control transistors with 2 M number of M -OIN racks. We can say that from two (or M number) LSBs they form four (or 2 M number) LSBs, using significantly lower hardware costs compared to the traditional method of synthesizing 4 (or 2 M) MSBs.

The weight and size indicators of transfilters are determined by the value of the LSB clock frequency and powerM-OIN -S ₂₍₁₎ (according to the fundamental harmonic). To assess this indicator, it is advisable to use their relative overall power TF-M- , reduced in frequency to the output frequencyf ₂. With sufficient accuracy for engineering practice, we can assume that the indicator is from from the indicatorS ₂₍₁₎does not depend. It is determined only by a frequency close to the clock frequency (and somewhat less than it). A study carried out on the basis of computer simulation of 2-OIN (at the output frequency of its voltagef ₂ =50 Hz and clock frequency valuef _T =1200 Hz) gave the following result:, which indicates the undoubted prospects of using TF-M when synthesizing new resource-saving solutions for inverters.

The use of the invention makes it possible to expand the functionality by providing a voltage regulation function and expand the scope of application in terms of power while unifying key elements.

Claims (3)

Single-phase voltage inverter with multiphase pulse-width modulation ( M -OIN with PWM), containing M +1 number of transistor-diode racks connected between the power buses to connect them to a DC voltage source, with each of the racks made in the form of two series-connected transistors shunted by reverse diodes, each of the M number of connection points of transistors in the main group of M number of racks is connected to the same polarity end of one of the M windings of the main transfilter, which are located on the rods of a common M core magnetic circuit, the other ends of these windings are combined and form the first power output terminal M -OIN, as well as a control unit (CU), which includes a master high-frequency oscillator (ZGVCH), a frequency divider unit (UDF) connected in series with it and a paraphase signal generator P ₀ and rectangular shape (FPS) with a duty cycle of 2 and an output frequency f ₂ , M channel pulse width modulator (MPW- j ), each channel of which is made with output paraphase PWM signals ( j =1, 2.., M – channel number, k =1, 2, 3,.., 4⋅ M – transistor number) and includes logical elements 2I and 2OR, and paraphase outputs MSHI-j are intended for connecting them to the control inputs of the corresponding transistors M number of main racks, characterized in that it is equipped with M -1 number of additional racks, which together with one of the above-mentioned racks form an additional group of M number of racks, as well as an additional transfilter made similarly to the main transfilter, the windings of which at one end are connected to the corresponding connection points of transistors of an additional group of M racks, the control inputs of 2 M number of transistors of which are intended to connect them to the corresponding outputs of its control unit, which is equipped with a distributor of M number of paraphase pulses P _j And with a repetition frequency f _RI = f _t /2, sequentially shifted in phase with each other by an angle δ ₁ = 2π/ M , M number of unipolar sawtooth voltage generators (GPN- j ) with output signals with a clock frequency f _t >> f ₂ , shifted in phase with each other by an angle δ ₂ = 2π/ M , a unipolar signal shaper u _z0 ( t ) (FZS) given, for example, a sinusoidal frequency shape 2 f ₂ , M number of comparators ( K _j ) with clock and control inputs and with an output signal , 2 M number of logical nodes, each of which contains three two-input logical elements 2OR and two two-input logical elements 2I, and the relationship of these logical elements with the outputs of the comparator K _j , RI _j and the FPS node at M = 2 is determined by the following logical expressions: Where – algorithms for switching transistors of 4 racks of 2-VIN with PWM, with transistors 1÷4 forming the 1st bridge circuit of the inverter cell (superscript 1), and transistors 5÷8 forming the 2nd bridge circuit of the inverter cell (superscript 2 ).