RU2803264C1 - Detector output correction method in received signal strength indicator (rssi) - Google Patents

Abstract

FIELD: electrical engineering.

SUBSTANCE: corrected signal detector is proposed, including a double half-wave detector made on two differential pairs consisting of transistors and bias resistors, as well as a corrective detector consisting of transistors and bias resistors. Moreover, the signal detector and the corrective detector are made on a chip with a high degree of identity. Thus, a small static current from the signal detector is added to a large current from the correction detector, and vice versa, a large static current from the signal detector is added to a small current from the correction detector, which leads to equality of potentials at the outputs OutN and OutP, i.e. to zero differential voltage at zero input signal.

EFFECT: elimination of arbitrary voltage at the output of microcircuits of signal level indication paths in the absence of an input signal.

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Description

Field of technology

The invention relates to electronic technology and can be used in the development of microcircuits for receiving paths. Due to the growing dynamic range of receiving paths and the increasing importance of digital signal processing, the need for Received Signal Strength Indication (RSSI) circuits has increased. Input signal magnitude data avoids overloading and is used to digitally control the entire device, allowing the required range of input signal magnitudes to be provided.

An example of the use of such devices is the operation of cell phones at different distances from a cellular base station. When approaching the base station, it is necessary to reduce the gain in the input stages in order to avoid “clogging” of the receiving path, and vice versa, maximum gain is required at a significant distance from the base station. A similar situation arises in radar devices, as well as anywhere else where we have to deal with signals of a wide dynamic range. The proposed invention aims to eliminate additional settings and adjustments in RSSI tracks that currently exist.

Prior Art

Technical solutions are known from the prior art that ensure the construction of RSSI paths. A number of foreign companies mass-produce similar devices built on the basis of logarithmic paths using the sequential detection method; the best results were achieved by the well-known company Analog Devices, USA. Over the past decades, this company has developed a number of similar devices that have a similar structure and differ in frequency and dynamic ranges (AD640 and subsequent ones) [1], which are made mostly using bipolar technology, in recent years using the SiGe process.

The basis of this class of circuits is the logarithmic signal processing path. A simplified block diagram of the logarithmic path using the sequential detection method is shown in FIG. 1. It should be noted that modern integrated circuits are based on differential cascades.

The basis of the tract is the serial connection of several links consisting of an amplifier-limiter (CA) and a detector on a biased differential stage. The signal from all detectors is summed up over a common load and, with a correctly selected transmission coefficient and threshold, the DC provides a logarithmic relationship between the power level of the input signal and the output voltage.

Well-known foreign analogues of this type require a number of additional pins for adjustment and connection of external adjustable resistors and large-capacity blocking capacitors. An important issue is the presence of a “pedestal” [1] when operating a detector made according to a well-known scheme on a biased differential stage. This “pedestal” is the sum of the voltage drop across the output resistor from the low currents of the detectors of all stages with a zero signal at the input. In FIG. Figure 2 shows graphs of the output voltage of the logarithmic sequential detection path for different input signal levels. It can be seen that for an arbitrarily small signal at the output there is a “pedestal” equal in this case to 100 mV. This voltage, corresponding to the absence of a signal at the input, can vary within certain limits due to technological variation and does not allow galvanic connection of an analog-to-digital converter (ADC), and also requires additional calibration to eliminate it, by adjusting through an external direct current source and a resistor, as recommended in all descriptions of well-known foreign microcircuits of this type [1].

Disclosure of the Invention

The objective of the present invention is to eliminate external adjustment elements for semiconductor microcircuits of signal level indication paths at the input of the receiving device.

The technical result to be achieved by the claimed invention is the elimination of the described effect of the presence of a “pedestal” - an arbitrary voltage at the output of the signal level indication circuit circuits in the absence of an input signal.

Description of how to achieve the result

The essence of the invention is illustrated by drawings.

In FIG. Figure 3 presents a new solution for a link with correction of the detector imbalance in direct current. The link consists of a detector on a biased differential stage, made according to a known circuit design, and an additional compensating detector. The specified technical result is achieved by the fact that as a correction device for the imbalance of the biased detector, made in a known design on bias resistors 1 and transistors 2-5 and to which a signal is supplied through the inputs InP, InN, an additional detector is used, also located on a crystal identical to the main one, made on bias resistors 6 and transistors 7-10, but without supplying a signal to it, and its static current at the outputs OutP, OutN is added in antiphase to the current of the main detector.

Static output currents of the main and additional detectors adding up to the common load resistor of all links, FIG. 1, when switched on differentially, they create equal potentials at the inverted and non-inverted output. This ensures zero offset at the detector output in the absence of an input signal. By selecting the low-power detector mode, the overall increase in current consumption is insignificant. In FIG. Figure 4 shows the output characteristics of the path with detector correction. All graphs start from the zero point; the circuit is suitable for galvanic connection to the ADC unit and does not require additional adjustments.

Information sources:

1. Datasheet Analog Devices AD640; Datasheet Analog Devices AD641; Datasheet Analog Devices AD8306; Datasheet Analog Devices AD8307; Datasheet Analog Devices AD8309; Datasheet Analog Devices AD8318.

Claims (1)

A signal detector with correction, including a full-wave detector made on two differential pairs consisting of a first transistor (2), a second transistor (3), a third transistor (4), a fourth transistor (5) and bias resistors (1) connected between the gates transistors (2), (5) and (3), (4), respectively, as well as a correction detector consisting of a fifth transistor (7), a sixth transistor (8), a seventh transistor (9), an eighth transistor (10) and two bias resistors (6) connected between the gates of transistors (7), (10) and (8), (9), respectively, and the signal detector and the correction detector are made on the same crystal with a high degree of identity, the drains of the first (2) and third ( 4) transistors are connected to the drains of the sixth (8) and eighth (10) transistors, and the drains of the second (3) and fourth (5) transistors are connected to the drains of the fifth (7) and seventh (9) so that a small static current from the signal detector , including the first-fourth (2-5) transistors, adds up to a large static current from the correction detector, including the fifth-eighth (7-10) transistors, and vice versa, a large static current from the signal detector, including the first-fourth (2-5 ) transistors, adds up with a low current from the correction detector, which includes the fifth-eighth (7-10) transistors, which leads to equal potentials at the outputs OutN and OutP and to zero differential voltage at the output with a zero signal at the input.

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