RU2790140C1 - Digital signal demodulator with two-level amplitude-phase shift keying and relative symbol amplitude estimation - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: invention relates to the field of radio engineering and can be used in digital devices for receiving information signals with multi-position amplitude-phase shift keying (APSK or APSK). The digital signal demodulator with two-level amplitude-phase keying and relative estimation of the symbol amplitude additionally contains a decision generation unit (DGU), a code generator (CG), a quadratic converter (QC), a clock synchronization unit (CSU), a delay unit (DZ), the first (U1) and second (U2) multiplier, third (B3) and fourth (B4) subtractor, trigger (T) and decision device (DD). The first input of the DGU is connected to the output of the digital filter. The first input of the FK is connected to the DGU output, the second input is connected to the RU output, the second T input and the third DGU input, the third input is connected to the second DGU input, the first T input, the BTS output and the second B3input, and the CG output is the demodulator output. The U1 input is connected to the B3output and the first input B4, the output is connected to one input B3. The first input of the CP is connected to the output of the first CCC, the second input is connected to the output of the second CCC, and the output is connected to a common point formed by connecting the first inputs of the DGU, B3, input U2 and another input B3. The second input B4 is connected to the output U2. The first input of the RU is connected to the B3 output, and the second - to the B4 output, and the third - to the T output.

EFFECT: increase in the information transfer rate due to the use of two positions of the symbol amplitude and a simplification of the demodulator implementation that does not require the formation of thresholds for comparing the absolute values of the amplitudes of the received symbols.

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Description

The invention relates to the field of radio engineering and can be used in digital devices for receiving information signals with multi-position amplitude-phase shift keying (APM or APSK).

A device for receiving signals with amplitude-phase keying [1], containing a phase demodulator, an amplitude comparator, a switch, a controlled attenuator, an amplifier and a low-pass filter, is known. Its disadvantage is the complex analog signal processing and the accompanying signal conversion errors.

Another device for receiving signals with amplitude-phase keying [2] is known, containing an analog-to-digital converter (ADC), a corrector, signal vector converters, a block for calculating the orthogonal projection of the gradient, and an automatic gain control block. Its disadvantage is the complexity of implementation and the need for precise control of the input signal level.

A device for adaptive reception of discrete signals with amplitude-phase modulation [3], containing an automatic level controller, a phase shifter, an ADC, a demodulator, a decision block, an adaptive corrector, a decoder and a phase locked loop, is known. Its disadvantages are significant computational costs and complexity of implementation, especially of the corrector and demodulator, as well as the analog formation of quadrature channels, the errors of which significantly affect the noise immunity of multi-position phase values.

A signal demodulation method and device [4] is known, containing a serially connected analog processing unit, an ADC unit and a programmable logic integrated circuit (FPGA), where the FPGA is configured to exchange data with a buffer memory and a microcontroller, and the microcontroller and FPGA are connected to interfaces that provide interaction with the computer and external devices. At the same time, the device is made with the possibility of a signal processing sequence, including converting an analog signal to a digital form at an intermediate frequency, envelope extraction and quadrature decomposition, symbol synchronization, adaptive filtering, carrier synchronization, demapping using data in the buffer memory, frame synchronization and decoding . Its disadvantage is the complexity of implementation.

A common disadvantage of known devices is the need to provide specified thresholds for comparing the amplitudes of the received symbols due, for example, to automatic gain control (AGC) of the receiver.

The closest in technical essence and internal structure to the proposed device is a digital phase detector [5], containing an ADC, a shift register of multi-bit codes for four samples, the first and second n-cascade channels of quadrature signal processing, a clock generator, a normalizing device, a digital shaper arc tangent and phase correction block. Its disadvantage is the low information transfer rate due to the single position of the symbol amplitude.

The technical objective of the present invention is high-speed optimal digital demodulation of signals with multi-position amplitude-phase keying with a relative estimate of the amplitude of the received symbol.

The technical result consists in increasing the information transfer rate by using two positions of the symbol amplitude and simplifying the implementation of the demodulator, which does not require the formation of thresholds for comparing the absolute values of the amplitudes of the received symbols.

This is achieved by the fact that the well-known digital signal demodulator with amplitude-phase keying, containing a cascade-connected analog-to-digital converter (ADC) and a shift register of multi-bit codes for four samples (PC4), the first and second n-cascade channels of quadrature signal processing (QPC ), the first and second inputs of which are connected to the odd and even outputs of the RS4, the normalizing device (NU), the first and second inputs of which are connected to the outputs of the first and second CCO, respectively, the digital arc tangent shaper (CF), the input of which is connected to the output of the NU and the generator clock pulses (GTI), equipped with a decision forming unit (BFR), the first input of which is connected to the output of the digital filter, a code generator (FC), the first input of which is connected to the output of the BFR, a quadratic converter (CP), the first input of which is connected to the output of the first CCC , the second input - with the output of the second CCO, the clock synchronization unit (BTS), the delay unit (BZ), the first multiplier (U1), the input of which is connected to the output of the BZ, the second multiplier (U2), the third subtractor (V3), one input of which is connected to the output of U1, the fourth subtractor (V4), the first input of which is connected to the output of the BZ, and the second to the output of U2, the output of the KP is connected to a common point formed by connecting the first inputs of the BTS, BZ, input U2 and another input B3, a decision device (RU), the first input of which is connected to the output B3, and the second to the output B4, a trigger (T), one input of which is connected to the output RU, and the output - to the third input of the RU, the output of the BTS is connected to a common point formed by connecting the second input of the BZ, the second input of the BFR, another input of T and the third input of the FK, the output of the RU is connected to the second input of the FK and the third input of the BFR, the ADC clock inputs , PC4, the first and second KCO, BTS, BFR and FK are connected to the GTI outputs, the FK output is the demodulator output.

The present invention is illustrated by drawings, where in Fig. 1 shows a block diagram of the proposed digital signal demodulator with two-level amplitude-phase keying and relative symbol amplitude estimation, FIG. 2 and FIG. 3 - signal constellations with 16APSK (16APSK), in Fig. 4 shows the input signal quantization process (4 samples per period), FIG. 5 are timing diagrams of quadrature channel responses, FIG. 6 - implementation of phase readings, in Fig. 7 is an implementation of symbol amplitude estimation, FIG. 8 and FIG. 9 shows the dependence of the error probability on the signal-to-noise ratio for the constellations shown in FIG. 3 and FIG. 2, respectively.

The digital demodulator of signals with two-level amplitude-phase keying and a relative estimation of the symbol amplitude contains an ADC 1, the first input of which is configured to receive an APM signal from the receiving device RX 2. The output of the ADC 1 is connected to the input of the register 3 for shifting multi-bit codes into four readings PC4, odd the outputs of which are connected to the corresponding inputs of the subtractor B1 4 of the first CEC 5, and the even outputs are connected to the corresponding inputs of the subtractor B2 6 of the second CEC 7. Each CEC, in addition to the subtractor, contains n cascade-connected blocks of accumulation of samples (BNO). The number of BNO n depends on the number N of signal accumulation periods and is determined by the binary logarithm N (n=log ₂ N). This construction of the device provides a minimum number of BNOs. The number of processed signal periods corresponds to N=2 ⁿ , and the duration of the processed information symbol is defined as NT ₀ , where T ₀ =1/ƒ ₀ is the period of the received signal with a carrier frequency ƒ ₀ .

The first KCO 5 contains serially connected BNO 8-1, ..., 8-n, and the second KCO 7 - serially connected BNO 9-1, ..., 9-n. Each of the BNOs consists of a shift register of multi-bit codes MP and an adder SUM. Blocks 8-1, ..., 8-n accumulation of samples contain registers 10-1, ..., 10-n shift multi-bit codes and adders 11-1, ..., 11-n, respectively, and BNO 9-1, ..., 9-n contain registers 12-1, ..., 12-n shift multi-bit codes and adders 13-1, ..., 13-n. In each block 8 (9) of the accumulation of samples, the input of the shift register 10 (12) is the input of the block 8 (9) of the accumulation of samples, and the corresponding outputs of the register 10 (12) are connected to the first and second inputs of the adder 11 (13). The output of the adder 11 (13) is the output of the block 8 (9) accumulation of samples, and the clock input of the register 10 (12) shift is the control input of the block 8 (9) accumulation of samples.

The output of the V1 subtractor 4 is connected to the input of the block 8-1 of the accumulation of readings of the KKO 5, and the output of the block 8-n of the accumulation of the readings of the KKO 5 is connected to the first input of the normalizing device NU 14. The output of the subtractor B2 6 is connected to the input of the block 9-1 of the accumulation of the readings of the KKO 7 , and the output of the block 9-n accumulation of readings of the KCO 7 - with the second input of the NU 14. The output of the NU 14 is connected to the input of the digital shaper of the arc tangent of the CF 15, the output of the CF 15 is connected to the first input of the BFR 16. The outputs of the first 5 and second 7 of the KKO are connected to the first and the second inputs of the KP 17, the output of which is connected to the first input of the BTS 18, the first input of the BZ 19, the input of U2 20 and the first input of the B3 21. The output of the BTS 18 is connected to the second input of the BZ 19, the first input of the trigger T 22 and the second input of the BFR 16.

The output of BZ 19 is connected to the input U1 23 and the first input V4 24, the output U1 23 is connected to the second input V3 21, the output of which is connected to the first input RU 25, and the output U2 20 is connected to the second input V4 24, the second input RU 25 is connected to output B4 24. The output of RU 25 is connected to the second input of the trigger T 22 and the third input of the BFR 16, and the output of T 22 is connected to the third input of the RU 25. The first input of the code generator FK 26 is connected to the output of the BFR 16, the second input of the FK 26 is connected to the output RU 25, and the third input of FK 26 is connected to the output of BTS 18.

The clock inputs of the ADC 1, the first 5 and the second 7 KCO, BTS 18, BFR 16 and FK 26 are connected to the outputs of the GTI 27, the output of FK 26 is the output of the demodulator.

A digital signal demodulator with two-level amplitude-phase shift keying and relative symbol amplitude estimation operates as follows.

An amplitude-phase-shift keying (APSK) signal is multi-position and the carrier is simultaneously modulated in amplitude and phase by the transmitted binary code. It is represented by a constellation - a diagram on a plane, the points of which display the values of the amplitude and the initial phase of the transmitted 2 ⁿ -positional information symbol, represented by an n-bit binary code. An example of a constellation of a 16APM signal used in digital television, with n=4 (the number of positions is 16) is shown in FIG. 2. A point in the quadrature plane (I,Q) corresponds to the position of the signal, for which the angle of inclination of the vector from the origin corresponds to the initial phase ψ _k of the k-th transmitted information symbol with values 0÷2n, and the length of the vector corresponds to its amplitude S _k . Thus, a polar coordinate system is realized. The points are encoded with four-bit Gray code combinations (for the example under consideration, 12 initial phase values and 2 amplitude values are transmitted). To demodulate the signal from the AFM on the receiving side, phase locking of the reference oscillator is required.

At the output of receiver 2, the k-th received symbol of the signal s(t) with APM can be written as

- символы, модулирующие фазу (на фиг. 2 М₂=4 при a _k=0 и М₂=12 при a _k=1). При этом общее число позиций сигнала с АФМ (1), описываемого созвездием, представленным на фиг. 2, определится как М=4+12=16.where U is the minimum symbol amplitude, ƒ ₀ ^_ carrier frequency, a _k are amplitude modulating symbols (it is assumed that they can take M ₁ =2 possible values a _k =0 or a _k =1),

- symbols that modulate the phase (in Fig. 2 M ₂ =4 when a _k =0 and M ₂ =12 when a _k =1). In this case, the total number of signal positions with APM (1), described by the constellation shown in Fig. 2 is defined as M=4+12=16.

In FIG. 3 shows another version of the constellation with M ₁ =2 and M ₂ =8 for each possible value of a _k (M=8+8=16). Its feature is the possibility of independent modulation of the amplitude (1 bit) and phase (3 bits) of the signal.

The signal from the AFM is fed to the input of the ADC 1, which generates four samples of the input signal for a repetition period T ₀ =1/ƒ ₀ in accordance with the GTI clock pulses following with a frequency of 4ƒ ₀ . The input signal sampling process for the ith period is shown in FIG. 4.

(где S - амплитуда текущего элемента), которая запоминается в регистре сдвига многоразрядных кодов 10-1. В следующем периоде сигнала на выходе вычитателя В1 4 получим величину

, а на выходе сумматора 11-1 -

. После поступления N=2ⁿ периодов входного сигнала (n - число БНО в каждом ККО) при отсутствии помех и в предположении, что за время NT₀ начальная фаза входного сигнала меняется незначительно, на выходе сумматора 11-n первого ККО 5 получим результат обработки 2N отсчетов принятого сигнала видаAfter processing the j-th period (filling the multi-bit shift register for four samples PC4 3), the subtractor B1 4 receives the samples s _2j and s _4j at the input, and the difference is formed at its output

(where S is the amplitude of the current element), which is stored in the shift register multi-bit codes 10-1. In the next period of the signal at the output of subtractor B1 4 we obtain the value

, and at the output of the adder 11-1 -

. After the arrival of N=2 ⁿ periods of the input signal (n is the number of BNOs in each CCC) in the absence of interference and assuming that during the time NT ₀ the initial phase of the input signal changes slightly, at the output of the adder 11-n of the first CCC 5 we obtain the processing result 2N samples of the received signal of the form

, которая запоминается в регистре 12-1. После поступления N периодов входного сигнала на выходе сумматора 13-n второго ККО 7 имеемSimilarly, at the input of the subtractor B2 6, the samples s _1j and s _3j first arrive (shifted relative to the pair s _2j and s _4j in time by T ₀ /4 or in phase by 90 °), and at the output of the subtractor B2 6 a difference is formed

, which is stored in register 12-1. After the arrival of N periods of the input signal at the output of the adder 13-n of the second CCC 7 we have

By changing the numbering of the received periods for convenience by means of the transformation i=j+N-1, for y _1i and y _2i we can write

where i is the number of the current (last received) processed period of the signal at the end of the reception of the current symbol. Examples of 2NS-normalized dependences of y _1i and y _2i on the number of the current period i for the constellation shown in FIG. 3 in the absence of interference are shown in FIG. 5. The linear nature of the change in these values indicates the optimality of signal processing.

The binary codes of the values y _1i and y _2i enter the normalizing device NU 14 (based on the shift registers), which provides, by joint shifting the codes, the complete filling of the bit grid of the largest modulo of them. Further, the results are sent to the digital shaper of the arc tangent TsF 15, in which the value is determined

equal to the phase shift between the received and reference (from GTI 27) signals and taking values in the range from -3π/2 to π/2. It is advisable to implement the procedure for calculating expression (3) in the digital filter 15 on the basis of a read-only memory device (ROM), in which the codes of the values y _1i and y _2i form the address of the memory cell containing the binary code ψ _i (3). If we choose the bit width of the normalized codes y _1i and y _2i equal to 10 (20-bit ROM address bus), and the code bit width ψ _i (data bus) equal to 16, then a ROM with a total capacity of 2 MB is required.

In FIG. 6 shows an example of ψ _i (3) versus i/N for the constellation shown in FIG. 3, in the absence of interference. The decision about the phase of the received symbol is made at integer values of i/N. From the output of the digital filter 15, the binary code c _i of the initial phase ψ _i is transmitted to the first input of the BFR 16.

The responses of the first 5 and second 7 CCCs y _1i and y _2i arrive at the CP 17, at the output of which the value is formed

According to (2), at the end of receiving the kth symbol with amplitude S _k

and is an estimate of the amplitude of the APM signal element. An example of z _i versus i/N for the constellation shown in FIG. 3 under no interference conditions is shown in FIG. 7.

The response KP 17 z _i enters the BTS 18, which generates the symbol synchronization, marking the end of the reception of the next signal element. As can be seen from the diagram shown in FIG. 7, the shape of the response pulses of the CP 17 is suitable for the formation of the sync pulses of the BTS 18.

Values z _i coming from KP 17 signal BTS 18, with integer k=i/N (where k is the number of the current received character) are transmitted to the input of the multiplier U2 20 with a coefficient a ₂ , to the first input of the subtractor B3 21 and to the input of the delay block BZ 19, which stores the previously recorded value of the amplitude of the previous symbol z _iN . From the output U2 20, the result is fed to the second input of the subtractor V4 24. From the output of the BZ 19, the data is transmitted to the input of the multiplier U1 23 with a multiplication factor a ₁ and to the first input of the subtractor V4 24. From the output U1 23, the result is fed to the second input of the subtractor V3 21. As a result, the output of subtractor B3 21 is formed by the value

and at the output B4 24 - the value

For the constellation shown in Fig. 3, it is advisable to choose the coefficients a ₁ = a ₂ =2. In this case, the multiplication operations in (4), (5) can be implemented by editing the bit grid.

It is easy to see that the signs b ₁ and b ₂ characterize the level (amplitude) of the received symbol. Namely, if b ₁ ≥0, then the symbol amplitude is equal to 3U, and code 1 is generated at the output of RU 25. If b ₂ ≤0, then the amplitude is equal to U, and code 0 is generated at the output of RU 25. Finally, if b ₁ < 0 and b ₂ >0, then the output of RU 25 is given the previous value of the symbol amplitude code, recorded earlier in the trigger T 22.

Thus, the amplitude code of the received symbol is determined in the demodulator by the relative levels of the current z _i and previous z _iN symbols. At the same time, there is no need for absolute measurements of symbol amplitudes and their comparison with predetermined thresholds, which greatly simplifies the technical implementation of the demodulator.

The symbol amplitude code from the output of RU 25 is fed to the third input of BFR 16, determining the set of symbol phase values for the constellation shown in FIG. 2. For the constellation shown in FIG. 3, this operation is not necessary because the phase of the symbol does not depend on its amplitude. At the output of the BFR 16, according to the signal from the BTS 18, decisions are formed about the amplitude and initial phase of the received symbol (their binary codes), according to which, in the FC 26, at the end of the received symbol, a binary (in particular, four-bit for the constellations shown in Fig. 2 and Fig. 3) signal code from the AFM, issued to the output of the demodulator. Blocks BFR 16 and FC 26 can be implemented on the basis of read-only memory or field-programmable logic integrated circuit (FPGA).

. Тогда шумовые компоненты величин y_1i, y_2i (2) описываются нормальным распределением вероятностей с нулевым средним значением и дисперсией, равной сумме дисперсий отсчетов:Let us estimate the noise immunity of the demodulator. Let us assume that the useful signal (1) is distorted by a centered Gaussian random noise, the samples of which are not correlated and have a dispersion

. Then the noise components of the quantities y _1i , y _2i (2) are described by a normal probability distribution with a zero mean and a variance equal to the sum of the sample variances:

and are approximately statistically independent for adjacent symbols.

The minimum signal-to-noise ratio at the output of the quadrature channels of signal processing (the ratio of the power of the signal component of the sequence of samples to the power of the noise component) is determined as

where U is the minimum amplitude of the signal element with AFM.

The noise immunity of a signal with AFM depends on the type of constellation. For the location of the signal points shown in FIG. 3, the number of amplitude positions M ₁ =2 (two values U and 3U), and the number of phase positions is M ₂ =8 and is the same for each of the signal element amplitudes. For elements with an amplitude of 3U, the signal-to-noise ratio is greater than the minimum (6) by 9.5 dB, i.e. the probabilities of erroneous reception of elements with an amplitude of 3U are negligible compared to the probabilities of erroneous reception of elements with an amplitude of U.

In [6], an expression is given for the error probability of the optimal coherent demodulation of a signal with MPSK (MPSK) with the number of positions M ₂ in the form

Then, for equiprobable symbol amplitudes, for the demodulation error probability of the constellation APM signal in FIG. 3 get

In (8), it is assumed that the amplitudes of the received signals U and 3U are known.

In FIG. 8, the solid line shows the dependence of P _oshAFM (h ₀ ) (8) on h ₀ (6), expressed in decibels, for the constellation shown in FIG. 3, at M ₂ =8. Here, the corresponding experimental values of the probability Р _oshAFM obtained in the course of statistical simulation of the operation of a digital signal demodulator with AFM at exactly known symbol amplitudes and N=256 are marked with triangles. The circles show the results of modeling the operation of the demodulator with the choice of the amplitudes of the received symbols based on (5) and (6) at the optimal values a ₁ = a ₂ =1.8, and the rectangles (for comparison) - at the values a ₁ = a ₂ =2, other than optimal. From FIG. 8 that the proposed demodulator for the constellation shown in FIG. 3, when P o _APM <10 ^-3 provides a slight decrease in noise immunity (less than 0.5 dB) compared to demodulation with known symbol amplitudes.

In FIG. 9, the solid line shows the dependence of the demodulation error probability

for the constellation shown in Fig. 2, when M ₂ =4. The circles show the experimental values of the probability Р _oshAPM obtained in the course of statistical simulation of the demodulator operation with an accurate estimate of the comparison threshold and symbol amplitude. The discrepancy observed here between the theoretical and experimental estimates of the probability Р _{osh APM} is due to the large influence of symbols with an amplitude of 3U, since for them the number of phase positions is 12, which reduces noise immunity, while the number of phase positions of symbols with amplitude U is 4, which significantly increases their noise immunity. compared to the constellation shown in Fig. 3. In general, noise interference immunity for the constellation shown in FIG. 2 is significantly higher than the constellation shown in FIG. 3.

The triangles in Fig. 9 shows the results of modeling demodulator operation with a relative symbol amplitude estimate. It is easy to see that in this case the noise immunity of the demodulator drops significantly, but remains no worse than for the constellation shown in Fig. 3. We also note that constellations with other symbol amplitude ratios (not only 3:1) can be used in the proposed demodulator. In this case, the values of a ₁ and a ₂ may differ from those indicated above.

For the practical implementation of the presented demodulator, it is most expedient to use programmable logic integrated circuits.

The use of the invention makes it possible to demodulate a signal with two-level amplitude-phase keying with a relative estimate of the symbol amplitude and thereby increase the information transfer rate compared to the prototype and simplify the implementation of the demodulator.

Literature

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2. Kleybanov S.B., Logunova N.L. Device for receiving signals with amplitude-phase keying // Author's certificate SU 1385316, IPC H04L 27/06, dated 30.03.88, Bull. No. 12.

3. Astapkovich K.F., Buyanov V.F., Zakharov I.I., Kalmykov B.P., Lopatin S.I., Neiman A.A., Perfil’ev E.P., Sivov O.T. Device for adaptive reception of discrete signals with amplitude-phase modulation // Author's certificate SU 1309319 A1, IPC H04V 1/10, dated 07.05.87, Bull. No. 17.

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Claims (1)

Digital signal demodulator with two-level amplitude-phase keying and relative estimation of the symbol amplitude, containing a cascade-connected analog-to-digital converter (ADC) and a shift register of multi-bit codes for four samples (RS4), the first and second n-cascade channels of quadrature signal processing (QPS) ), the first and second inputs of which are connected to the odd and even outputs of the RS4, the normalizing device (NU), the first and second inputs of which are connected to the outputs of the first and second CCO, respectively, the digital arc tangent shaper (CF), the input of which is connected to the output of the NU and the generator clock pulses (GTI), characterized in that it is equipped with a decision forming unit (BFR), the first input of which is connected to the output of the digital filter, a code generator (FC), the first input of which is connected to the output of the BFR, a quadratic converter (CP), the first input of which connected to the output of the first CCC, the second input is connected to the output of the second CCC, a clock synchronization unit (BTS), a delay unit ( BZ), the first multiplier (U1), the input of which is connected to the output of the BZ, the second multiplier (U2), the third subtractor (B3), one input of which is connected to the output of U1, the fourth subtractor (V4), the first input of which is connected to the output of the BZ, and the second - to the output U2, the output of the KP is connected to a common point formed by connecting the first inputs of the BTS, BZ, input U2 and another input B3, a decision device (RU), the first input of which is connected to the output B3, and the second - to the output B4, trigger (T), one input of which is connected to the output of RU, and the output to the third input of RU, the output of the BTS is connected to a common point formed by connecting the second input of the BZ, the second input of the BFR, the other input of T and the third input of the FK, the output of the RU is connected to the second input of the FK and the third input of the BFR, the clock inputs of the ADC, PC4, the first and second KCO, BTS, BFR and FK are connected to the outputs of the GTI, the output of the FK is the output of the demodulator.

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