RU2782681C1 - Reliable cloud storage system with adjustable data redundancy - Google Patents

Abstract

FIELD: computing systems.

SUBSTANCE: invention relates to computing systems. A reliable cloud storage system with adjustable data redundancy, consisting of blocks for finding remainders modulo p_i(x), an error correction block, and a block for converting to a positional number system, contains k+r blocks for finding remainders modulo p_i(x),

where p_i(x) are coprime trinomials of the form p_i(x)=x¹⁵+x^a+1 over the field F₂, where a=[1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 13, 14] and 2≤k≤11, (k+r)<12, whose inputs are connected to the input of the original number, and the outputs are connected to the input of the corresponding XOR block of the transmitting half and the upper bits of the register for storing transmitted parts modulo pi(x), the least significant bit of which is connected to output of the corresponding XOR block of the transmitting half, the outputs of the storage registers of the transmitted parts modulo pi(x) are transferred to the cloud infrastructure for storage and/or processing.

EFFECT: increasing the reliability of cloud storage (polynomial RNS) and the ability to control redundancy.

1 cl, 2 dwg

Description

The invention relates to modular computing systems and is intended to perform the preparation of source files for reliable cloud storage by converting residue classes into a polynomial system and using a parity check code.

A system and a method for user interaction with cloud object data storages are known (patent RU2656836, published on 06/06/2018), which relate to network communication technologies. The invention improves the security of data storage. The gateway contains: three serially connected blocks, where each block contains one or more modules, where: the first block is intended for the interaction of the gateway with the user terminal, in which the modules are one or more options from: a software web server; interface for interaction with the web server; the second block is for processing requests and data from the user terminal to the first block, in which the modules are one or more of: data encryption; data decryption; data compression; data recovery; data caching; deduplication and data; data encoding; data splitting according to n,k-scheme; data recovery by n,k-scheme; the third block, consisting of modules for interaction with cloud storage, designed to implement interaction with cloud storage services through the interface for interaction with cloud storage.

The disadvantage is the limited reliability and adaptability of the redundancy of the algorithms.

There is a known coordination mechanism for choosing a cloud (patent RU2628902, published on August 22, 2017), which refers to the means for choosing and managing a public cloud computing network for placing customer account information and consists in automatically choosing a public cloud that satisfies a set of criteria defined by administrators, and providing a simplified interaction with the selected public cloud. The result is provided by performing a method for distributing the load over one or more public computer networks, while: accepting a request issued by a user of a private corporate network to update accounting information; identifying, using the means of coordination, the target computer network of said one or more public computer networks; translating said one or more commands into a format compatible with the rule language followed by the target computer network when interacting with an external source; and initiating the distribution of these one or more translated commands to the computing resources associated with the target computer network, which are designed to perform the said updating of accounting information.

The disadvantage of this method is the lack of information about the corrective properties and redundancy of the algorithms used.

A multi-channel adaptive device for encoding and transmitting data based on a system of residual classes is known (Patent UA105430, published on May 12, 2014), which contains a data separation module in the system of residual classes, a module for determining the state of the communication channel; module for adaptive distribution of message parts; a data transmission module, a data reception module, a module for detecting and correcting errors in the residual number system, a module for adaptively changing the correcting bases of the residual number system, wherein the distribution of message parts between available paths occurs adaptively depending on the size of the message and the characteristics of the paths. The proposed method improves the reliability and capacity of data transmission.

The disadvantage is the complexity of implementing redundancy adaptation algorithms.

There is a known method and device for performing calculations using residue arithmetic (Patent US7523151, published 04/21/2009), which can use logic gates to perform calculations such as multiplication by a constant, calculation of the number-theoretic logarithm of the remainder for a given base α _i and modulus p _i , as well as calculating the product of two residues modulo p _i . The use of logic gates can provide advantages over the use of ROM for table lookup functions in integrated implementations of the DSP residual system.

The disadvantage is the limited reliability and adaptability of the redundancy of the algorithms.

A device is known for converting a number from a system of residual classes into a positional code (patent RU2293437, published on August 22, 2017), which relates to computer technology and is intended for use in computing devices operating in a system of residual classes (RCS), as well as communication technology for transmission of information by SOK codes. The technical result of this invention is a reduction in the volume of equipment and an increase in performance when converting a number from RNS to a positional code. To do this, the device contains a group of persistent storage devices, a group of registers, bit-parallel modulo adder.

The essence of this device is based on grouping when adding two products and calculating the remainder by a large modulus, however, this method does not have sufficient redundancy adaptability and reliability.

по модулю последовательности верхних модулей M _i , причем верхние вычеты x _j для по меньшей мере одного конкретного верхнего модуля M _j дополнительно представляются в хранилище посредством последовательности нескольких нижних вычетов

верхнего вычета x _j по модулю последовательности нижних модулей m _i , при этом по меньшей мере один из нескольких нижних модулей m _i не делит модуль из нескольких верхних модулей M _j ; схему процессора выполненную с возможностью вычисления произведения первого целого числа x и второго целого числа y, причем первое и второе целое число хранится в хранилище в соответствии с представлением многослойной СОК, причем процессор сконфигурирован c по меньшей мере нижней процедурой умножения и верхней процедурой умножения, причем нижняя процедура умножения вычисляет произведение двух дополнительно представленных верхних вычетов x _j ,y _j , соответствующих одному и тому же верхнему модулю M _j , по модулю упомянутого верхнего модуля M _j , верхняя процедура умножения вычисляет произведение первого и второго целого числа посредством покомпонентного умножения верхних вычетов первого целого числа x _i и соответствующих верхних вычетов второго целого числа y _i по модулю соответствующего модуля M _i , при этом верхняя процедура умножения вызывает нижнюю процедуру умножения для умножения верхних вычетов, которые являются дополнительно представленными, при этом верхняя процедура умножения выполнена с возможностью приема верхних вычетов x _i ,y _i , которые меньше предварительно определенного коэффициента расширения, умноженного на соответствующий модуль

и выполнена с возможностью создания верхних вычетов Z _i произведения принятых верхних вычетов Z, которые меньше предварительно определенного коэффициента расширения, умноженного на соответствующий модуль

Known is an electronic computing device (RU2019121710, publ. 03/20/2021), configured to calculate the product of integers, and the device contains: at least the RNS of the upper layer and the RNS of the lower layer, and the RNS of the upper layer is the residual class system for the sequence of several upper modules M _i , and the RNS of the lower layer is the residual class system for the sequence of several lower modules m _i , and the integer x is represented in the storage through a sequence of several upper residues

modulo a sequence of upper modules M _i , wherein the upper residues x _j for at least one specific upper module M _j are additionally represented in the store by a sequence of several lower residues

upper residue x _j modulo the sequence of lower modules m _i , wherein at least one of several lower modules m _i does not divide the module from several upper modules M _j ; a processor circuit configured to calculate the product of a first integer x and a second integer y , wherein the first and second integer are stored in storage in accordance with the multilayer RNS representation, the processor being configured with at least a lower multiplication procedure and an upper multiplication procedure, wherein the lower the multiplication procedure calculates the product of two additionally presented upper residues x _j , y _j , corresponding to the same upper modulus M _j , modulo the said upper modulus M _j , the upper multiplication procedure calculates the product of the first and second integer by componentwise multiplication of the upper residues of the first integer number x _i and the corresponding upper residues of the second integer y _i modulo the corresponding modulo M _i , wherein the upper multiplication routine calls the lower multiplication routine to multiply the upper residues that are additionally presented, while the upper multiplication routine i is configured to receive upper residues x _i ,y _i that are less than a predetermined spreading factor multiplied by the corresponding modulus

and configured to generate upper residues Z _i of the product of received upper residues Z that are less than a predetermined spreading factor multiplied by the corresponding modulus

The disadvantage of this invention is the use of a two-level RNS, which leads to algorithmic complexity, and the present invention does not disclose the corrective capabilities of the RNS.

A neural network is known for detecting errors in a symmetrical system of residual classes (patent RU2374678, published on November 27, 2009), which relates to computer technology and can be used to build modular neurocomputers operating in a symmetrical system of residual classes. The technical result of this invention is to reduce hardware complexity. The claimed neural network contains a block of the neural network of the final ring for the formation of the highest coefficient of the generalized positional number system, a polarity shift block, an error determination block, and "errors" tires.

The disadvantage of this invention is the lack of corrective properties of non-redundant SOC.

A device for converting a binary code into a code of a system of residual classes is known (patent RU2413279, published on February 27, 2011), which relates to the field of computer technology and can be used in computing systems for converting binary codes into codes of a system of residual classes. The technical result of this invention is to increase the capacity of binary codes converted into SOC. The device contains an input register, a commutator, a multiplexer, a correction circuit, two modulo adders, two registers for fixing intermediate results of modulo summation, and three output registers.

The disadvantage of this invention is the limited corrective capabilities of the used SOC.

A device is known for detecting dynamic range overflow, determining errors and localizing a malfunction of a computing channel in computers operating in a system of residual classes (patent RU2483346, publ. 05/27/2013), which relates to computer technology and can be used in diagnosing computer systems to detect overflow dynamic range, error determination and faulty channel localization in computers operating in the system of residual classes. The technical result is to increase the speed of determining functional characteristics and reduce hardware costs. The device contains input registers, projection formation circuits, memory blocks, adders, analysis circuit, AND logic elements, trigger, projection counter.

The disadvantage of this invention is the use of an approximate Chinese remainder theorem, which can lead to coefficient rounding errors and a large number of projections when errors are detected.

умножителей, где умножители производят умножение на коэффициенты

ортогональных базисов B _i системы остаточных классов (СОК), где

– мультипликативная инверсия,

- рабочий диапазон СОК, представленных в обобщенной позиционной системе счисления (ОПСС) с основаниями

дополнительно ввели модулярный сумматор по модулю p ₁ , n умножителей на основания ОПСС

сумматор с выходом восстановленного числа и модулярный сумматор с входом расширенного основания.A device for converting numbers from a system of residual classes and expanding bases is known (patent RU2744815, published on March 16, 2021), which relates to computer technology and can be used in communication and information processing systems operating in a system of residual classes. The technical result of this invention is the expansion of functionality, namely the ability to obtain the remainder of division by an arbitrary additional modulus, as well as the restored number in the positional number system. This technical result is achieved by the fact that in a device for converting numbers from the system of residual classes and expanding the bases with modules p ₁ , p ₂ , ..., p _n , containing n inputs of residues, the output of the remainder by the extended base, n registers for storing residues, n- 1 modulo adder, triangular matrix of

multipliers, where the multipliers multiply by the coefficients

orthogonal bases B _i of the residual class system (RCS), where

is the multiplicative inversion,

- operating range of RNS, presented in the generalized positional number system (OPSS) with bases

additionally introduced a modular adder modulo p ₁ , n multipliers to the bases of the OPSS

an adder with a recovered number output and a modular adder with an extended base input.

The disadvantage of this invention is the use of a generalized positional number system, which in most cases excludes the parallel implementation of algorithms.

Known neural network for detecting, localizing and correcting errors in the system of residual classes (patent RU2301442, publ. 20.06.2007), which relates to computing and can be used in modular neurocomputer systems. The technical result is an increase in the speed of error correction, a reduction in equipment, as well as an expansion of functionality. To do this, the neural network contains an input layer, finite ring neural networks for determining the error syndrome, a memory block for storing constants, neural networks for calculating the correct result, and an OR element for determining the presence of an error.

The disadvantage of this invention is the difficulty in determining the bases of the RNS, which caused errors.

A finite ring neural network is known (patent RU2759964, publ. 11/19/2021), which refers to neurocomputer technology and is intended for classifying classes of numbers according to a given modulo p. The technical result is to increase the speed of the neural network in the classification of residues. The device contains input, hidden and output layers of neurons, two registers, a group of blocks of AND elements and a group of AND elements.

The disadvantage of this invention is the algorithmic complexity associated with the calculation of indices of numbers.

Known multi-channel systolic processor for calculating polynomial functions (patent RU2737236, publ. 11/26/2020), which relates to computing and can be used in specialized systems for multi-channel digital signal processing and in measuring and computing systems. The present invention implements calculations using a parallel non-positional RNS code. In this system, calculations are carried out in parallel on low-bit residues determined by the bases of the system of residual classes, which allows using ROM to perform addition and multiplication operations, while the execution time of these operations will be determined by the sampling time from the ROM. Thus, parallelization at the level of arithmetic operations and independent data processing based on RNS bases, implemented by samples from ROM, increases the speed of digital signal processing using polynomial functions without additive and multiplicative errors. The invention is aimed at increasing the speed and accuracy of multi-channel digital signal processing through the use of a system of residual classes.

The disadvantage of this invention is the limited corrective capabilities of the used SOC.

A device is known for correcting errors in a polynomial system of residue classes using pseudo-orthogonal polynomials (patent RU2393529, publ. 06/27/2010), which relates to computer technology for monitoring and correcting errors in the transmission of information and for performing arithmetic operations in extended Galois fields GF(2 ^v ). The technical result is to reduce circuit costs. The device contains a register, an adder and an error syndrome calculation unit, which is a three-layer neural network containing neurons forming the first, second and third layers of neurons.

The disadvantage of this invention is the complexity of the algorithms associated with the use of pseudo-orthogonal polynomials.

The closest in technical essence is a device for calculating the sums of paired products in a polynomial system of residue classes (patent RU2622881, publ. 06/20/2017), chosen as a prototype. SUBSTANCE: invention relates to computer engineering and can be used in signal processors, in digital filters for error detection and correction. The technical result achieved in the implementation of this invention is the reduction of hardware costs. The specified technical result is achieved due to the fact that the number of transitions outside the operating range is determined only by the values of the residuals on the working bases of the PSV, which can be calculated in advance and taken into account in the structure of the neural network of the correction unit. This makes it possible to abandon the transition count and the additional layer of the neural network that are in the error correction block.

The disadvantage of this invention is the complexity of error correction associated with a large amount of stored data and the complexity of determining the erroneous bit.

The technical result of this invention is to improve the correction properties of the code of the polynomial system of residue classes (polynomial RNS) and the ability to control redundancy.

где p_i(x) – взаимно простые трехчлены вида p_i(x)=x¹⁵+x^a+1 над полем F₂, где a=[1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 13, 14] и 2≤k≤11, (k+r)<12, входы которых связаны с входом исходного числа, а выходы соединены с входом соответствующего блока XOR передающей половины и старшими битами регистра хранения передаваемых частей по модулю p_i(x), младший бит которого соединен с выходом соответствующего блока XOR передающей половины, выходы регистров хранения передаваемых частей по модулю p_i(x) передаются в облачную инфраструктуру для хранения и/или обработки, данных из облачной инфраструктуру поступают на регистры хранения получаемых частей по модулю p_i(x), все биты выходов которых соединены с входами блоков XOR принимающей половины, а старшие биты выходов соединены с четными входами блока коррекции ошибок, нечетные входы которого соединены с выходами блоков XOR принимающей половины, блока коррекции ошибок анализирует количество принятых без ошибок значений и подает на выходы значения принятого остатка

по модулю p_i(x),

где P(x) – произведение модулей p _i (x) по которым не возникло ошибок, а принятых с ошибкой данные

,

,

обнуляются, значения

,

,

с выходов блока коррекции ошибок поступают на входы блока перевода в позиционную систему счисления, выход которого является информационным выходом устройства, при этом блок перевода в позиционную систему счисления содержит k+r умножителей многочленов по модулю p_i(x), k+r умножителей многочленов и сумматор многочленов, при этом на входы умножителей многочленов по модулю p_i(x) поступают соответствующие значения

,

и производятся вычисления

результаты которых перемножаются с

в соответствующих умножителях многочленов, выходы которых соединены с входами сумматора многочленов, выход которого является выходом блока перевода в позиционную систему счисления.The technical result is achieved by the fact that a reliable cloud storage system with adjustable data redundancy, consisting of blocks for finding residues modulo p_i(x), an error correction block and a translation block into a positional number system, contains k + r blocks for finding residues modulo p_i(x),

where p_i(x) are coprime trinomials of the form p_i(x)=x^fifteen+x^a+1 over F field₂, where a=[1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 13, 14] and 2≤k≤11, (k+r)<12, whose inputs are related to the input of the original numbers, and the outputs are connected to the input of the corresponding XOR block of the transmitting half and the high bits of the register storage of transmitted parts modulo p_i(x), the least significant bit of which is connected to the output of the corresponding XOR block of the transmitting half, the outputs of the registers storage of transmitted parts modulo p_i(x) are transferred to the cloud infrastructure for storage and / or processing, data from the cloud infrastructure is received to the storage registers of the received parts modulo p_i(x), all output bits of which are connected to the inputs of the XOR blocks of the receiving half, and the high-order bits of the outputs are connected to the even inputs of the error correction block, the odd inputs of which are connected to the outputs of the XOR blocks of the receiving half, the error correction block analyzes the number of values received without errors and supplies to the outputs of the value of the accepted balance

mod p_i(x),

whereP(x) – product of modulesp _i (x) for which no errors occurred, but data received with an error

,

,

reset, values

,

,

from the outputs of the error correction block are fed to the inputs of the block of translation into the positional number system, the output of which is the information output of the device, while the block of the translation into the positional number system contains k + r multipliers of polynomials modulo p_i(x), k+r polynomial multipliers and polynomial adder, while the inputs of polynomial multipliers modulo p_i(x) corresponding values are received

,

and calculations are made

the results of which are multiplied with

in the corresponding multipliers of polynomials, the outputs of which are connected to the inputs of the adder of polynomials, the output of which is the output of the conversion unit to the positional number system.

The essence of the invention is based on the following mathematical apparatus. In the polynomial system of residue classes, any polynomial F(x) is represented as a set of residues

F(x)=(f ₁ (x), f ₂ (x),…, f _k (x), f _{k +1} (x),.., f _{k +r} (x)) (1),

where f _i (x)=rest(F(x)/p _i (x)), the remainder of the division of polynomials; p _i (x) are coprime trinomials of the form p _i (x)=x ¹⁵ +x ^a +1 over the field F ₂ , where a=[1,2,3,4,5,6,7,8,9, 11,13,14]. In this case, in this ( k,n ) system, k working bases and r control bases are used, n=k+r . To move from a binary representation to a polynomial one, we will associate a number in the binary system 1011 ₂ with a polynomial x ³ +x+1 over F ₂ , i.e. 1 corresponds to 1 before the corresponding degree. Calculations over the field F ₂ correspond to the XOR operation, modulo 2 summation.

Consider the representations of the polynomial F(x) given in the binary system F(x)=x ¹⁶ +x ¹⁴ +x ¹³ +x ¹¹ +x ¹⁰ +x ⁸ +x ⁷ +x ⁵ +x ⁴ +x ² +x+1 = 10110110110110111 ₂ in the redundant polynomial system of residual classes (3,4) with modules p ₁ (x)=x ¹⁵ +x+1, p ₂ (x)=x ¹⁵ +x ² +1, p ₃ (x)=x ¹⁵ +x ³ +1, p ₄ (x)=x ¹⁵ +x ⁴ +1 , we get:

представляется в виде:

in binary system

is presented in the form:

представляется в виде:

in binary system

is presented in the form:

представляется в виде:

in binary system

is presented in the form:

представляется в виде:

in binary system

is presented in the form:

One of the simplest error-correcting coding mechanisms is parity check codes, which is equal to the modulo 2 sum of all bits of the original number. The check is carried out similarly by modulo 2 summation. Let's add the parity bit to the obtained values:

where “|” - concatenation.

Thus, an encoded number has been obtained, which can be transferred to one or more clouds for storage or processing, since the codes of the system of residual classes allow calculations to be made on the bits f _i independently and the result will be comparable with the desired result.

мы получили

где

сложение по модулю 2. Следовательно на вход системы мы получаем:Consider the decoding process. Let the error be in the third projection and instead

we got

where

addition modulo 2. Therefore, at the input of the system we get:

- не содержат ошибок, а

– содержит ошибку. Следовательно, для восстановления искомого значения мы будем использовать

. Отбросив от значений

младший бит проверки на четность, получим значения разрядов

в полиномиальной системе классов вычетов.Let's check the correctness of each correction using the parity code, we get:

- do not contain errors, and

- contains an error. Therefore, to restore the desired value, we will use

. Discarding from values

the least significant bit of the parity check, we get the values of the digits

in the polynomial system of residue classes.

Using the Chinese remainder theorem, we calculate the value

получим:Compute

we get:

получим:Compute

we get:

получим:Calculate the weights

we get:

Compute

совпадает с исходным F(x) несмотря на возникновение ошибки по одному из оснований.It is obvious that the resulting restored value

coincides with the original F(x) despite the occurrence of an error due to one of the bases.

The invention is illustrated by figures 1 and 2.

где p _i (x) – взаимно простые трехчлены вида p _i (x)=x ¹⁵ +x ^a +1 над полем F₂, где a=[1,2,3,4,5,6,7,8,9,11,13,14]. При этом при построении системы может быть использовано 12 многочленов, таким образом 2≤k≤11, (k+r)<12. Блоки 1.i нахождения остатков по модулю p _i (x) могут быть выполнены как с использованием вычислительных устройств, например, интегральных схем или FPGA, так и в виде памяти, которая в ответ на значение исходного числа F(x) подает на выход блока 1.i нахождения остатков по модулю pi(x) остаток fi(x) от деления на модуль pi(x).Figure 1 shows a general diagram of a reliable cloud storage system with managed data redundancy. Initial valueF(x) enters the inputs of blocks 1.i of finding residues modulop _i (x),

wherep _i (x) are coprime trinomials of the formp _i (x)=x ^fifteen +x ^a +1 over field F₂, wherea=[1,2,3,4,5,6,7,8,9,11,13,14]. At the same time, 12 polynomials can be used when building the system, thus 2≤k≤11, (k+r)<12. Blocks 1.i finding modulo residuesp _i (x) can be performed both using computing devices, for example, integrated circuits or FPGA, and in the form of memory, which, in response to the value of the initial number F(x), supplies the remainder fi to the output of block 1.i for finding residues modulo pi(x). (x) from dividing by the modulo pi(x).

с четным количеством единиц в двоичном представлении.Residual valuesf _i (x)from the outputs of blocks 1.i finding modulo residuesp _i (x) arrive at the XOR 2.i blocks of the transmitting half, which contain the modulo 2 sum of all bits of the remainderf _i (x), results from the outputs of the XOR 2.i blocks of the transmitting half arrive on the least significant bit register storage 3.i transmitted parts modulop _i (x), the upper bits of which are transferred to the values of the remaindersf _i (x) from the outputs of blocks 1.i finding modulo residuesp _i (x), thus concatenating the values for parity, i.e. in registers storage 3.i transmitted parts modulop _i (x) values are always stored

with an even number of ones in binary representation.

Data from register outputs storage 3.i transmitted parts modulop _i (x) are transferred to the cloud infrastructure 4, which can be used both for storing and processing data, since a feature of the system of residual classes is the ability to perform arithmetic operations of addition and multiplication independently for each module. At the same time, the cloud infrastructure can be represented by one or several cloud providers, which will allow distributing data during storage, thereby increasing the reliability of data recovery in the event of failure of one or more clouds due to the redundant structure of the polynomial system of residue classes.

поступают на входы блоков XOR 6.i принимающей половины, выходы которых поступают на нечетные входы блока коррекции ошибок 7, на четные входы которого поступают значения

старших бит выходов регистров 5.i хранения получаемых частей по модулю p _i (x). After processing or storage, the data enters the registers 5.i for storing the received parts modulo p _i (x), from where the total received values

are fed to the inputs of the XOR blocks 6.i of the receiving half, the outputs of which are fed to the odd inputs of the error correction block 7, to the even inputs of which the values

the highest bits of the outputs of the registers 5.i store the received parts modulo p _i (x).

. Данный блок анализирует количество принятых без ошибок значений, и если их меньше k, то восстановление числа невозможно и на 3(k+r)+4-й выход блока коррекции ошибок 7 поступает значение «коррекция невозможна».Thus, the odd inputs of the error correction block 7 receive values indicating the presence of a single error for each base, and the even inputs receive both erroneous and true values

. This block analyzes the number of values received without errors, and if they are less than k, then the recovery of the number is impossible and the 3(k+r)+4th output of the error correction block 7 receives the value "correction is impossible".

где P(x) – произведение модулей p _i (x) по которым не возникло ошибок. Для принятых с ошибкой данных значения

обнуляются.In other cases, the outputs of the error correction block 7 receive the values

where P(x) is the product of modules p _i (x) for which no errors occurred. For erroneously received data values

are reset.

с выходов блока коррекции ошибок 7 поступают на входы блока 8 перевода в позиционную систему счисления, выход которого является информационным выходом устройства.Values

from the outputs of the error correction block 7 are fed to the inputs of the block 8 of the transfer to the positional number system, the output of which is the information output of the device.

умножители 9.i производят вычисления

Результаты поступают на умножители 10.i многочленов, в которых происходит умножение результата на

Затем результаты поступают на сумматор многочленов 11, выход которого является выходом блока 8 перевода в позиционную систему счисления.The figure 2 discloses a diagram of block 8 of the transfer to the positional number system. The inputs of multipliers 9.i of polynomials modulo p _i (x) receive the values

multipliers 9.i produce calculations

The results are fed to multipliers 10.i of polynomials, in which the result is multiplied by

Then the results are fed to the adder of polynomials 11, the output of which is the output of the block 8 of the transfer to the positional number system.

The advantage of this device is the improvement of the correction properties of the code of the polynomial system of residue classes and the ability to control redundancy. Since the parity codes easily detect erroneous received values, there is no need to build an n-1 projection of the number and perform complex calculations to restore the number in the error correction block used. Varying the values of k and r will provide a sufficient level of redundancy and reliability of data storage and processing by the cloud infrastructure.

The implementation of the entire device is possible using field-programmable logic integrated circuits (FPGA), application-specific integrated circuits, as well as in the form of a computer operation algorithm, and can be used as a separate device or as a coprocessor to perform reliable cloud storage with adjustable data redundancy.

Claims (1)

Reliable cloud storage system with adjustable data redundancy, consisting of blocks for finding residuals modulo p_i(x), an error correction block and a translation block into a positional number system, characterized in that it contains k + r blocks of finding remainders modulo p_i(x),

, where p_i(x) - coprime trinomials of the form p_i(x)=x^fifteen+x^a+1 over F field₂, where a=[1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 13, 14] and 2≤k≤11, (k+r)<12, whose inputs are related to the input of the original numbers, and the outputs are connected to the input of the corresponding XOR block of the transmitting half and the high bits of the register storage of transmitted parts modulo p_i(x), the least significant bit of which is connected to the output of the corresponding XOR block of the transmitting half, the outputs of the registers storage of transmitted parts modulo p_i(x) are transferred to the cloud infrastructure for storage and / or processing, the data from the cloud infrastructure goes to the storage registers of the received parts modulo p_i(x), all output bits of which are connected to the inputs of the XOR blocks of the receiving half, and the high-order bits of the outputs are connected to the even inputs of the error correction block, the odd inputs of which are connected to the outputs of the XOR blocks of the receiving half, the error correction block analyzes the number of values received without errors and supplies to the outputs of the value of the accepted balance

mod p_i(x),

,

, whereP(x) - product of modulesp _i (x), for which no errors occurred, and the data received with an error

,

,

reset, values

,

,

from the outputs of the error correction block are fed to the inputs of the block of translation into the positional number system, the output of which is the information output of the device, while the block of the translation into the positional number system contains k + r multipliers of polynomials modulo p_i(x), k+r polynomial multipliers and polynomial adder, while the inputs of polynomial multipliers modulo p_i(x) corresponding values are received

,

and calculations are made

, the results of which are multiplied with

in the corresponding multipliers of polynomials, the outputs of which are connected to the inputs of the adder of polynomials, the output of which is the output of the conversion unit to the positional number system.

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