RU2778211C1 - Printing component with a memory circuit - Google Patents

Abstract

FIELD: printing.

SUBSTANCE: memory circuit for a printing component includes multiple I/O platforms including a platform for analogue signal, for connection to multiple signal paths whereby working signals are communicated to the printing component. The memory component stores the memory values associated with the printing component, and the control circuit, in response to a sequence of working signals on the I/O platforms, representing the memory reading, transmits an analogue signal to the platform for analogue signal, providing the value of the analogue electrical signal on the platform for analogue signal, representing the stored memory values selected by reading the memory.

EFFECT: provided memory for a printing component.

11 cl, 15 dwg

Description

Background of the invention

[0001] Some printing components may include an array of nozzles and/or pumps, each of which includes a fluid chamber and a fluid activator, wherein the fluid activator may be actuated to cause movement of fluid in the chamber . Some exemplary fluid dies may be print heads, and the fluid may correspond to inks or printing agents. The print components include printheads for 2D and 3D printing systems and/or other high precision fluid distribution systems.

Brief description of the drawings

[0002] FIG. 1 is a block and circuit diagram illustrating a memory circuit for a printing component according to one example.

[0003] FIG. 2 is a block and circuit diagram illustrating a memory circuit for a printing component according to one example.

[0004] FIG. 3 is a block and circuit diagram illustrating a memory circuit for a printing component according to one example.

[0005] FIG. 4 is a block and circuit diagram illustrating a memory circuit for a printing component according to one example.

[0006] FIG. 5 is a block and circuit diagram illustrating a memory circuit for a printing component according to one example.

[0007] FIG. 6A and 6B are block and circuit diagrams illustrating a wired flexible substrate for connecting a memory circuit to a printing component, according to one example.

[0008] FIG. 7 is a block and circuit diagram illustrating a memory circuit for a printing component according to one example.

[0009] FIG. 8 is a block and circuit diagram illustrating a memory circuit for a printing component according to one example.

[0010] FIG. 9 is a block and circuit diagram illustrating a memory circuit for a printing component according to one example.

[0011] FIG. 10 is a block and circuit diagram illustrating a memory circuit for a printing component according to one example.

[0012] FIG. 11 is a block and circuit diagram illustrating a flexible wired substrate for connecting a memory circuit to a printing component according to one example.

[0013] FIG. 12 is a block and circuit diagram illustrating a memory circuit for a printing component according to one example.

[0014] FIG. 13 is a block and circuit diagram illustrating a memory circuit for a printing component according to one example.

[0015] FIG. 14 is a block and circuit diagram illustrating a wired flexible substrate for connecting a memory circuit to a printing component according to one example.

[0016] FIG. 15 is a block and schematic diagram illustrating a fluid ejection system according to one example.

[0017] Throughout the drawings, like reference numerals denote like, but not necessarily identical, elements. The figures are not necessarily drawn to scale, and the size of some parts may be exaggerated to more clearly illustrate the example shown. In addition, the drawings provide examples and/or implementations consistent with the description; however, the description is not limited to the examples and/or implementations provided in the drawings.

Detailed description of the invention

[0018] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and which show, by way of illustration, specific examples in which the disclosure may be practiced. It should be understood that other examples may be used and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims. It should be understood that the features of the various examples described herein may be combined, in part or in whole, with each other, unless expressly stated otherwise.

[0019] Exemplary fluid matrices may include fluid activators (e.g., for fluid ejection and recirculation), fluid activators may include thermistor activators, piezoelectric membrane activators, electrostatic membrane activators, membrane activators mechanical/shock action, magnetostrictive actuators, or other suitable devices that can cause fluid movement in response to electrical activation. The fluid matrices described herein may include a plurality of fluid activators, which may be referred to as an array of fluid activators. An activation event may be referred to as a single or simultaneous activation of fluid matrix fluid activators causing fluid movement. An example of an activation event is a fluid excitation event that causes fluid to be jetted through a nozzle.

[0020] In exemplary fluid matrices, an array of fluid activators may be placed in sets of fluid activators, each such set of fluid activators may be referred to as a "base module (primitive)" or "drive primitive". The number of fluid activators in a primitive may be referred to as the size of the primitive. In some examples, the set of fluid activators of each primitive is addressable with the same set of activation addresses, with each fluid activator of the primitive corresponding to a different activation address from the set of activation addresses, the addresses being reported on the address bus. In some examples, during an activation event, in each primitive, a fluid activator corresponding to an address on the address bus will be activated (e.g., fired) in response to a drive signal (also referred to as a drive pulse) based on the state of the selection data (e.g., the state of a bit selection) corresponding to the primitive (sometimes also called nozzle data or primitive data).

[0021] In some cases, the electrical and fluid functionality limitations of the fluid matrix may limit the number of fluid activators that can be activated simultaneously during an activation event. The primitives provide a selection of subsets of fluid activators that can be simultaneously activated for a given activation event to comply with such functional constraints.

[0022] As an example, if the matrix for fluid includes four primitives, with each primitive having eight fluid activators (with each fluid activator corresponding to a different address from, for example, a set of addresses from 0 to 7), and when electrical and fluid constraints limit activation to one fluid activator per primitive, a total of four fluid activators (one from each primitive) can be activated at the same time for a given activation event. For example, for the first activation event, the corresponding fluid activator of each primitive corresponding to address "0" may be activated. For the second activation event, the corresponding fluid activator of each primitive corresponding to address "5" may be activated. As will be appreciated, such an example is provided for illustrative purposes only, and fluid matrices contemplated herein may contain more or fewer fluid activators per primitive, and more or fewer primitives per matrix.

[0023] Exemplary fluid matrices may include fluid chambers, orifices, and/or other features that may be defined by surfaces fabricated on a fluid matrix substrate by etching, micromachining (e.g., photolithography), micromachining processes or other suitable processes or combinations thereof. Some exemplary substrates may include silicon substrates, glass substrates, gallium arsenide substrates, and/or other such suitable types of substrates for micromachined devices and structures. As used herein, fluid chambers may include ejection chambers in fluid communication with nozzle openings from which fluid may be ejected and fluid channels through which fluid may be transported. In some examples, the fluid conduits may be microfluidic conduits, and as used herein, the microfluidic conduit may correspond to a conduit of a sufficiently small size (e.g., nanometer scale, micrometer scale, millimeter scale, etc.) to allow transportation small volumes of fluid (eg, picoliter scale, nanoliter scale, microliter scale, milliliter scale, etc.).

[0024] In some examples, a fluid activator may be provided as part of a nozzle where, in addition to the fluid activator, the nozzle includes an ejection chamber in fluid communication with the nozzle orifice. The fluid activator is positioned relative to the fluid chamber such that activation of the fluid activator causes movement of fluid in the fluid chamber, which can cause a drop of fluid to be ejected from the fluid chamber through the nozzle orifice. Accordingly, a fluid activator provided as part of a nozzle may sometimes be referred to as a fluid ejector or ejection activator.

[0025] In some examples, a fluid activator may be provided as part of a pump where, in addition to the fluid activator, the pump includes a fluid passage. The fluid activator is positioned relative to the fluid channel such that activation of the fluid activator creates fluid movement in the fluid channel (e.g., a fluid microchannel), moving the fluid in the fluid matrix, such as, for example, between a source fluid and nozzle. An example of fluid movement/injection in a matrix may sometimes be referred to as micro-recirculation. A fluid activator configured to move fluid in a fluid channel may sometimes be referred to as a non-ejection or micro-recirculation activator.

[0026] In one exemplary nozzle, the fluid activator may comprise a thermal activator where the activation of the fluid activator (sometimes referred to as "energization") heats the fluid to form a gaseous actuating bubble in the fluid chamber that can cause a fluid droplet to be ejected. from the nozzle hole. As described above, fluid activators may be placed in arrays (such as columns) where the activators may be implemented as jet ejectors and/or pumps, with selective operation of the jet ejectors causing a drop of fluid to be ejected and selective operation of the pumps causing displacement. fluid in a fluid matrix. In some examples, an array of fluid activators may be placed in primitives.

[0027] Some fluid matrices receive data in the form of data bursts, sometimes referred to as drive bursts or drive burst data bursts. In some examples, such data packets may include configuration data and selection data. In some examples, the configuration data includes data for configuring functions on a chip, such as address bits representing the address of fluid activators to be activated as part of a drive operation, drive pulse data for configuring drive pulse characteristics, and thermal data for configuring thermal operations such as heating and perception (registration). In some examples, data packets are configured with head and tail sections including configuration data and a main section including selection data (primitive). In exemplary fluid matrices, in response to receiving a data packet, the control circuitry on the matrix employs address decoders/drivers, providing an address on the address line, activation logic, activating selected fluid activators (e.g., based on address, selection data, and drive pulse), and configuration logic, configuring operations of functions on the matrix, such as, for example, drive pulse configuration, crack registration, and thermal operations based on the configuration data and the modal signal.

[0028] In addition to fluid activators, some exemplary fluid matrices include on-chip memory (e.g., non-volatile memory (NVM)) for exchanging information (e.g., memory bits) with external devices, such as a printer, to help in the operation of controlling fluid devices, including the operation of fluid activators and other devices (eg, heaters, crack sensors) to control fluid release. In examples, such information may include, for example, thermal conditions, offsets, region information, color map, fluid levels, and number of nozzles.

[0029] Memory devices (memory) typically include service circuits (eg, address, decode, read and write modes, etc.) that are expensive to implement and consume relatively large amounts of silicon area on a chip. However, since a similar circuitry is applied in selecting, activating, and communicating data to an array of fluid activators, some exemplary fluid matrices have multipurpose control circuit portions for selecting and communicating data to fluid activators (including, for example, high speed data link portions) to select also the memory elements from the memory array.

[0030] To further save space and reduce the complexity associated with multi-bus architectures, some exemplary fluid arrays use a single-lane analog bus that is communicatively coupled in parallel with memory elements to read and write information to/from memory elements in common. the single-band analog bus you are using (also sometimes referred to as the registration bus). In some examples, the single lane bus is capable of reading from/writing to memory elements individually or in various combinations of memory elements in parallel. Additionally, some exemplary fluid matrices include devices such as crack sensors, temperature sensors, and heating elements that may also be connected to a single line analog bus for sensing and control.

[0031] In exemplary fluid arrays having on-chip memories, in addition to reporting selection data for selecting fluid activators to activate as part of a fluid activation operation, data packets may report selection data for selecting memory elements to which be accessed as part of a memory access operation (eg, a read/write operation). To distinguish between different modes of operation, such as fluid activation mode and memory access mode, exemplary fluid matrices may employ different operating protocols for different modes of operation. For example, the fluid matrix may apply a single operating signal protocol sequence such as data (eg, data packets) received via data (DATA) pads, a clock signal received through a clock pad (CLK), a mode signal received through a mode pad (MODE) and a drive signal received through a drive pad (FIRE) identifying an operation of the fluid activator, and another sequence of such signals identifying memory access operations (e.g., reading and record).

[0032] In exemplary fluid arrays, the on-chip storage elements may be one time programmable (OTP) elements. During manufacture, information may be written to the memory elements at the end of the manufacturing process, including after the fluid matrix may be placed as part of a printhead or pen. If the memory is found to be corrupted (eg, has one or more bad bits that will not be programmed correctly), the fluid matrix may not function correctly such that the fluid matrix, printhead, and pen are also damaged. Additionally, even though the memory service circuit can be shared with the fluid activator selection and activation circuit, incorporating on-chip memory elements consumes silicon area and increases the size of the fluid matrix.

[0033] The present disclosure, as will be described in more detail herein, provides a printing component, such as a print head or a print pen, for example, including a fluid matrix having an array of fluid activators. The fluid matrix is connected to a series of input/output (I/O) contacts (terminals), which provide operating signals to control the operation of the fluid matrix, including the operations of ejection of fluid activators, while the terminals (pads) I/ O include a pin for registering an analog signal. The printing component includes a memory chip separate from the fluid matrix connected to the I/O terminals, wherein the memory chip is configured to store memory values associated with the printing component, such as, for example, manufacturing data, thermal conditions, offsets, information about the region, color map, number of nozzles and type of fluid. According to one example, in response to observing operating signals at the I/O pins representing the memory access sequence for the stored memory values, the memory chip applies an analog signal to the register pin based on the stored memory values corresponding to the memory access sequence.

[0034] As will be described in more detail herein, in one example, the memory chip replaces or replaces a damaged memory array on the fluid array, thereby enabling the fluid array and the printing component using the fluid array, such as, for example, , typing pen, stay working. In another example, a memory chip may be used in place of a fluid array memory array, thereby allowing the fluid array and the print head using the fluid array to be smaller. In another example, a fluid matrix may be used to supplement a memory array on a fluid matrix (eg, to expand memory capacity).

[0035] FIG. 1 is a block and circuit diagram generally illustrating a memory circuit 30 according to one example of the present disclosure for a printing component such as a printing component 10. The memory circuit 30 includes a control circuit 32 and a memory component 34 storing a series of memory values 36 associated with operation of the printing component 10. The memory component 34 may comprise any suitable storage element including any number of, for example, non-volatile storage devices (NVMs) such as EPROM, EEPROM, flash memory, NV RAM, fusible link. In one example, the storage values 36 may be values stored in a lookup table, where such a lookup table may be an array of index data, with each storage element having a corresponding address or index. In the examples, each memory value 36 represents a data bit having a bit state of "0" or "1", or an analog value (eg, voltage or current) corresponding to "0" and "1". In the examples, the memory circuit 30 is a chip (chip on a chip).

[0036] The memory circuit 30 includes a series of input/output (I/O) pads 40 for connecting to a plurality of signal paths 41 that provide operating signals to the printing component 10. In one example, the plurality of I/O pads 40 includes a pad 42 CLK, data pad 44, drive pad 46, mode pad 48, and analog signal pad 50, which will be described in more detail below. In the examples, the control circuit 32 controls the operating signals transmitted to the printing component 10 via the I/O pads 40. In one example, upon observing a sequence of operating signals representing a memory read (e.g., a “read” protocol), the control circuit 32 applies an analog electrical signal to the pad. 50 for an analog signal, providing in the analog pad 50 an analog electrical signal value representing the stored memory values 36 selected by reading the memory. In the examples, the analog electrical signal supplied to the analog signal pad 50 may be one of an analog voltage signal and an analog current signal, and the analog electrical signal may be one of a voltage level and a current level. In the examples, the analog signal pad 50 may be an analog signal acquisition pad connected to the analog signal acquisition circuit, and is sometimes referred to here as the acquisition pad 50.

[0037] In one example, upon observing a sequence of operating signals representing a memory write (the "write" protocol), the control circuit 32 corrects the values for the stored memory values.

[0038] FIG. 2 is a block and schematic diagram generally illustrating a memory chip 30 according to one example for a printing component 10, where the printing component 10 may be a print pen, a print cartridge, a print head, or may include a series of print heads. In the examples, the printing component 10 may be removable and replaceable in the printing system. The printing component may be a refillable device and may include a tank, chamber, or reservoir for a fluid such as ink. The printing component may include a replaceable fluid reservoir.

[0039] In one example, the printing component 10 includes a fluid ejection circuit 20, a memory circuit 30, and a series of input/output (I/O) pads 40. The fluid ejection circuit 20 includes an array 24 of fluid activators 26 . In the examples, fluid activators 26 may be configured to form a series of primitives, with each primitive having a series of fluid activators 26. Part of the fluid activators 26 may be formed as part of a fluid ejection nozzle and another part may be formed as part of a fluid circulation pump. In one example, the fluid ejection circuit 20 comprises a matrix (crystal).

[0040] In one example, the I/O pads 40 of the memory circuit 30 include a CLK pad 42, a data pad 44, a drive pad 46, a mode pad 48, and an analog signal pad 50 that are connected to a plurality of signal paths that transmit a series of digital and analog operating signals for operating the fluid ejection circuit 20 between the printing component 10 and a separate device such as a printer 60. The CLK pad 42 may transmit a clock signal, the data pad 44 may transmit data including configuration data and selection data, including including in the form of drive pulse group (FPG) data packets, the drive pad may transmit a drive signal, such as a drive pulse, initiating the operation of the fluid ejection circuit 20 (such as, for example, the operation of selected fluid activators 26), the mode pad 48 may indicate various modes of operation of the fluid ejection circuit 20, and the registration area 50 can transmit analog electrical signals for recording and operating the detection elements of the fluid release circuit 20 (such as, for example, crack sensors, heat sensors, heaters) and the memory elements of the fluid release circuit 20, such as will be described in more detail below.

[0041] In one example, the memory values 36 of the memory component 34 of the memory circuit 30 are memory values associated with the printing component 10, including memory values associated with the operation of the fluid ejection circuit 20, such as, for example, the number of nozzles, ink levels , operating temperatures, manufacturing information. In examples like those described above, when observing a sequence of operating signals representing a memory read (e.g., a "read" protocol), control circuit 32 applies an analog electrical signal to analog signal pad 50, providing analog electrical signal value to analog pad 50 , representing the stored memory values 36 selected by reading the memory.

[0042] In an example where the fluid ejection circuit 20 is implemented as a fluid matrix, by locating the memory circuit 30 separately from the fluid ejection circuit 20, such a fluid matrix can be made smaller so that the print head , including the fluid matrix 20, may be smaller.

[0043] In one example, the fluid ejection circuit 20 may include a memory circuit 28 including a series of memory elements 29 storing memory values associated with the operation of the printing component 10 and the fluid ejection circuit 20. In one case, when the memory array 28 includes corrupted memory elements 29, the memory circuit 30 may serve as a substitute memory (replacement memory) for the memory array 28 with stored memory values 36 replacing the values stored by the memory elements 29. Alternatively, the memory circuit 30 may supplement the memory array 28 (increase the storage capacity associated with the fluid ejection circuit 20). In one example, as will be described in more detail below, such as when used to replace or replace a damaged on-chip memory array 28, the memory circuit 30 may be connected to the printing component 10 via a wired overlay substrate (e.g., a flexible overlay) that includes (contact) pads that cover and contact the I/O 40 pad series.

[0044] FIG. 3 is a block and circuit diagram generally illustrating a memory circuit 30 coupled to a printing component 10 including a fluid ejection circuit 20 having a memory array 28 and a memory circuit 30 (e.g., a memory chip) according to one example of the present disclosure. In one case, as will be described in more detail below, the memory circuit 30 replaces the memory array 28 of the fluid ejection circuit 20, for example, when the memory array 28 is damaged.

[0045] The fluid ejection circuit 20 includes an array 24 of fluid activators 26 and an array 28 of memory elements 29. In one example, an array of 24 fluid activators 26 and an array of 28 memory elements 29 are each arranged to form a column, with each column arranged in groups being referred to as a primitive, with each primitive P ₀ -P _M including a series of fluid activators. media, indicated as fluid activators F ₀ -F _N , and a series of memory elements, indicated as memory elements M ₀ -M _N . Each primitive P ₀ -P _M uses the same set of addresses, illustrated as addresses A ₀ -A _N . In one example, each fluid activator 26 has a corresponding memory element 29 addressed to the same address, for example, each of the fluid activator F ₀ and the memory element M ₀ of primitive P ₀ corresponds to address A ₀ .

[0046] In one example, each fluid activator 26 may have more than one corresponding memory element 29, such as two corresponding memory elements 29, as indicated by the dashed memory elements 29, when the memory element array 28 is laid out forming two columns of memory elements 29 such as columns 28 ₁ and 28 ₂ , with each additional memory element sharing a corresponding address. In other examples, each fluid activator 26 may have more than two corresponding memory elements 29 when each additional memory element 29 is placed as part of an additional column of memory elements 29 of the memory array 28. According to one example, as will be described in more detail below, when more than one column of memory elements 29 is used such that more than one memory element 29 shares the same address, each column of memory elements 29 may be separately addressed (or accessed). ) using the column bits in the burst group data packet identifying the column to be accessed.

[0047] In one example, the fluid release circuit 20 may include a series of sensors 70, illustrated as sensors S ₀ -S _X , sensing the state of the fluid release circuit 30, such as temperature sensors and crack sensors, for example. In one example, as will be described in more detail below, memory elements 29 and sensors 70 may be selectively connected to registration pad 50, such as via registration line 52, for access by, for example, printer 60. In one example, communicating with printer 60, such as measurements of cracks and temperatures in areas of the circuit 20 release of the fluid, and the information stored by the elements 29 memory (for example, thermal conditions, offsets, color map, number of nozzles, etc.), provides the ability to calculate and correct instructions for operation a fluid ejection circuit 20 (including fluid ejection) according to the detected conditions.

[0048] In one example, the fluid ejection circuit 20 includes a control circuit 80 for controlling the operation of an array 24 of fluid activators 26, an array of 28 memory elements 29, and sensors 70. In one example, the control circuit 80 includes an address decoder/driver 82 , an activation/selection logic 84, a configuration register 86, a memory configuration register 88, and a write circuit 89, wherein address decoder/driver 82 and activation/selection logic 84 are shared to control access to an array of 24 fluid activators 26 and an array of 28 elements 29 memory.

[0049] In one example, during a fluid activation event, control logic 80 receives a drive pulse group (FPG) data packet via data pad 44, such as from a printer 60. In one case, the FPG data packet has a head section including data configurations, such as address data, and a main section including activator selection data, wherein each bit of the selection data has a selection state (eg, "1" or "0"), and each bit of the selection data corresponds to a different one of the primitives P ₀ - P _M . The address decoder/driver 82 decodes and provides an address corresponding to the address data of the data packet, for example, via an address bus. In one example, in response to receiving a drive pulse via drive pad 46 (e.g., from printer 60), in each P ₀ -P _M primitive, activation logic 84 drives (activates) a fluid activator corresponding to the address provided by address decoder/driver 82, when the corresponding selection bit is set (eg, has the state "1").

[0050] Similarly, as in the examples, during a memory access operation, the control logic 80 receives a packet of drive pulse group (FPG) data through the data pad 44, for example, from the printer 60. However, instead of including the activator selection data, during memory access operations, the main portion of the FPG data packet includes memory selection data, where each bit of the selection data has a selection state (eg, "0" or "1") and corresponds to a different one of the primitives P ₀ -P _M . In one example, in response to receiving a drive pulse via drive pad 46 in each P ₀ -P _M primitive, activation logic 84 initiates the connection of memory element 29 corresponding to the address provided by address decoder/driver 82 to registration line 52 when the corresponding select bit is set. (for example, has a state of "1").

[0051] In the case where the memory access operation is a "read" operation, the analog response signal of the memory element 29 (or elements 29) connected to the registration line 52 to the analog registration signal (for example, a registration current signal or a registration voltage signal) filed on the line 52 registration, for example, the printer 60, through the pad 50 registration, indicates the state of the element 29 (or elements) of the memory. In the case where the memory access operation is a "write" operation, the memory elements 29 connected to the registration line 52 can be programmed into a predetermined state (for example, to "1" from "0") by an analog program signal applied on the line 52 registration, for example, by the printer 60, through the registration platform 50, or by the recording circuit 89 combined with the fluid ejection circuit 20.

[0052] During a read operation, a single memory element 29 may be connected to the registration line 52 and be read out, or a combination (or subset) of the memory elements 29 may be connected in parallel with the registration line 52 and read simultaneously based on the expected analog response signal to the analog registration signal. In the examples, each memory element 29 may have known electrical characteristics when in a programmed state (eg, set to "1") and an unprogrammed state (eg, set to "0"). For example, in one instance, memory elements 29 may be floating gate metal-oxide-semiconductor field-effect transistors (MOSFETs) having a relatively high resistance when not programmed and a relatively low resistance when programmed. Such electrical properties allow known responses to known registration signals intended to indicate the state of the memory element 29 (or elements) of the memory, during a read operation.

[0053] For example, if a fixed logging current is applied to the logging line 52, a voltage response can be measured that indicates the state of the memory for the selected memory element 29 or memory elements 29 . When more than one memory element 29 is connected in parallel with the registration line 52, each additional memory element reduces the resistance, which reduces the registration voltage response at the registration area 50 by a predictable amount. As such, information (eg, program state) can be determined with respect to the combination of selected memory elements 29 based on the measured recording voltage. In the examples, a current source internal to the fluid ejection circuit 20 may be used to apply the detection current. In other examples, a current source external to the fluid ejection circuit 20 (eg, printer 60 via registration pad 50) may be used.

[0054] Accordingly, if a fixed detection voltage is applied, the current response signal can be measured, which indicates the state of the memory for the selected memory element 29 (or memory elements 29). When more than one memory element 29 is connected in parallel with the registration line 52, each additional memory element reduces the resistance, which increases the registration current at the registration area 50 by a predictable amount. As such, information (eg, program status) can be determined with respect to the combination of selected memory elements 29 based on the measured logging current. In the examples, a voltage source internal to the fluid ejection circuit 20 may be used to apply the detection voltage. In other examples, a voltage source external to the fluid ejection circuit 20 (eg, printer 60 via registration pad 50) may be used.

[0055] In one instance, to allow the fluid ejection circuit 20 to identify a memory access operation so that information is not unintentionally written to the memory array 29 during other operations, such as a fluid activation operation, a unique memory access protocol is used that includes a particular sequence of operating signals received via I/O pads 40. In one example, the memory access protocol begins with data pad 44 rising (eg, rising to a relatively higher voltage). With data pad 44 still elevated, mode pad 48 rises (eg, mode signal at mode pad 48 rises). With the elevated data pad 44 and mode pad 48, the control logic 80 recognizes that the configuration register 86 must be accessed. A series of data bits is then shifted into configuration register 86 from data pad 44 with a clock signal at CLK pad 42 . In one example, configuration register 86 holds a series of bits, such as 11 bits, for example. In other examples, configuration register 86 may include more or less than 11 bits. In one example, one of the bits in control register 86 is a memory access bit.

[0056] The FPG data packet is then received via the data pad 44, with the select bits in the main portion of the data packet representing the select bits of the memory element 29 . In one example, the FPG data packet further includes a configuration bit (eg, in the head or tail of the data packet) that, when set, indicates that the FPG is a memory access FPG. When the control logic 80 recognizes that both the memory enable bit in the configuration register 86 and the memory access configuration data bit in the received FPG packet are "set", the control logic 80 enables the memory configuration register (MCR) 88 to receive data via pad 44 data in a manner similar to the manner in which the configuration register 86 received data bits (as described above). According to one example, upon recognizing that both the memory unlock bit in the configuration register 86 and the memory access configuration data bit in the received FPG data packet are "set", a series of data bits are shifted into the memory configuration register 88 from the data pad 44, which includes a column enable bit to allow (unlock) access to a column of 28 bits of memory, and a read/write enable bit indicating whether the memory access is a read or write access (for example, "0" indicates a memory read, and "1" indicates a memory entry). In one example, when the fluid ejection circuit 20 has a memory array 28 having more than one column of memory elements 29 such as columns 28 ₁ and 28 ₂ , the FPG data packet configuration data reporting the memory selection data includes column selection bits , identifying which column 28 data items are being accessed. The column enable bit of the memory configuration register 88 and the column select bit of the FPG data packet together allow the selected column 28 to be accessed for memory operation.

[0057] After data is loaded into the memory configuration register 88, the drive pulse at the drive pad 44 rises, and each memory element 29 corresponding to the address presented in the FPG header and having the corresponding memory select bit in the FPG main section that is set (for example, has value "1"), is connected to the registration bus 52 for read or write access as indicated by the state of the read/write bit of the memory configuration register.

[0058] In one example, the read operation for the crack sensor 70 of the fluid ejection circuit 30 has a protocol similar to the read operation protocol for the memory elements 29 . The data site 44 rises followed by an increase in the mode signal at the mode site 48 . A series of data bits is then shifted into the configuration register 86 . However, instead of the configuration data bit corresponding to the reading operation of the memory element 29 set in the configuration register 86, the configuration data bit corresponding to the reading operation of the crack sensor 70 is set. After the data has been shifted into the configuration register 86, the FPG is received by the control logic 80 when all data bits of the FPG main body have a non-selectable value (eg, a value of "0"). The excitation pulse signal at the excitation site 46 then rises and the crack sensor 70 is connected to the registration line 52 . The analog crack sensor 70 response to the analog sensing signal on sensing line 52 indicates whether crack sensor 70 detects a crack (e.g., the analog voltage sensing signal reduces the analog current response, and the analog current sensing signal creates an analog voltage response).

[0059] In one example, the read operation of the thermal sensor 70 is performed during a fluid ejection operation. In one case, the configuration data bit corresponding to a particular thermal sensor is specified in the head or tail section of the FPG data packet, while the main section of the FPG includes activator selection data bits, one for each primitive P ₀ -P _M , and has a state indicating which fluid activators 26 are to be activated. When the excitation pulse signal at the excitation pad 46 rises, the selected fluid activators 26 are excited and the selected thermal sensor (eg, a thermal diode) is connected to the detection line 52. An analog sensing signal applied to a selected thermal sensor via sensing line 52 results in an analog response signal on sensing line 52 indicative of the temperature of the thermal sensor.

[0060] In one example, when the memory array 28 of the fluid ejection circuit 20 may include corrupted memory elements 29 storing incorrect memory values, the memory circuit 30 may be connected in parallel with the fluid ejection circuit 20 to the I/O pins 40 with memory values 36 of the memory component 34 to serve as a substitute memory for the memory array 28 and store the correct memory values. In one example, the control circuit 32 monitors the operating signals received through the I/O pads 42. In one case, after recognizing a memory access sequence such as described above, the control circuit 32 checks the status of the read/write bit provided in the memory configuration register 88 via pad 44 data.

[0061] In one example, when the memory access is a "write" operation, the control circuit 32 checks the state of the memory select bits in the main FPG section received via data pad 44 to determine which memory elements 29 are indicated as being programmed (e.g., have the corresponding select bit set (eg, set to "1") The control circuit 32 then updates the respective memory values 36 of the memory component 34 to reflect any changes in the memory values 36 due to the write operation.

[0062] In one example, when the memory access is a "read" operation, the control circuit 32 checks the state of the memory select bits in the main FPG section provided via the data pad 44 to determine which memory elements 29 are indicated as being programmed. The control circuit 32 then checks the respective memory values 36 in the memory component 34 and determines the type of analog registration signal present at the registration pad 50 . In one example, in response to the detected analog logging signal, and based on read memory values, control circuit 32 generates an analog response signal on logging line 52 and logging pad 50 indicating values for memory values 36 .

[0063] For example, in the case where the analog logging current is applied on the logging line 52 through the logging pad 50, for example, by the printer 60, and a single memory value is read, the control circuit supplies an analog voltage response signal to the logging line 52, which indicates the value for the read single memory value. For example, if a single memory value is being read, the analog voltage response provided on recording line 52 by control circuit 32 may be a relatively high voltage for an unprogrammed memory value and may be a relatively low voltage for a programmed memory value. In one example, the control circuit 32 supplies on the registration line 52 an analog voltage response signal having a value equal to the expected response signal, taking into account the known characteristics of the memory elements 29, the number of memory elements 29 read in parallel, and the analog registration signal.

[0064] By monitoring operating signals at I/O pads 40 identifying a memory access operation (e.g., read/write operations) in order to maintain and update memory values 36, and provide expected analog response signals on registration line 52 in response to memory read operations, the memory circuit 30 is indistinguishable from the memory array 28 of the fluid ejection circuit 20 for the device accessing the printing component 10, such as the printer 60.

[0065] FIG. 4 is a block and circuit diagram illustrating the memory circuit 30 connected to the printing component 10, according to one example. In the example of FIG. 4, the printing component 10 includes a series _of fluid ejection circuits 20, illustrated as fluid ejection circuits ₂₀₀ , 201, ₂₀₂ , and ₂₀₃ , each including an array of fluid activators 24, illustrated as arrays ₂₄₀ , 24 ₁ , 24 ₂ , and 24 ₃ activators, and each includes a memory array 28 illustrated as memory arrays 28 ₀ , 28 ₁ , 28 ₂ , and 28 ₃ . In one example, each fluid ejection circuit 20 comprises a separate fluid ejection matrix, with each matrix outputting a different color ink. For example, fluid burst matrix 20 ₀ may be a matrix for cyan, fluid burst matrix 20 ₁ may be a matrix for magenta, fluid burst matrix 20 ₂ may be a matrix for yellow, and fluid burst matrix 20 ₃ may be matrix for black. In the example, the fluid ejection matrix 20 ₀ , 20 ₁ and 20 ₂ is made as part of the color printing pen 90, and the fluid ejection matrix 20 ₃ is made as part of the monochrome printing pen 92 .

[0066] In one example, each fluid release array 20 ₀ -20 ₃ receives data from a respective one of the data pads 44 ₀ -44 ₃ and each shares a CLK pad 42, a drive pad 46, a mode pad 48, and a registration pad 50. In the examples, each of the memory arrays 28 ₀ , 28 ₁ , 28 ₂ , and 28 ₃ can be individually accessed during a memory access operation. In other examples, any combination of memory arrays 28 ₀ , 28 ₁ , 28 ₂ , and 28 ₃ can be simultaneously accessed during a memory access operation. For example, the memory elements from each of the memory arrays 28 ₀ , 28 ₁ , 28 ₂ and 28 ₃ can be simultaneously accessed (for example, a read operation) through the registration line 52, for example, by the printer 60.

[0067] The memory circuit 30 is connected to the CLK pad 42, the drive pad 46, the mode pad 48, and the registration pad 50, and is connected to each of the data pads 44 ₀ -44 ₃ to be connected in parallel with each of the matrices 20 ₀ , 20 ₁ , 20 ₂ and 20 ₃ ejection of the fluid. In the examples, memory circuit 30 may serve as a substitute memory for any combination of memory arrays 28 ₀ , 28 ₁ , 28 ₂ , and 28 ₃ . For example, in one instance, memory circuit 30 may serve as a substitute memory for memory array 24 ₁ , while in another example, memory circuit 30 may serve as a substitute for each of memory arrays 28 ₀ , 28 ₁ , 28 ₂ , and 28 ₃ .

[0068] In one example, the memory circuit 30 may serve as additional memory for the fluid ejection circuit 20. In such a case, for memory access operations, the memory elements 29 of the fluid ejection circuit 20 and the memory values 36 of the memory circuit 30 can be separately identified by the column select bits in the configuration data of the FPG data packets reporting the memory select data. For example, the fluid ejection circuit 20 ₃ of the monochrome printing pen 92 may include a memory circuit 28 ₃ having a series of columns of memory elements 29, such as three columns. In such a case, the memory element columns of the fluid ejection circuit 20 ₃ can be identified by the FPG data packet configuration data column selection bits as columns 1-3, and additional memory value columns 36 of the memory component 34 acting as additional memory can be identified as additional columns starting at column 4.

[0069] In one example, similar to that described above with respect to FIG. 3, the memory circuit 30 monitors the operating signals _{on the} series of I/O pads 40, detecting the memory access sequence for any _of the memory arrays 280, ₂₈₁ , 282, and 283 for which the memory circuit 30 serves as a substitute memory.

[0070] In one example, when the memory circuit 30 serves as a substitute memory for less than all of the fluid ejection matrices 20 ₀ , 20 ₁ , 20 ₂ , and 20 ₃ of the printing component 10, the memory elements 29 of the fluid ejection matrices 20 for which the memory circuit 30 does not serve as a substitute memory, is not capable of reading in parallel with the memory elements of the fluid release matrices 20 for which the memory circuit serves as a substitute memory.

[0071] FIG. 5 is a block and circuit diagram generally illustrating the memory circuit 30 connected to the memory component 10 according to one example, where parts of the memory component 10 are also shown. As will be described in more detail below, according to the example of FIG. 5, the memory circuit 30 is connected in parallel with the fluid ejection device 20 to the registration pad 50 during memory access operations. In the example, as illustrated in FIG. 5, the memory circuit 30 can serve as a substitute memory for the array 28 of the memory elements 29 of the fluid ejection circuit 20 (when one or more of the memory elements 29 may be corrupted).

[0072] In one example, the activation logic 84 of the fluid ejection circuit 20 includes a read enable (unlock) switch 100, a column activation switch 102 controlled via an AND gate 103, and a memory element selection switch 104 controlled via an AND gate 106 According to one example, as described above, during a read operation, the fluid ejection circuit 20 receives a group of drive pulses including configuration data (for example, in the head and/or tail section) and memory selection data (for example, in the main section ). In one example, the configuration data includes a column select bit and address data. The column select bit indicates the particular column of memory elements 29 that are accessed when the memory array 28 includes more than one column of memory elements, such as columns 28 ₁ and 28 ₂ in FIG. 3. The address data is decoded by the address decoder 82 and provided to the activation circuit 84 . In one example, the selection data includes a series of memory selection bits, when each memory selection bit corresponds to a different primitive (P ₀ -P _M ) of a column of memory elements 29, when the selection column that is specified (eg, has a value of "1") provides the ability to access the elements 29 of the memory column 28 for reading (or writing).

[0073] Additionally, as part of the read operation protocol, the memory configuration register 88 is loaded with a column enable bit and a read enable bit. The read enable bit of the memory configuration register 88 turns on the read enable switch 100 . When the drive signal rises, the read enable bit of the configuration register 88 together with the column select bit of the drive pulse group configuration data cause the AND gate 1083 to turn on the column enable switch 102 for the selected column, and the selection data and address (via the address decoder 86) of the drive pulse group and the drive signal together cause the AND gate 106 to turn on the memory element selection switch 104, thereby connecting the memory element 29 to the registration line 52 . Note that in some examples, the column select bit may not be part of the drive pulse group configuration data when the fluid ejection circuit 20 includes a single column of memory elements.

[0074] After connecting to the registration line 52, the memory element 29 provides an analog output signal in response to the analog registration signal on the registration line 52, when the value of the analog output signal depends on the program state of the memory element (when such a program state may be corrupted). In one example, as described above, memory element 29 may have a relatively higher electrical resistance when it is in an unprogrammed state (eg, a value of "0") than when it is in a programmed state (eg, a value of "1"). Accordingly, when the analog registration signal is a fixed analog current (so-called "forced current mode"), the analog output voltage outputted by the memory element 29 will have a relatively higher voltage level when the memory element 29 is in an unprogrammed state, and a relatively lower level current when the memory element 29 has a programmed state. Similarly, when the analog recording signal is a fixed voltage (so-called "forced voltage mode"), the analog output current provided by the memory element 29 will have a relatively lower current level when the memory element 29 is in an unprogrammed state, and a relatively higher level current when the memory element 29 has a programmed state.

[0075] Note that during the write operation, the read release switch 100 is maintained in the open position, disconnecting the memory element 29 from the registration line 52, while the column release switch 102 and the memory element selection switch 104 are closed. The write enable bit of the memory configuration register connects the voltage regulator 90 to the memory element 29 to apply a program voltage thereto.

[0076] The control circuit 32 of the memory circuit 30, according to one example, includes control logic 120, a first voltage controlled current source 122 operating as a current source for node 128, and a second voltage controlled current source operating as a current sink from the node. 128, wherein the node 128 is connected to the registration line 52 at the second registration site 50 ₁ via the control line 129. In the example of FIG. 4, during a memory access operation, the memory circuit 20 is connected to the registration line 152 in parallel with the fluid ejection circuit 20 in the second registration platform 50 ₁ .

[0077] In one example, the memory circuit 30 is connected in parallel with the fluid ejection circuit 20 to the I/O pads 40 via a wired overlay 160, which is described in more detail below (eg, see FIG. 6A). In one example, the wired substrate 160 includes a pair of I/O pads for each signal path, with the signal path being routed through the wired substrate overlay 160 to the print component 10 from the first I/O pad of the pair to the second I/O pad of the couples. For example, the wired substrate 160 includes a pair of CLK pads 42 and 42 ₁ , a pair of data pads 44 and 44 ₁ , a pair of drive pads 46 and 46 ₁ , a pair of mode pads 48 and 48 ₁ , and a pair of registration pads 50 and 50 ₁ . In one example, in each case, the first pad of the pad pair connects to the incoming signal line, and the second pad of the pad pair connects the outgoing signal line to the print component 10.

[0078] In one example, the wired overlay substrate 160 further includes a registration resistor 150 connected in series with the registration line 52 when the control logic 120 controls the voltage at the high and low side terminals 152 and 154 of the registration resistor 150. In other examples, the registration resistor 150 may be provided as part of the control circuit 32 (eg, see FIG. 10).

[0079] Although illustrated as being connected to the signal paths and the printing component 10 via the wired substrate 160, any number of other implementations may be applied to provide such a connection. For example, in one example, the functionality of the wired substrate 160 may be integrated into the memory circuit 30.

[0080] The memory component 34 includes a series of memory values 36 . In one example, each memory value 36 corresponds to a different one of the memory elements 29 of the fluid ejection circuit 20 . However, while one or more of the memory elements 29 of the fluid ejection circuit 20 may be corrupted and store incorrect values, each of the memory values 36 of the memory component 34 represents a valid memory value. Note that in the examples, the memory component 34 may include, in addition to the memory values 36, the memory values 36 corresponding to the memory elements 29 .

[0081] In one example, the control circuit 32 controls the operating signals provided to the fluid ejection circuit 20 at the I/O pads 40, for example, from the printer 60. In one example, upon detecting operating signals representing a memory access sequence indicating an element read operation 29 memory, the control logic 120 monitors the voltage at the high-side terminal 152 (or low-side terminal 154) of the registration resistor 150, determining whether the read operation is performed in the forced current mode or the forced voltage mode. If the forced current mode is applied, the voltage level at the high side terminal 152 will rise (eg, ramp up) during the period of time following the rise of the drive pad 46 when the registration line 52 is being charged. If the forced voltage mode is applied, the voltage at the high side pin 152 will remain relatively stable at a fixed voltage level of the registration input signal.

[0082] In one example, upon detecting a read operation, control logic 120 reads a memory value 36 corresponding to the memory element 29 identified as being accessed by the read operation. Based on the memory value 36, the control logic 120 is able to determine an expected voltage response output level to be present at the registration pad 50 during a forced current read operation, and an expected current output response level to be present at the registration pad 50 during read operations in forced voltage mode, through a feedback loop formed with the registration resistor 150 .

[0083] Since the memory circuit 30 is connected in parallel with the fluid ejection circuit 20 to the registration line 52, during the read operation, in response to the analog registration signal forced on the registration line 52, in the second pad 50_one registration there is an analog output response signal (eg voltage or current) from the memory element 29 . In one example, control logic 120 regulates voltage controlled current sources 122 and 124 to supply current to second pad 50_one registration or taking current from the second platform 50_oneregistration so that the combination of the output response signal from the memory element 29 of the fluid ejection circuit 20 and the output response signal of the control circuit 32 at the second registration area 50 produces the expected level of the analog output response signal (voltage or current) at the registration area 50.

[0084] In one example, when in forced current mode, control logic 120 monitors the voltage at high side terminal 152 of recording resistor 150 and adjusts voltage controlled current sources 122 and 124 to control the amount of current supplied to second recording pad 50 ₁ (either supplies current to the second recording pad 50 ₁ or draws current from the second recording pad 50 ₁ ) so that the combined response of the memory circuit 30 and the fluid ejection circuit 20 provides the expected voltage response output level at the recording pad 50.

[0085] Similarly, in one example, while in the forced voltage mode, the control logic monitors the voltage across the sensor resistor 150 via the high side and low side terminals 152 and 154, determining the current response output level at the recording pad 50. The control circuit 120 then regulates the voltage controlled current sources 122 and 124 to control the amount of current supplied to the second registration pad 50 ₁ (either supplies current to the second registration pad 50 ₁ or draws current from the second registration pad 50 ₁ ) so that the combined response the signal of the memory circuit 30 and the fluid ejection circuit 20 provides the expected level of the output current response signal at the recording site 50 .

[0086] By adjusting the voltage controlled current sources 122 and 124 to provide the expected value of the analog output response signal at the recording pad 50 based on the correct memory values for the fluid ejection circuit 20 that are stored as memory values 36 by the memory component 34, circuit 30 memory array is able to replace the damaged memory array 28 in the fluid ejection circuit 20 so that the printing component 10 is able to remain operational, thereby reducing the number of damaged printing components during manufacture. Additionally, by connecting the memory circuit 30 in parallel with the fluid ejection circuit to the I/O pads 40, the sensors 70 of the fluid ejection circuit 20 remain available at all times for monitoring through the registration pad 50, for example, by the printer 60.

[0087] FIG. 6A is a sectional view illustrating portions of overlay substrate 160 with wiring for connecting memory circuit 20 to I/O pins 40. In particular, FIG. 6A is a sectional view through the registration area 50 of FIG. 5 when the memory circuit 30 is connected in parallel with the fluid ejection circuit 20 to the registration platform 50 . In one example, the routed overlay substrate 160 includes a flexible substrate 162 having a first surface 163 and an opposing second surface 164. 50 registration with circuit 30 memory. In one example, as illustrated, registration resistor 150 is placed in series with registration line 52 between registration pad 50 and memory circuit 30. In one example, conductive through wiring 166 extends from registration line 52 on first surface 163 through flexible substrate 163 to second registration pad 50 ₁ on second surface 164.

[0088] The printing component 10 includes a substrate 168 on which the fluid ejection circuit 20 is mounted, and includes a registration pad 50 ₂ connected to the fluid ejection circuit 20 by a registration line 52 ₁ . When the wired flexible substrate 160 is connected to the printing component 10 as indicated by the directed arrow 169, the second registration pad 50 ₁ aligns with the registration pad 50 ₂ connecting the registration line 52 to the registration pad 50 ₂ between the registration resistor 150 and the memory circuit 30.

[0089] FIG. 6B is a block diagram generally illustrating a sectional view of overlay substrate 160 with wiring showing connections of I/O pads 40 other than registration pad 50, such as mode pad 48, for example. As illustrated, mode pad 48 is located on upper surface 163 of substrate 162. Through-wire 167 extends through substrate 162, connecting first mode pad 48 to second mode pad 48 ₁ on second surface 164. When routed flexible substrate 160 is connected to print component 10, the mode pad 48 ₁ is aligned with the mode pad 48 ₂ to connect the mode pad 48 to the fluid ejection circuit 20 .

[0090] FIG. 7 is a block and circuit diagram generally illustrating the memory circuit 10 according to one example. Parts of the printing component 10 are also generally illustrated. The example of FIG. 7 is similar to the example of FIG. 5 when the memory circuit 30 is connected in parallel with the fluid ejection device 20 to the registration platform 50 during memory access operations. However, in the example of FIG. 7, the control circuit 32 of the memory circuit 30 includes an operational amplifier 170 and a regulated voltage source 172 instead of voltage controlled current sources 122 and 124.

[0091] The first input of the operational amplifier 170 is connected to a reference potential (eg, ground) through a regulated voltage source 172. The second input and output of the operational amplifier 170 is connected to the node 128, while the node 128 is connected to the registration pad 50 ₁ through the line 129.

[0092] In one example, during a memory read operation, while in the forced current mode, the control logic 120 monitors the voltage at the high side terminal 152 of the registration resistor 150 and adjusts the output voltage of the operational amplifier 170 by adjusting the voltage level of the regulated voltage source 172 (when the output voltage approximately corresponds to the voltage of the regulated voltage source 172) to control the amount of current supplied to the second recording pad 50 ₁ (either supplies current to the second recording pad 50 ₁ or draws current from the second recording pad 50 ₁ ), so that the combined response signal of the memory circuit 30 and the fluid ejection circuit 20 provides the expected voltage response output level at the registration pad 50 .

[0093] Similarly, in one example, when in the forced voltage mode, the control logic monitors the voltage across the sensor resistor 150 via the high side and low side terminals 152 and 154, determining the current response output level at the recording pad 50. The control circuit 120 then regulates the output voltage of the operational amplifier 170 by adjusting the voltage level of the regulated voltage source 172 (when the output voltage approximately matches the voltage of the regulated voltage source 172) to regulate the amount of current supplied to the second registration pad 50 ₁ (or supplies current to the second pad 50 ₁ registration or draws current from the second registration pad 50 ₁ ) so that the combined response of the memory circuit 30 and the fluid ejection circuit 20 provides the expected level of output current response signal at the registration platform 50 .

[0094] FIG. 8 is a block and circuit diagram of a memory circuit 30 for a printing component 10 according to one example. The example of FIG. 8 is similar to the example of FIG. 5 when the memory circuit 30 is connected in parallel with the fluid ejection device 20 to the registration platform 50 during memory access operations. However, in the example of FIG. 8, the control circuit 32 of the memory circuit 30 includes a series of resistors 180-183 that can be connected to form an adjustable voltage divider between the voltage source VCC and a reference voltage (eg, ground) instead of voltage controlled current sources 122 and 124.

[0095] In an example, a source resistor 180 is connected between a voltage source VCC and node 128. Current collector resistors 181-183 are connected in parallel with each other between node 128 and a reference voltage (eg, ground) via respective switches 184-186. Note that the control circuit 32 may use a different number of resistors than the number illustrated in FIG. eight.

[0096] In one example, during a memory read operation, while in forced current mode, control logic 120 monitors the voltage at high side terminal 152 of registration resistor 150 and adjusts the number of current collector resistors 181-183 that are connected between node 128 and ground by controlling switches 184-186 to adjust the amount of current supplied to the second recording pad 50 ₁ such that the combined response of the memory circuit 30 and the fluid ejection circuit 20 provides the expected voltage response output level at the recording pad 50.

[0097] Similarly, in one example, while in the forced voltage mode, the control logic monitors the voltage across the sensor resistor 150 via the high side and low side terminals 152 and 154, determining the current response output level at the recording pad 50. The control circuit 120 then controls the number of current collector resistors 181-183 that are connected between node 128 and ground by operating switches 184-186 to control the amount of current supplied to the second registration pad 50 ₁ (either supplies current to the second registration pad 50 ₁ or draws current from the second recording pad 50 ₁ ) so that the combined response of the memory circuit 30 and the fluid ejection circuit 20 provides the expected current response output level at the recording pad 50 .

[0098] FIG. 9 is a block and circuit diagram generally illustrating the memory circuit 30 according to one example. The memory circuit 30 includes a plurality of I/O pads 40, including an analog signal pad 50, connected to a plurality of signal paths 41 that provide operating signals to the printing component 10. In one example, a controllable selector 190 is connected in series with one from the signal paths 41 through the I/O pads 40, while the controlled selector 190 is controlled to open the corresponding signal line with the printing component 10 (interrupt or break the connection with the printing component 10). In one example, in response to a sequence of operating signals received by the I/O pads 40 representing a memory read, the control circuit 32 opens the controllable selector 190, interrupting the signal path to the printing component 10, blocking the memory read of the memory component 10, and applies an analog signal to the pad. 50 for an analog signal, providing in the analog pad 50 an analog electrical signal value representing the stored memory values 36 selected by reading the memory. By interrupting the signal path during a memory read, the printing component 10 is unable to supply an analog signal to the analog signal pad 50 during memory read operations. In the examples, printing component 10 is allowed to provide an analog signal to pad 50 during non-memory read functions that access pad 50 for an analog signal, such as analog component reading. In examples, such an analog component may be a sensing circuit (eg, a thermal sensor).

[0099] FIG. 10 is a block and circuit diagram illustrating a memory circuit 30 according to one example of the present disclosure when the controlled selector 190 is a controlled switch 190. In the example of FIG. 10, the I/O pads 40 include a first analog pad 50 and _a second analog pad 501 connected to an analog line 52 when a controllable switch 90 is connected between _the analog pads 50 and 501 with a single connection. row with line 52 for analog signals. In one example, as illustrated, control circuit 32 further includes a second controllable switch 192 coupled to first analog signal pad 50. The example of FIG. 10 is similar to the example of FIG. 5, except that the controlled selector switches 190 and 192 allow the control circuit 32 to selectively connect to and disconnect the memory circuit 30 and the fluid ejection circuit 20 from the selection line 52 such that, in one example, the memory circuit 30 is not connected in parallel with by the fluid ejection circuit 20 during a memory access operation. Additionally, according to one example, the registration resistor 150 along with the high side and low side terminals 152 and 154 are placed in the memory circuit 32.

[00100] In one example, when the control logic 120 identifies a non-memory access operation, the control logic opens the controllable selector switch 190, disconnecting the voltage-controlled current sources 122 and 124 from the registration line 52, and closes the selector switch 192, connecting the fluid ejection circuit 20 environment with a line 52 registration to enable control of the sensors 70 (see Fig. 3), for example, using the printer 60, without the potential for interference in the output signals of the sensors 70 due to the control circuit 32.

[00101] In one example, when control logic 120 identifies a memory access operation, control logic may close selector switch 192, connecting node 128 and voltage controlled current sources 122 and 124 to registration line 52, and open selector switch 190, disconnecting circuit 20 ejection of fluid from the detection line 52 so that the ejection circuit 20 is no longer connected in parallel with the control circuit 32 to the second registration pad 50 ₁ so that the ejection circuit 20 is blocked from responding to the memory read operation. The control circuit 32 may then regulate the voltage controlled current sources 122 and 124 to provide the expected analog voltage response at the recording pad 50 as described above with respect to FIG. 5, but without the contribution of the analog output response from the fluid ejection circuit 20. By disconnecting the fluid ejection circuit 20 from the recording line 52 during memory access operations, potential contamination from corrupted memory elements 29 in the analog output response at the recording pad 50 can be eliminated.

[00102] In other examples, the controllable selector switch 190 may be connected in a similar manner to be in line with the drive signal path through the drive pad so that the drive signal is blocked from the fluid ejection circuit 20 during a memory read operation so that the ejection circuit 20 the fluid medium is not capable of responding to such a memory read operation. In another example, the controllable selector 190 may be a multiplexer connected in series with the registration line 52 (or path 52 for an analog signal), when the control circuit 32 operates, the multiplexer operates to disconnect the registration line 52 from the fluid ejection circuit 20 during memory reading. , and otherwise operates by connecting the registration line 52 to the fluid ejection circuit 20, for example, during non-memory read operations that access the analog signal registration pad 50 and the registration line 52.

[00103] Note that the configurations of the control circuit 32 described in FIG. 6 and 7, and any number of other suitable control configurations, may be used in the exemplary printing component 10 of FIG. ten.

[00104] FIG. 11 is a sectional view illustrating portions of an overlay substrate 160 with wiring for connecting the memory circuit 30 to the I/O pins 40 as illustrated in FIG. 10 according to one example. In particular, FIG. 11 is a sectional view through the registration area 50. In one example, the memory circuit 30 and the registration pad 50 are placed on the first surface 163 of the flexible substrate 162, with the conductive path representing the registration line 52 connecting the registration pad 50 to the memory circuit 30. According to one example, the registration resistor 150 and the selector switches 190 and 192 are placed internal to the memory circuit 30. The conductive through wiring 167 passes through the flexible substrate 162, with the memory circuit 30 electrically connected to the registration pad 50 ₂ on the second surface 164 of the flexible substrate 162 by conductive tracks 52 ₂ and 52 ₃ (representing portions of the registration line 52) via the through wiring 167. When flexible the wired substrate 160 is connected to the printing component 10 as indicated by arrow 169, the registration pad 50 ₂ is aligned with the registration pad 50 ₁ so that the registration pad 50 is connected to the fluid ejection circuit 20 through the selector switch 192 in the memory circuit 30.

[00105] FIG. 12 is a block and circuit diagram generally illustrating the memory circuit 30 according to one example. The memory circuit 30 includes a plurality of I/O pads 40 including first and second analog signal pads 1 and 2, referred to as 50 and 50 ₁ , connecting a plurality of signal paths 41 to the printing component 10, including a path 52 for analog signals connected to pads 50 and 50 ₁ for analog signal. In one example, the first analog signal pad 50 is electrically isolated from the second analog signal pad 50 ₁ , interrupting the analog signal path to the printing component 10. provides an analog signal to the first analog signal pad 50 by providing an analog electrical signal value to the first analog signal pad 50 representing the stored memory values 36 selected by reading the memory.

[00106] By interrupting the analog signal path 52 during memory reads, the printing component 10 is disconnected from the analog signal path 52 during memory read operations. As will be described in more detail below, in addition to providing memory values 36 corresponding to the memory elements of the printing component 10, the memory values 36 may represent values for other functions that access the printing component 10 via the analog signal path 52, such as read commands. sensor (e.g. for reading thermal sensors).

[00107] FIG. 13 is a block and circuit diagram of a memory circuit 30 according to one example, and generally illustrates parts of the printing component 10. The example of FIG. 13 is similar to the example of FIG. 10, but instead of including a selector switch (eg, selector switch 192) selectively controlling the connection of the fluid ejection circuit 30 to the registration line 52, the fluid ejection circuit 30 is physically disconnected from the registration line 52. In one example, with reference to FIG. 14 below, a wired patch substrate 160 is placed to connect the memory circuit 30 to the selection line 52 and to connect the memory circuit 30 to the I/O pads 42-48 in parallel with the fluid ejection circuit 20 when the fluid ejection circuit 20 is disconnected from the registration pad 50.

[00108] In one example, when identifying a memory access operation of the fluid ejection circuit 20 at the I/O pads 40, the control logic operates as described in FIG. 4 and 8 above, updating the memory values 36 with the writes and providing the expected analog output responses to the registration pad 50 with the reads.

[00109] However, as previously described, the registration area 50 via the registration line 52 is also used to read sensors 70 (see FIG. 3), such as, for example, thermal sensors and crack sensors. Such sensors are read in a manner similar to the memory elements 29 of the fluid ejection circuit 20 when an analog recording signal is applied to the sensor and the analog response signal indicates the recorded (read) temperature in the case of a temperature (thermal) sensor and indicates the presence or absence of a crack in the case of crack sensor. In one example, in the case of a temperature sensor, an analog output signal representing a sensed temperature within the intended operating temperature range indicates correct operation of the fluid ejection circuit 20, while a sensed temperature outside the intended operating temperature range may indicate incorrect operation of the ejection circuit 20. fluid (for example, overheating). Similarly, in the case of a crack sensor, an analog signal representing a detected resistance below the intended threshold value may indicate the absence of a crack in the fluid ejection circuit 20, while a recorded resistance above the intended threshold value may indicate the presence of a crack in the fluid ejection circuit 20. environment.

[00110] In view of the foregoing, in one example, in addition to the memory component 34 including memory values 36 corresponding to the memory elements 29 of the fluid ejection circuit 20, the memory component 34 includes a memory value 36 corresponding to each of the sensors 70 of the circuit 20 fluid ejection. In one example, memory value 36 represents the analog output value supplied by control circuit 32 to registration pad 50 in response to a sensor 70 read operation corresponding to memory value 36 recognized at I/O pads 40 by memory circuit 30. In one example, the control logic 120 controls the voltage controlled current sources 122 and 124 by providing an analog output signal to the registration pad 50 as indicated by the corresponding memory value 36 .

[00111] In view of the foregoing, as described above, by registering pad 50 physically disconnected from fluid discharge circuit 20, memory circuit 30 simulates analog output response signals for memory elements 29 and sensors 70 of fluid discharge circuit 20 based on values 36 memory stored by the memory component 34 . According to one example, the memory circuit 30 of FIG. 13 can be installed on the printing component 10 via a flexible wired substrate 160 to replace damaged memory elements 26 and damaged sensors 70 to maintain the operation of the printing component 10.

[00112] In one example, the memory circuit 30 of FIG. 13 may be temporarily mounted to the printing component 10 via the flexible wired substrate 160 and serve as a diagnostic circuit for testing the response of an external circuit, such as the printer 60, to simulated conditions in the fluid ejection circuit 20. For example, memory values 36 corresponding to sensors 70 containing temperature sensors may have values corresponding to temperature values outside a desired operating temperature range to test the printer 60's response to such conditions. In other examples, memory values corresponding to sensors 70 containing crack sensors may have values corresponding to a resistance value above a threshold value indicative of the presence of a crack in order to test printer 60's response to such conditions. Any number of other conditions may be simulated by the memory circuit 30, thereby allowing the printer 60 to test the response to simulated operating conditions without access to the fluid ejection circuit 20 via the registration line 52. In one example, after the diagnostics have been completed, the memory circuitry 30 and flexible wiring circuitry 160 can be removed from the printing component 10.

[00113] FIG. 14 is a sectional view illustrating portions of the overlay substrate 160 with wiring for connecting the memory circuit 30 to the I/O pins 40 illustrated in FIG. 13 according to one example. In particular, FIG. 14 is a sectional view through the registration area 50. In one example, the memory circuit 30 and the registration pad 50 are placed on the first surface 163 of the flexible substrate 162, with the conductive path representing the registration line 52 connecting the registration pad 50 to the memory circuit 30. The second registration area 50 ₁ is located on the second surface 164 of the substrate 162 and is electrically isolated from the registration area 50, the registration line 52 and the memory circuit 30. The registration pad 50 ₂ is placed on the substrate 168 of the printing component and is connected by a conductive path 52 ₁ to the fluid ejection circuit 20 . When the routed flexible substrate 160 is placed on the printing component 10 (as indicated by the directed arrow 169), the registration area 50 ₁ is aligned and in contact with the registration area 50 ₂ . Because the registration area 50 ₁ is electrically isolated from the registration area 50, no electrical contact is made between the registration area 50 and the underlying area 50 ₁ so that the connection between the fluid ejection circuit 20 and the registration area 50 is interrupted.

[00114] FIG. 15 is a block diagram illustrating one example of a fluid ejection system 200. The fluid ejection system 200 includes a fluid ejection assembly such as a printhead assembly 204 and a fluid supply assembly such as an ink supply assembly 216 . In the illustrated example, the fluid ejection system 200 also includes a service station assembly 208, a cartridge assembly 222, a print media transport assembly 226, and an electronic controller 230. While the following description provides examples of systems and assemblies for handling fluid regarding ink, the disclosed systems and assemblies are also applicable to the processing of fluids other than inks.

[00115] The print head assembly 204 includes at least one print head 212 that ejects drops of ink or fluid through a plurality of orifices (nozzles) or nozzles 214, when the print head 212 can be implemented, in one example, as circuit 20 ejection fluid with fluid activators (FA) 26 implemented as nozzles 214, as previously described here, for example, in FIG. 3. In one example, drops are directed onto a carrier, such as print media 232, so as to be printed on print media 232. In one example, print media 232 includes any type of suitable sheet material such as paper, card stock, transparencies, mylar, fabric, and the like. In another example, print media 232 includes three-dimensional (3D) printable media, such as a powder bed, or bioprinting and/or drug research testing media, such as a vessel or reservoir. In one example, nozzles 214 are arranged in at least one column or array such that properly ordered ejection of ink from nozzles 214 causes characters, symbols, and/or other graphics or images to be printed on print media 232 when print head assembly 204 and media 232 prints move relative to each other.

[00116] The ink supply unit 216 supplies ink to the print head unit 204 and includes an ink storage vessel 218. As such, in one example, ink flows from receptacle 218 to printhead assembly 204. In one example, print head assembly 204 and ink supply assembly 216 are housed together in an inkjet or liquid inkjet print cartridge or pen. In another example, the ink supply assembly 216 is separate from the printhead assembly 204 and supplies ink to the printhead assembly 204 via a mating connection 220, such as a supply tube and/or valve.

[00117] The carriage assembly 222 positions the print head assembly 204 relative to the print media transport assembly 226, and the print media transport assembly 226 positions the print media 232 relative to the print head assembly 204. Thus, the area 234 print is limited next to the nozzles 214 in the area between the node 204 print head and carriers 232 print. In one example, the print head assembly 204 is a scan type print head assembly such that the carriage assembly 222 moves the print head assembly 204 relative to the print media transport assembly 226 . In another example, the print head assembly 204 is a non-scan type print head assembly such that the carriage assembly 222 locks the print head assembly 204 in a prescribed position relative to the print media transport assembly 226 .

[00118] The service station assembly 208 provides pressure flushing (purge), wiping, plugging, and/or refilling of the printhead assembly 204 to maintain the functionality of the printhead assembly 204 and, in particular, the nozzles 214. For example, the service station assembly 208 may include a rubber knife or cleaning scraper that periodically passes over the printhead assembly 204, wiping and clearing excess ink from the nozzles 214. In addition, the service station assembly 208 may include a cap that covers the print head assembly 204, protecting the nozzles 214 from drying out during periods of inactivity. In addition, the service station assembly 208 may include an ink collection container into which the printhead assembly 204 ejects ink during pressure washes, ensuring that the vessel 218 maintains an appropriate level of pressure and fluidity, and ensuring that the nozzles 214 not clogged or leaking. The functionality of the service station node 208 may include relative movement between the service station node 208 and the printhead node 204 .

[00119] Electronic controller 230 communicates with printhead assembly 204 over communication channel 206, service station assembly 208 over communication channel 210, carriage assembly 222 over communication channel 224, and print media transport assembly 226 over communication channel 228. In one example, when the printhead assembly 204 is installed in the carriage assembly 222, the electronic controller 230 and the printhead assembly 204 may communicate through the carriage assembly 222 over the communication channel 202 . The electronic controller 230 may also communicate with the ink supply unit 216 so that, in one implementation, a new (or used) ink source may be detected.

[00120] Electronic controller 230 receives data 236 from a host system, such as a computer, and may include temporary data storage 236. Data 236 may be sent to fluid release system 200 via electronic, infrared, optical or other communication channel. Data 236 represents, for example, a document and/or file to be printed. As such, data 236 forms a print job for fluid ejection system 200 and includes at least one command and/or print job command parameter.

[00121] In one example, the electronic controller 230 provides control of the printhead assembly 204, including controlling the timing of ejection of ink droplets from the nozzles 214. As such, the electronic controller 230 specifies a pattern of ejected ink droplets that forms characters, characters, and/or other graphics or images on print media 232. The timing control, and thus the pattern of ejected ink drops, is determined by the commands and/or parameters of the print job commands. In one example, the logic and drive circuitry forming part of the electronic controller 230 is located on the printhead assembly 204. In another example, the logic and drive circuitry forming part of the electronic controller 230 is located outside the printhead assembly 204. In another example, the logic and drive circuitry forming part of the electronic controller 230 is located outside the printhead assembly 204. In one example, the electronic controller 230 may provide operating signals through the I/O pads 40 to the printing component 10, such as that illustrated in FIG. one.

[00122] While specific examples have been illustrated and described herein, the specific examples shown and described may be replaced by a variety of alternative and/or equivalent implementations without departing from the scope of this disclosure. This application is intended to cover any adaptations or variations of the specific examples discussed here. Therefore, this disclosure is intended to be limited only by the claims and their equivalents.

Claims (17)

1. Printing component containing: a series of input/output (I/O) pads including an analog signal pad for communicating operating signals for controlling operation of a printing component; a fluid ejection circuit connected to the I/O pads and including an array of fluid activators; and a memory circuit connected to the I/O pads, including: a memory component for storing memory values associated with the printing component; and a control circuit for supplying to the analog signal pad, in response to a sequence of operation signals reported by the I/O pads representing a memory read, an analog signal representing stored memory values corresponding to a memory read, wherein the fluid ejection circuit and the memory circuit are separate chips. 2. The printing component of claim 1, wherein, in response to a sequence of operating signals communicated by the I/O pads representing a memory write, the control circuit is configured to update the stored memory values identified by the memory write. 3. A printing component according to claim 1 or 2, wherein in response to a sequence of operating signals on the I/O pads representing non-memory read functions that access the analog signal pad, the control circuit is configured to supply an analog signal to the analog pad. signal with providing on site for the analog signal the value of the analog electrical signal representing the stored values of the memory corresponding to the functions of reading not the memory. 4. Printing component according to any one of paragraphs. 1-3, wherein the analog signal area is the analog signal detection area. 5. Printing component according to any one of paragraphs. 1-4, wherein the analog signal pad is connected to the analog signal detection circuit. 6. Printing component according to any one of paragraphs. 1-5, wherein the fluid ejection circuitry includes an array of memory elements, wherein the memory values of the memory circuit are intended to complement the array of memory elements. 7. Printing component according to any one of paragraphs. 1-6, wherein the memory component comprises an array of memory cells storing memory values. 8. Printing component according to any one of paragraphs. 1-7, wherein the memory component contains a lookup table of memory values. 9. Printing component according to any one of paragraphs. 1-8 with the memory circuit connected to the I/O pads in parallel with the fluid ejection circuit. 10. Printing component according to any one of paragraphs. 1-9, wherein the print component includes a print head. 11. Printing component according to any one of paragraphs. 1-10, wherein the print component includes an integrated print head.

Images