RU2777553C1 - Memory cell of a static primary memory apparatus with a radioactive power source - Google Patents

Abstract

FIELD: nanotechnology.

SUBSTANCE: invention relates to nanoelectronics and is used to create a non-volatile random access memory apparatus. The technical result is achieved by the electrical circuit of a 4-transistor memory cell of a static primary memory apparatus with a radioactive power source containing a common bus, a power bus, an address bus, a first and a second bit lines, a first and a second control n(p)-channel MOS-transistors, a first and a second switching n(p)-channel MOS-transistors, and using the radioactive emission source built into the RAM matrix as a generator of photocurrents in the load diodes of the trigger cell.

EFFECT: reduction in the power consumption and increase in the degree of integration.

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Description

The invention relates to nanoelectronics and can be used to create a non-volatile static random access memory device (ES RAM PV) with increased integration, manufacturability and lack of power consumption in the information storage mode.

Known electrical circuit of the memory cell of a dynamic random access memory device with random access information ( DOZU PV ) [US 3387286, published. 06/04/1968], containing an n-MOS (Metal-Oxide-Semiconductor) transistor, a common bus, a power bus, an address bus and two bit buses. The cell design is an n-MOS and a capacitor located on the front surface of a silicon wafer.

The disadvantage of the DOZU cell is its low speed and decrease in the reliability of operation with a decrease in its topological dimensions.

A known electrical circuit of a 6-transistor memory cell for a K-MOS S.RAM PV [RF Patent No. 2216795 dated 11/20/2003], containing two switching n-MOS and two load p-MOS transistors forming a trigger and two n-MOS control transistors providing write modes - reading and storing information, as well as a common bus, a power bus, an address bus and two bit buses.

The cell design consists of four n-MOS and two p-MOS transistors located on the front surface of a silicon wafer.

The disadvantage is the complex manufacturing technology and relatively large dimensions, which does not allow maximum integration of the RAM RAM.

The closest in technical essence is the memory cell n-MOS RAM PV [US 4901284 publ. 02/13/1990], containing two switching n-MOS transistors and two load resistors that form a trigger, while their sources are connected to a common bus, drains through load resistors to the power bus and, accordingly, to each other's gates, two n-MOS control transistors, gates which are connected to the address bus, the sources to the corresponding switching drains, and the drains to the corresponding bit buses.

Cell design, which consists of four n-MOS transistors located on the front surface of a silicon wafer, on the surface of the transistors there is a dielectric, on which load resistors are located [US 4901284 publ. February 13, 1990].

The disadvantages are significant energy consumption in the mode of storage, reading and writing information, a relatively large area occupied by high-resistance polysilicon resistors, poor reproducibility of resistors with a decrease in their topological dimensions, which also limits the possibility of increasing the integration of VLSI RAM.

A common disadvantage of these cells is the loss of information when the power is turned off.

The purpose of the invention is creation of a non-volatile RAM PV with increased integration and manufacturability.

The technical result achieved in the invention is to reduce energy consumption and increase the degree of integration.

The specified technical result is achieved as follows. In the electrical circuit the drains of the switching n(p)-MOS transistors are connected to the anodes of the corresponding (cathodes) load photodiodes, the cathodes (anodes) of which are connected to the power bus, while the photodiodes are sources of photo-emf, the positive potentials of which are on the anodes, and negative on the cathodes of photodiodes. The cathodes (anodes) of the photodiodes are connected to a common bus.

And also the goal is achieved by the fact that, in the design of the cell, (polysilicon / amorphous) photodiodes are located on the dielectric, on the surface of which the scintillator is located, on the surface of the scintillator - a source of radioactive radiation.

The invention is illustrated by the drawing, where in Fig. 1. shows the electrical circuit of the memory cell of the prototype, in Fig. 2. - electrical circuit of the memory cell of the invention according to P1, in Fig. 3. - electrical circuit of the memory cell of the invention according to P2, in Fig. 4. - electrical circuit of the memory cell of the invention according to P3, in Fig. 5. - design of the memory cell of the n-MOS RAM PV with polysilicon load transistors, in fig. 6. - design of a memory cell of a static random access memory device with a radioactive power source.

On FIG. 1 shows the electrical circuit of the prototype memory cell, which contains a common bus 1, power bus 2, address bus 3, first 4 and second 5 bit buses, first 6 and second 7 control n(p)-MOS transistors, first 8 and second 9 switching n(p)-MOS transistors, the sources of which are connected to a common bus 1, the drain of the first switching MOS transistor 8 is connected to the gate of the second switching MOS transistor 9, and the drain of the second switching MOS transistor 9 to the gate of the first switching MOS transistor 8, the gates of the control MOS transistors 6.7 are connected to the address bus 3, the sources of the first and second control transistors 6.7 are connected respectively to the drains of the first 8 and second 9 switching MOS transistors, and their drains to the first 4 and second 5 bit buses, respectively, the drain of the first switching MOS transistor 8 is connected through the first load resistor 10 to the power rail 2, and the drain of the second switching MOS transistor 9 is connected through the second load Pull resistor 11 to power rail 2.

On FIG. 2 shows the electrical circuit of the memory cell of the invention according to P1, which contains a common bus 1, power bus 2, address bus 3, first 4 and second 5 bit buses, first 6 and second 7 control n(p)-MOS transistors, first 8 and second 9 switching n(p)-MOS transistors, the sources of which are connected to a common bus 1, the drain of the first switching MOS transistor 8 is connected to the gate of the second switching MOS transistor 9, and the drain of the second switching MOS transistor 9 to the gate of the first switching MOS transistor 8, the gates of the control MOS transistors 6, 7 are connected to the address bus 3, the sources of the first and second control transistors 6,7 are connected respectively to the drains of the first 8 and second 9 switching MOS transistors, and their drains to the first 4 and second 5 bit buses, respectively, the drain of the first switching The MOS transistor 8 is connected to the anode (cathode) of the first load photodiode 10, and the drain of the second switching MOS transistor 9 is connected to the anode (cathode s) the second load photodiode 11, the cathode of the first photodiode 10 is connected to the negative pole of the first emf source. 12, and its anode is connected to the positive pole of the first emf source. 12, the cathode of the second photodiode 11 is connected to the negative pole of the second emf source. 13, and its anode is connected to the positive pole of the second emf source. 13.

On FIG. 3, the electrical circuit of the memory cell of the invention according to P2 is shown, containing a common bus 1, a power bus 2, an address bus 3, the first and second bit buses 4,5, the first and second control n(p)-MOS transistors 6,7, the first and the second switching n(p)-MOS transistors 8,9, the sources of which are connected to a common bus, the drain of the first switching transistor is connected to the gate of the second switching MOS transistor, and the drain of the second switching MOS transistor to the gate of the first switching MOS transistor 8, the gates of the control MOS transistors connected to the address bus 3, the sources of the first and second control transistors are connected respectively to the drains of the first and second switching MOS transistors 8,9, and their drains to the first and second bit buses 4,5, respectively, the first and second load photodiodes, while the drains the first and second switching n(p)-MOS transistors 8.9 are connected respectively to the anodes (cathodes) of the first and second load photodiodes 10.1 1, while the photodiodes are sources of photo emf, the positive potentials of which are located on the anodes, and the negative potential is on the cathodes of the photodiodes. The cathodes (anodes) of the photodiodes are connected to a common bus 1.

Figure 4 shows the electrical circuit of the memory cell of the invention according to P3, containing a common bus 1, a power bus 2, an address bus 3, the first and second bit buses 4.5, the first and second control n(p)-MOS transistors 6.7, the first and second switching n(p)-MOS transistors 8,9, the sources of which are connected to a common bus, the drain of the first switching transistor is connected to the gate of the second switching MOS transistor, and the drain of the second switching MOS transistor to the gate of the first switching MOS transistor 8, the gates of the control MOS transistors are connected to the address bus 3, the sources of the first and second control transistors are connected respectively to the drains of the first and second switching MOS transistors 8,9, and their drains to the first and second bit buses 4, 5, respectively, the first and second load photodiodes, while the drains of the first and second switching n(p)-MOS transistors 8.9 are connected respectively to the anodes (cathodes) of the first and second load photodiodes odes 10,11, while photodiodes are sources of photo emf, the positive potentials of which are located on the anodes, and the negative potential is on the cathodes of the photodiodes. The cathodes (anodes) of the photodiodes are connected to the address bus 3.

On FIG. 5 shows the design (topology of the section) of the known memory cell of the n-MOS RAM PV with polysilicon load transistors, taken as a prototype. The design contains switching and control n(p)-MOS transistors 6,7,8,9, located on the front surface of the silicon wafer, on the surface of which the dielectric 12 (silicon oxide) is located.

On FIG. 6 shows the construction of a memory cell . The design contains switching and control n(p)-MOS transistors 6,7,8,9 located on the front surface of a silicon wafer, on the surface of which a dielectric 12 (silicon oxide) is located, polysilicon (amorphous) photodiodes 10,11 are located on the dielectric, on the surface of which the scintillator 13 is located, on the surface of the scintillator is a source of radioactive radiation 14 (nickel-63, tritium)

EN memory cell. C. RAM PV works as follows:

In the "information storage" mode, the zero potential of the common bus 1 is supplied to the memory cell on the address bus 3 and, accordingly, the gates of the control n-MOS transistors 6,7, which disconnects the trigger cell from the bit tires 4,5.

In the "writing information" mode, a positive potential is applied to the memory cell on the power bus 2 to the address bus 3 and, accordingly, the gates of the control n-MOS transistors 6.7 relative to the common bus, and high and low potentials corresponding to the logical zero and one (or vice versa).

In the mode of "reading information" from the memory cell to the address bus 3 and, accordingly, the gates of the control n-MOS transistors 6, 7, a positive potential is applied relative to the common bus 1, and logical zero information readout amplifiers are connected to the bit buses 4,5.

In this embodiment, the electrical circuit and cell design is simpler than that of the prototype, due to the lack of a power bus (see Fig. 3)

The electrical circuit and design can be further simplified by connecting cathodes (anodes) of diodes with address bus 3 (see Fig. 4)

Photodiodes can be made in monosilicon. The use of polysilicon diodes as load resistors is not possible due to the irreproducibility of their dark currents.

Examples:

The first one is "combined" consisting in supplying the supply voltage of the circuit from an external source of emf to the power bus 2. – Vdd (for example, +5 V) with simultaneous irradiation of photodiodes with ionizing radiation fluxes, for example, photons of the optical range or radiation radiation - electrons, X-ray quanta, a-particles. The radiation-induced photocurrent of one of the diodes creates a high potential at the drain of the closed transistor of the trigger pair, almost equal to the supply voltage - Vdd. The photocurrent of the second diode is switched / shorted / by another transistor to a common bus. In this case, there is a consumption of electrical energy from the emf source. - Vdd.

The second one is "non-volatile", in this variant the emf source is - Vdd is absent and the irradiated diodes are in the "photovoltaic mode" and themselves generate a photo emf in magnitude close to the contact potential difference of the p-n junction of the photodiode (Vk - 0.7 V). In this case, the high potential at the drain of a closed transistor is practically equal to -Vk - 0.7 V.

In this case, there is no consumption of electrical energy from the emf source. - Vdd, and the memory cell is powered by a source of optical or radioactive ionizing radiation.

At the same time, the photo of the emf diodes can be created either by direct interaction of radiation with the material of photodiodes (for example, nickel-63 isotope, tritium) or indirectly through a scintillator that converts radiation into a stream of optical photons.

When a "long-lived" source of radiation (for example, from nickel-63) is placed in the microcircuit case above the memory elements of the RAM crystal, the PV becomes "non-volatile" for the user.

From FIG. 6 it can be seen that the memory cells of the "non-volatile" SRAM PV are implemented according to the standard technology of n-MOS SRAM PV - the technology for manufacturing a prototype (see Fig. 5).

In this case, photodiodes can be made of polysilicon, amorphous silicon, or other materials. Nickel-63 isotope, which is relatively safe for human health, or hydrogen isotope - tritium, etc., can be used as a radiation source. As a scintillator - cesium-iodine, phosphorus, etc.

Claims (3)

1. An electrical circuit of a 4-transistor memory cell of a static RAM device with a radioactive power source, containing a common bus, a power bus, an address bus, the first and second bit buses, the first and second control n(p)-MOS transistors, the first and second switching n(p)-MOS transistors, the sources of which are connected to a common bus, the drain of the first switching transistor is connected to the gate of the second switching MOS transistor, and the drain of the second switching MOS transistor is connected to the gate of the first switching MOS transistor, the gates of the control MOS transistors are connected to the address bus, the sources of the first and second control transistors are connected, respectively, to the drains of the first and second switching MOS transistors, and their drains, respectively, to the first and second bit buses, characterized in that it contains the first and second load photodiodes, while the drains of the first and second switching n(p) - MOSFETs connected accordingly to the anodes and cathodes of the first and second load photodiodes, the cathodes and anodes of which are connected to the power bus, or to a common bus, or to the address bus, while the photodiodes are sources of photoEMF, the positive potentials of which are on the anodes, and the negative ones on the cathodes of the photodiodes. 2. The electrical circuit of the 4-transistor memory cell according to claim 1, characterized in that the cathodes and anodes of the photodiodes are connected to a common bus. 3. The electrical circuit of the 4-transistor memory cell according to claim 1, characterized in that the cathodes and anodes of the photodiodes are connected to the address bus.

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