RU2770459C1 - Slave generator synchronization system - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: invention relates to the field of information technology, in particular to a clock network synchronization system. For this purpose, a synchronization system of slave generators is proposed, in which N-1 synchro signal transmission systems are introduced, a synchronization signal selection device, a parallel-serial converter, a modified maximum time interval error calculator, a modified maximum time interval error storage device.

EFFECT: reduction in the phase error of the synchronization signal.

1 cl, 2 dwg

Description

The invention relates to the field of telecommunication networks, in particular, to a network clock synchronization system.

For the convenience of describing the synchronization system of slave generators, we introduce the following concepts.

Clock network synchronization system (TSS system) is a technological system designed to generate, distribute, receive and restore synchronization signals in order to ensure the integrity, stability of operation and security of the unified telecommunications network of the Russian Federation (see Order of the Ministry of Communications of Russia No. 113 dated 03/21/2016 .).

Primary reference source (PEI) is a TSS technical tool that generates reference synchronization signals using quantum frequency standards or using signals from receivers of GLONASS or GLONASS / GPS satellite navigation systems (see Order of the Ministry of Communications of Russia No. 113 dated 03/21/2016 No. ).

The primary reference generator (PEG) is a technical means of the TSS of the first level of the hierarchy, which performs the functions of generating reference synchronization signals and controlling their quality, selecting a synchronization signal from one of the PEIs that is part of the PEG (see Order of the Ministry of Communications of Russia No. 113 of 03/21/2016 .).

The secondary master oscillator (SGM) is a technical means of the TSS of the second level of the hierarchy, which performs the functions of restoration, reproduction, backup and control of input synchronization signals.

Clock network synchronization signal (hereinafter referred to as the synchronization signal) - a periodic clock signal of 2048 kHz or a stream at a speed of 2048 kbit / s, structured in cycles and supercycles, generated by a master oscillator to ensure synchronous operation of communication facilities (see Order of the Ministry of Communications of Russia No. 113 dated March 21 .2016).

Time interval error (TRI) - the difference between the measured value of the time interval produced by the master oscillator and the measured value of the same time interval produced by the reference master oscillator (see Order of the Ministry of Communications of Russia No. 113 of 03/21/2016).

The maximum time interval error (MOVI) is the phase wandering parameter of the synchronization signal, which determines the maximum values of deviations of the significant phase moments in the measured signal relative to the nominal value for observation intervals of various durations and characterizes frequency errors in the synchronization signal (see Order of the Ministry of Communications of Russia No. 113 dated March 21. 2016).

Synchronization circuits are formed by the technical means of the TSS and generators of network elements of the communication means of the synchronous digital hierarchy (SDH), plesiochronous digital hierarchy (PDH) or synchronous Ethernet (SyncE) (see Order of the Ministry of Communications of Russia No. 113 of 03/21/2016).

The presence in the digital transport communication network (DTSN) of the TSN system is one of the conditions for ensuring its integrity, stability of operation and security.

до

отн. ед. Указанная точность может поддерживаться некоторое время по истечению которого, если не будет восстановлен отказавший ПЭГ или если не будет восстановлена хотя бы одна цепь синхронизации, то вследствие дрейфа частоты ВЗГ от величины зафиксированной в памяти ВЗГ в момент перехода в режим удержания, ВЗГ перейдет в режим свободных колебаний (free-run mode). Уход ВЗГ в режим свободных колебаний приведет к переходу цифровой сети в асинхронный режим работы. Этот режим считается аварийным и не допустим на ЦТСС.The main element of the TSS system is the TSS network, which is a geographically distributed complex of technical means, including: PEI, VZG, PEG, elements of restoration, maintenance and distribution of synchronization signals, transmission systems (TS) and communication lines, TSS network control system. The formation of the TSS network is carried out according to the principle of forced hierarchical synchronization of network elements. The synchronization signals generated by the PEG are transmitted to the VIG via the synchronization circuits. ICGs are driven by PEGs. VZG is used for synchronization by signals generated by PEG - the normal mode of operation of the TsTSS, in which slippage (the exclusion or repetition of one or more bits in the digital signal) is random. In emergency situations, when the PEG fails, or all synchronization circuits fail, the VZG switches to holdover mode, in which the frequency of the forced synchronization network is memorized. Depending on the VZG model, the types of generator units used in the VZG and the quality of their execution, the frequency memory accuracy can range from

before

rel. units The indicated accuracy can be maintained for some time after which, if the failed PEG is not restored or if at least one synchronization circuit is not restored, then due to the drift of the VZG frequency from the value recorded in the VZG memory at the moment of switching to the hold mode, the VZG will switch to the free mode. fluctuations (free-run mode). The departure of the VZG to the mode of free oscillations will lead to the transition of the digital network to the asynchronous mode of operation. This mode is considered emergency and is not allowed on the central heating system.

A known method for synchronizing a linear transport network built on the basis of a synchronous digital hierarchy transmission system (patent RU 2405264 C2, published 27.11.2010). In a method for synchronizing a linear transport network built on the basis of a synchronous digital hierarchy transmission system, it is proposed to include at least two VGs in series in a serial linear transport network built on the basis of an SDH transmission system, separately for each direction of transmission of synchronization signals.

There is also known a method for synchronizing a transport communication network, which is described in the industry guidance document RD 45.230-2001, as well as in the European standard ETSI EG 201793 V.I.1.1 (2000-10) and used on existing transport communication networks. To ensure the required quality of synchronization signals in the event of failures, each section of the digital communication network in which SDH transmission systems have a linear structure must receive synchronization signals from two sides. With a relatively large number of network elements in the serial synchronization chain of such a network, it is required to install the VZG. In accordance with regulatory documents (RD 45.230-2001, ETSI EG 201793 V.I.1.1 (2000-10)) the number of SDH network elements between PEG and VZG and between two VZGs should not exceed 20.

устройств измерения фазовых отклонений,

первичных эталонных источников,

устройств синхронизации с фазовой автоподстройкой частоты и вторичный задающий генератор, где

- любое целое число больше 2, при этом первые входы устройств измерения фазовых отклонений соединены с системой передачи синхросигнала, вторые входы устройств измерения фазовых отклонений подключены к выходам соответствующих эталонных источников и первым входам соответствующих устройств синхронизации с фазовой автоподстройкой частоты, вторые входы которых соединены с выходами соответствующих устройств измерения фазовых отклонений, а выходы устройств синхронизации с фазовой автоподстройкой частоты соединены со входами вторичного задающего генератора.The closest in technical essence (implementation) to the claimed system and selected as a prototype is the “Synchronization System for Primary Reference Oscillators” (patent RU 2270518 C2 published on February 20, 2006), which contains a leading primary reference oscillator connected via a synchronization signal transmission system to based on a synchronous digital hierarchy or a plesiochronous digital hierarchy with a driven primary reference oscillator containing

devices for measuring phase deviations,

primary reference sources,

synchronization devices with phase locked loop and a secondary master oscillator, where

- any integer greater than 2, wherein the first inputs of the phase deviation measuring devices are connected to the synchronization signal transmission system, the second inputs of the phase deviation measuring devices are connected to the outputs of the corresponding reference sources and the first inputs of the corresponding phase-locked synchronization devices, the second inputs of which are connected to the outputs the corresponding devices for measuring phase deviations, and the outputs of the synchronization devices with phase locked loop are connected to the inputs of the secondary master oscillator.

The technical problem is the low quality of the network clock synchronization system, characterized by a large value of the phase error of the synchronization signal, expressed in units of time - JVI, coming to the input of the VZG, and leading the digital communication network to emergency operation. The reason for the high value of the synchronization signal JVI is the passage of the synchronization signal through a single circuit from the master PEG, the absence of additional synchronization circuits from the master PEG, as well as the absence of devices for selecting the synchronization signal and prompt switching to the synchronization signal from the PEG with a lower JVI. In turn, a large value of the JVI of the synchronization signal will lead to the transition of the VZG to the mode of free oscillations, as a result of which the digital network will switch to an asynchronous - emergency operation mode.

The creation of a synchronization system for slave generators is aimed at solving this technical problem, which will improve the quality of the network clock synchronization system, reduce the value of the JVI of the synchronization signal arriving at the input of the VZG, due to the fact that N-1 transmission systems based on SDH, PDH are additionally introduced or SyncE, sync signal selector, parallel-to-serial converter, Modified Maximum Time Interval Error (MMOVI) calculator, MMOV memory.

Disclosure of invention

входами устройства выбора сигнала синхронизации, вторые выходы устройств систем передачи синхросигнала соединены с входами устройств измерения ОВИ, выходы устройств измерения ОВИ соединены с входами параллельно-последовательного преобразователя, выход параллельно-последовательного преобразователя соединен с первым входом вычислителя ММОВИ, первый выход вычислителя ММОВИ соединен с входом запоминающего устройства ММОВИ, выход запоминающего устройства ММОВИ соединен со вторым входом вычислителя ММОВИ, второй выход вычислителя ММОВИ соединен с

-м входом устройства выбора сигнала синхронизации, выход устройства выбора сигнала синхронизации, соединен со входом ВЗГ.In the claimed synchronization system of slave generators, the technical problem is solved by the fact that N-1 synchronization signal transmission systems based on SDH, PDH or SyncE, a synchronization signal selector, a parallel-to-serial converter, a MMOVI calculator, a MMOVI memory device are additionally introduced, while the first outputs N devices of synchronization signal transmission systems are connected to the first

inputs of the device for selecting the synchronization signal, the second outputs of the devices of the synchronization signal transmission systems are connected to the inputs of the devices for measuring the JVI, the outputs of the devices for measuring the JVI are connected to the inputs of the parallel-to-serial converter, the output of the parallel-to-serial converter is connected to the first input of the MMOVI calculator, the first output of the MMOVI calculator is connected to the input of the MMOVI storage device, the output of the MMOVI memory device is connected to the second input of the MMOVI calculator, the second output of the MMOVI calculator is connected to

-th input of the synchronization signal selection device, the output of the synchronization signal selection device, is connected to the VZG input.

A new set of essential features provides a reduction in the value of the JVI of the synchronization signal arriving at the input of the VZG due to the fact that additionally N-1 systems for transmitting a synchronization signal based on SDH, PDH or SyncE, a device for selecting a synchronization signal, a parallel-to-serial converter, a MMOVI calculator, a memory MMOVI device.

The analysis of the prior art made it possible to establish that there are no analogues characterized by sets of features that are identical to all the features of the claimed system. Therefore, the claimed invention meets the condition of patentability "novelty".

The “industrial applicability” of the developed synchronization system for slave generators is due to the presence of an element base, on the basis of which devices can be made that implement this system with the achievement of the result specified in the invention.

The results of the search for known solutions in this and related fields of technology in order to identify features that match the distinguishing features of the prototypes of the claimed invention showed that they do not follow explicitly from the prior art. From the level of technology determined by the applicant, the influence of the essential features of the claimed invention on the achievement of the specified technical result has not been revealed. Therefore, the claimed invention meets the condition of patentability "inventive step".

The declared objects of the system are illustrated by drawings, which show:

Fig. 1 is a block diagram of the slave generator synchronization system.

Fig. 2 - distribution of discrete values of the function of the phase error of synchronization signals, along the chains of transmission of the synchronization signal from the leading PEG, expressed in MMOVI.

Explanation of the elements shown in Fig. one:

1 - leading primary reference generator;

2-1, 2-2, ..., 2-N - synchronous signal transmission system based on synchronous digital hierarchy, plesiochronous digital hierarchy or synchronous Ethernet;

3 - device for selecting a synchronization signal;

4-1, 4-2, ..., 4-N - devices for measuring the error of the time interval;

5 - parallel-to-serial converter;

6 - calculator of the modified maximum error of the time interval;

7 shows a modified maximum slot error memory;

8 - secondary master oscillator.

входа устройства выбора сигнала синхронизации, например, ПЛИС фирмы Xilinx семейства Virtex-7 (https://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html) (блок 3). Со вторых выходов устройств СП синхросигнала СЦИ, ПЦИ, SyncE (блоки 2-1, 2-2, …, 2-N) сигналы синхронизации подаются на входы устройств измерения ОВИ сигнала синхронизации, например ИВО-2 (https://www.alto@.metropost) (блоки 4-1, 4-2, …, 4-N). Устройства измерения ОВИ сигнала синхронизации (блоки 4-1, 4-2, …, 4-N) измеряют значения функции фазовой ошибки сигналов синхронизации, выраженное в единицах измерения времени - ОВИ. Далее в расчетах ОВИ сигнала синхронизации используются дискретные значения этой функции -

(дискретное значение функции фазовой ошибки сигналов синхронизации выраженное в единицах измерения времени - ОВИ по

-ой цепи на

-м интервале наблюдения). ОВИ сигналов синхронизации вычисляется по формулеThe synchronization system of the slave generators (figure 1) functions as follows: synchronization signals from the master PEG, for example, VCH-001 (https://www.vremya-ch.com) (block 1) are transmitted over the SP of the SDH clock signal, for example OCM -K (https://www.supertel.nt-rt.ru), PCI, such as MP-8 (https://www.supertel.nt-rt.ru), SyncE, such as ACX-1000 (https:/ /www.juniper.net) (blocks 2-1, 2-2, ..., 2-N) in strict accordance with the restrictions imposed on the reference synchronization circuit (Industry Recommendation R 45.09-2001 "Connection of networks of telecom operators to the core network of clock network sync"). From the first outputs of the SP clock signal devices SDH, PDH, SyncE (blocks 2-1, 2-2, ..., 2-N), synchronization signals are fed to the first

the input of the synchronization signal selection device, for example, the Xilinx FPGA of the Virtex-7 family (https://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html) (block 3). From the second outputs of the SP clock signal devices SDH, PDH, SyncE (blocks 2-1, 2-2, ..., 2-N), synchronization signals are fed to the inputs of devices for measuring JVI of the synchronization signal, for example, IVO-2 (https://www.alto @.metropost) (blocks 4-1, 4-2, ..., 4-N). Devices for measuring JVI of the synchronization signal (blocks 4-1, 4-2, ..., 4-N) measure the values of the phase error function of the synchronization signals, expressed in units of time - JVI. Further, in the calculations of the JVI of the synchronization signal, the discrete values of this function are used -

(discrete value of the phase error function of synchronization signals expressed in time units - JVI according to

th chain on

-th observation interval). JVI of synchronization signals is calculated by the formula

-

-й отсчет ОВИ сигналов синхронизации по

-ой цепи,

- номер интервала наблюдения,

- число отсчетов на интервале наблюдения. Полученные сигналы, содержащие значения ОВИ сигнала синхронизации -

с выхода устройства измерения ОВИ сигнала синхронизации (блоки 4-1, 4-2, …, 4- N), подаются на входы параллельно-последовательного преобразователя, например ПЛИС фирмы Xilinx семейства Virtex-7 (https://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html) (блок 5). В параллельно-последовательном преобразователе (блок 5) сигналы, содержащие значения ОВИ -

ранжируются по времени в соответствии с номером цепи передачи. С выхода параллельно-последовательного преобразователя (блок 5), ранжированные сигналы, содержащие значения ОВИ сигнала синхронизации -

, подаются на первый вход вычислителя модифицированной максимальной ошибки временного интервала (ММОВИ), например ПЛИС фирмы Xilinx семейства Virtex-7 (https://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html) (блок 6). В вычислителе ММОВИ (блок 6) производятся вычисления ММОВИ -

по формулеwhere

-

-th reading of JVI of synchronization signals according to

th chain,

- observation interval number,

- the number of readings in the observation interval. Received signals containing JVI values of the synchronization signal -

from the output of the device for measuring JVI of the synchronization signal (blocks 4-1, 4-2, ..., 4-N), are fed to the inputs of a parallel-to-serial converter, for example, an FPGA from Xilinx of the Virtex-7 family (https://www.xilinx.com /products/silicon-devices/fpga/virtex-7.html) (block 5). In a parallel-to-serial converter (block 5), signals containing JVI values -

are ranked in time according to the transmission chain number. From the output of the parallel-to-serial converter (block 5), the ranked signals containing the values of the JVI of the synchronization signal -

, are fed to the first input of the modified maximum time interval error calculator (MMOVI), for example, Xilinx FPGAs of the Virtex-7 family (https://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html) (block 6). In the MMOVI calculator (block 6), MMOVI calculations are made -

according to the formula

,

,

- коэффициент памяти ОВИ (при

ММОВИ соответствует МОВИ, вычисляемой в соответствии с рекомендациями МСЭ-Т G.810 (08/96), чем меньше

, тем более значимыми оказываются текущие измерения ОВИ и, соответственно, более значимыми оказываются текущие вычисления ММОВИ. С первого выхода вычислителя ММОВИ (блок 6), сигналы, содержащие вычисленные значения ММОВИ -

поступают на вход запоминающего устройства ММОВИ, например ПЛИС фирмы Xilinx семейства Virtex-7 (https://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html) (блок 7). С выхода запоминающего устройства ММОВИ (блок 7), сигналы, содержащие значения ММОВИ, полученные на предыдущем такте работы вычислителя ММОВИ (блок 6) -

поступают на второй вход вычислителя ММОВИ (блок 6). В вычислителе ММОВИ (блок 6), значения

сравниваются со значениями ММОВИ, полученными в настоящий момент времени -

. По результатам сравнения значений ММОВИ -

с значениями ММОВИ

, сигналы синхронизации ранжируются в порядке убывания ММОВИ. Сигнал синхронизации с меньшей ММОВИ выбирается в качестве основного сигнала синхронизации ВЗГ, например, VCH-002 (https://www.vremya-ch.com) (блок 8). В вычислителе ММОВИ (блок 6) вырабатывается команда выбора основного сигнала синхронизации, которая передается с его второго выхода на

вход устройства выбора сигнала синхронизации (блок 3). Устройство выбора сигнала синхронизации (блок 7) коммутирует сигнала синхронизации с меньшей ММОВИ на вход ВЗГ (блок 8).where

- JVI memory coefficient (at

MMOVI corresponds to MTMI calculated in accordance with ITU-T G.810 (08/96) recommendations, the less

, the more significant are the current JVI measurements and, accordingly, the more significant are the current calculations of the MMOVI. From the first output of the MMOVI calculator (block 6), the signals containing the calculated values of the MMOVI -

are fed to the input of an MMOVI storage device, for example, an FPGA from Xilinx of the Virtex-7 family (https://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html) (block 7). From the output of the MMOVI storage device (block 7), signals containing the values of the MMOVI obtained at the previous cycle of the MMOVI calculator (block 6) -

are fed to the second input of the MMOVI calculator (block 6). In the MMOVI calculator (block 6), the values

are compared with the values of MMOVI obtained at the present time -

. According to the results of comparing the values of MMOVI -

with MMOVI values

, synchronization signals are ranked in descending order of MMOVI. The synchronization signal with a smaller MMOVI is selected as the main VZG synchronization signal, for example, VCH-002 (https://www.vremya-ch.com) (block 8). In the MMOVI calculator (block 6), a command is generated to select the main synchronization signal, which is transmitted from its second output to

input of the synchronization signal selection device (block 3). The synchronization signal selection device (block 7) switches the synchronization signal from a smaller MMOVI to the VZG input (block 8).

Thanks to a new set of essential features, the specified technical result is achieved due to the fact that N-1 synchronization signal transmission systems based on SDH, PDH or SyncE, a synchronization signal selection device, a parallel-to-serial converter, an MMOVI calculator, and an MMOVI memory device are introduced.

The quantitative value of the expected technical effect from the use of the proposed slave generator synchronization system was carried out through experimental studies according to FIG. 1. As a device for measuring the JVI of the synchronization signal, the IVO-2 time deviation meter was chosen.

- номер цепи передачи сигнала синхронизации от ведущего ПЭГ,

- дискретное значение функции фазовой ошибки сигналов синхронизации по

- ой цепи на

-м интервале наблюдения, выраженное в ММОВИ,

- дискретное значение функции фазовой ошибки сигнала синхронизации по единственной цепи на

-м интервале наблюдения, выраженное в ММОВИ,

- минимальное дискретное значение функции фазовой ошибки сигнала синхронизации по

-ой цепи на

-м интервале наблюдения, выраженное в ММОВИ.The quantitative value of the expected technical effect from the use of the proposed slave generator synchronization system is shown in Fig. 2, where

- number of the synchronization signal transmission chain from the master PEG,

- discrete value of the function of the phase error of synchronization signals according to

- oh chain on

-th observation interval, expressed in MMOVI,

- discrete value of the function of the phase error of the synchronization signal for a single circuit on

-th observation interval, expressed in MMOVI,

- the minimum discrete value of the function of the phase error of the synchronization signal according to

th chain on

-th observation interval, expressed in MMOVI.

, а следовательно, и с меньшей ОВИ.From the analysis of Fig. 2 it follows that it becomes possible to select a synchronization signal with a smaller MMOVI -

and, consequently, with less JVI.

Based on this, it follows that the claimed slave generator synchronization system improves the quality of the network clock synchronization system.

Claims (1)

Slave oscillator synchronization system, comprising a master primary reference oscillator connected via a synchronization signal transmission system based on a synchronous digital hierarchy, plesiochronous digital hierarchy with a slave oscillator containing N time interval error measurement devices, a secondary master oscillator, characterized in that it additionally contains N-1 synchronization signal transmission systems based on synchronous digital hierarchy, plesiochronous digital hierarchy or synchronous Ethernet, synchronization signal selector, parallel-to-serial converter, modified maximum time interval error calculator, modified maximum time interval error memory, while the first outputs of N devices of synchronization signal transmission systems connected to the first N inputs of the synchronization signal selection device, the second outputs of the devices of the synchronization signal transmission systems are connected to the inputs of the devices for measuring the error of the time interval , the outputs of the devices for measuring the error of the time interval are connected to the inputs of the parallel-to-serial converter, the output of the parallel-to-serial converter is connected to the first input of the calculator of the modified maximum error of the time interval, the first output of the calculator of the modified maximum error of the time interval is connected to the input of the memory device of the modified maximum error of the time interval, the output of the modified maximum time interval error memory device is connected to the second input of the modified maximum time interval error calculator, the second output of the modified maximum time interval error calculator is connected to the N + 1st input of the synchronization signal selection device, the output of the synchronization signal selection device is connected to the input of the secondary master generator.

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