RU2768535C1 - Fault-tolerant channel of the interprocessor exchange system with programmable and adaptive selection of data transmission lines - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: invention relates to computer technology. The fault-tolerant channel of the interprocessor exchange system with programmable and adaptive selection of data transmission lines contains the first control unit for transmitting and receiving data over one line, including a buffer for sending data, a transceiver, a packet reception control unit on the receiving side, moreover, transmission and reception control units are introduced data on one line, identical to the first block, at the same time, a data coding block is introduced into each block on the transmitting side, and a data decoding block and a data synchronization block are introduced on the receiving side, blocks of virtual channel switches, virtual channel buffers are introduced on the transmitting and receiving sides, and a block for controlling the channel operation modes is additionally introduced.

EFFECT: providing a fault-tolerant channel of the system of interprocessor exchanges with a programmable and adaptive choice of data transmission lines with increased reliability and throughput.

1 cl, 1 dwg

Description

The invention relates to the field of communication systems, in particular to mechanisms for high-speed serial data input/output.

A device is known - a channel block of an interprocessor exchange system based on multi-gigabit serial GTX transceivers from Xilinx (see http://hpc-education.unn.ru/files/conference_hpc/2011/files/174.pdf). containing the first control unit for transmitting and receiving data on one line, including a buffer for sending data, the output of which is connected to the input of the packet transmission control unit on the transmitting side, a transceiver, a packet reception control unit on the receiving side, the output of which is connected to the input of the buffer for receiving data.

On the transmitting side (output channel), data from the switch is written to a buffer for transmission over a communication channel. The buffer is a first-in-first-out (FIFΟ) queue. From there, the data is read by the packet control unit, which generates the service characteristics of the beginning and end of the packets and transmits the data to the transceiver. When the first word of the packet appears in the buffer, the packet control unit transmits the service character of the beginning of the packet. The packet is then transmitted and checked for errors in it. If there are no errors, then the end-of-packet sign without errors is transmitted to the transceiver. Otherwise, the sign of the end of the packet with errors is transmitted. The transceiver performs data encoding (applied encoding 8V/10V).

converting data from a parallel code to a serial stream of symbols and transmitting it over a differential pair.

On the receiving side (input channel), the transceiver performs the reverse actions: it converts the data into a parallel code, decodes it and transmits it to the packet reception control unit. For each received payload word, the packet receive control block adds three service flags. After receiving the service flag of the beginning of the packet, the service flag of the beginning of the packet is added to the next word and the buffer is written to receive data. If there were errors during the reception of the packet or the sign of the end of the packet with errors came, then the error flag is added to the last word of the packet, together with the service flag, the end of the packet. In the absence of synchronization between the transmitter and receiver, the control unit sets a signal to the transceiver to perform character-by-character data alignment.

The above device is the closest in technical essence to the claimed device and therefore selected as a prototype.

The disadvantages of the prototype are the lack of virtual channels, the transmission and reception of data on the same line, the use of encoding 8V/10V.

The technical problem to be solved is the creation of a fault-tolerant channel of the interprocessor exchange system with a programmable and adaptive selection of data transmission lines with increased reliability and throughput, as well as supporting both various communication network topologies and data exchanges without the occurrence of a deadlock state.

The achieved technical result is the introduction of virtual channel buffers, additional data transmission and reception lines, the use of 64V / 66V encoding, as well as programmable and adaptive selection of data transmission lines for various channel operation modes.

To achieve a technical result in a fault-tolerant channel of the interprocessor exchange system with programmable and adaptive selection of data transmission lines, containing the first control unit for transmitting and receiving data over one line, including a buffer for sending data, the output of which is connected to the input of the packet transmission control unit on the transmitting side, a transceiver, a control block for receiving packets on the receiving side, the output of which is connected to the input of the buffer for receiving data, what is new is that control blocks for transmitting and receiving data on one line are introduced, identical to the first block, while each block on the transmitting on the side, a data encoding unit is introduced, the input of which is connected to the output of the packet transmission control unit, and its output is connected to the input of the transceiver, and on the receiving side, a data decoding unit and a data synchronization unit are introduced, the input/output of which is connected to the input/output of the data decoding unit, whose input is connected with the output of the transceiver, and the output is connected to the input of the packet reception control unit, on the transmitting and receiving sides, virtual channel switch blocks, virtual channel buffers are introduced, the inputs of each buffer for sending data of all transmission and reception control sinks over one line on the transmitting side are connected to corresponding outputs of the virtual channel switch on the transmitting side, the outputs of each buffer for receiving data of all control blocks for transmitting and receiving data over one line on the receiving side are connected to the corresponding inputs of the virtual channel switch on the receiving side, an additional control unit for channel operation modes is introduced, the output of which is connected with the corresponding inputs of the virtual channel switches on the transmitting and receiving sides, the inputs and outputs of which are connected respectively to the outputs and inputs of the virtual channel buffers on the transmitting and receiving sides, the inputs and outputs of which are the inputs and outputs of the triplets.

A new set of essential features improves reliability and throughput, and also provides support for both various communication network topologies and data exchanges without the occurrence of a deadlock condition. The system capacity is increased by introducing additional data transmission and reception lines, and the system reliability is increased by introducing various channel operation modes, as well as by programmable and adaptive selection of data transmission lines. Providing support for both different topologies of the communication network and data exchanges without the occurrence of a deadlock state is carried out by introducing buffers of virtual channels.

The figure 1 shows a block diagram of the proposed device.

The fault-tolerant channel of the interprocessor exchange system with programmable and adaptive selection of data transmission lines contains the first control unit for transmitting and receiving data over one line 1, including a buffer for sending data 2. The output of which is connected to the input of the packet transmission control unit on the transmitting side 3, a transceiver 5, a control block for receiving packets on the receiving side 8, the output of which is connected to the input of the buffer for receiving data 9. The control blocks for transmitting and receiving data along one line 1.1-1.11 are identical to the first block 1, while in each block 1-1.11. on the transmitting side, a data encoding block 4 is introduced, the input of which is connected to the output of the packet transmission control block 3, and its output is connected to the input of the transceiver 5, and on the receiving side, a data decoding block 6 and a data synchronization block 7 are introduced, the input / output of which is connected to input / output of the data decoding block 6, the input of which is connected to the output of the transceiver 5, and the output is connected to the input of the control block for receiving packets 8. On the transmitting and receiving sides, virtual channel switch blocks 12 and 13, virtual channel buffers 10-10.5 and 11- 11.5, the inputs of each buffer for sending data 2-2.11 of all blocks for transmitting and receiving data on one line 1-1.11 on the transmitting side are connected to the corresponding outputs of the virtual channel switch on the transmitting side 12, the outputs of each buffer for receiving data 9-9.1 of all blocks control the transmission and reception of data on one line 1-1.11 on the receiving side are connected to the corresponding by the inputs of the virtual channel switch on the receiving side 13. A block for controlling the operating modes of the channel 14 is introduced, the output of which is connected to the corresponding inputs of the virtual channel switches on the transmitting 12 and receiving side 13, the inputs and outputs of which are connected, respectively, to the outputs and inputs of the virtual channel buffers on the transmitting 10-10.5 and the receiving side 11-11.5, the inputs and outputs of which are the inputs and outputs of the device.

The device works as follows. On the transmitting side, the data from the switch is written to the virtual channel buffers 10-10.5 for transmission over the communication channel. All six buffers 10-10.5 are identical and are a first-in-first-out (FIFO) queue. The buffer of each virtual channel 10-10.5 has a signal that is set to "1" when there is room for only one data packet. This signal is connected to the switch and is intended to prevent overflow of buffers 10-10.5.

From the buffers 10-10.5, the data is read by the virtual channel switch 12, which performs the following functions:

- switching of data packets between buffers of virtual channels 10-10.5;

- word formatting depending on the operating mode of the channel unit;

- writing data to asynchronous buffers of lines 2-2.11 corresponding to the mode of operation;

- processing information about the status of the buffers of virtual channels of the receiver 11-11.5.

The virtual circuit switch 12 determines which virtual circuit buffer 10-10.5 to read data from. Switching from one buffer of virtual channels 10-10.5 to another occurs after reading the sign of the end of the packet. If the data is in only one buffer of virtual channels 10-10.5, then they will be read from it, out of order. The packet starts to be read if the corresponding virtual channel buffer is not filled on the receiving side 11-11.5. When receiving information about the filling of the buffers of the virtual channels of the receiver 11-11.5, the switch 12 stops the process of transmitting packets over the channel. The data transmission is resumed when the signal about the release of buffers 11-11.5 is established. The virtual circuit switch on the transmitting side 12 supports the following modes of operation:

- x12 mode - data transmission and reception is carried out simultaneously via 12 independent lines;

- x8 mode - data transmission and reception is carried out simultaneously via eight independent lines;

- x4 mode - data transmission and reception is carried out simultaneously by four independent ones.

- mode x1 - data transmission and reception is carried out on one line.

The channel unit contains 12 identical and independent control units for transmitting and receiving data over one line 1-1.11. Each control unit 1-1.11 operates at its own clock frequency for transmitting and receiving data.

To transfer data from the clock frequency of the switch to the clock frequency of line 1, an asynchronous buffer 2 is used. Data is written to buffer 2 by the virtual channel switch on the transmitting side 12 at the frequency of the switch, and are read by the packet transmission control unit 3 on a clean line.

When the first word of the packet appears in the buffer 2, the packet control unit 3 transmits the service character of the beginning of the packet. Together with this symbol, the number of the virtual channel from which the packet was read is transmitted. Then a packet is transmitted and each word is checked for the presence of a packet terminator. After reading the last word of the packet from buffer 2, it is checked whether there are errors in this packet. If there are none, and there were no errors during the transmission of the packet, then the sign of the end of the packet without errors is transmitted to the channel. Otherwise, the sign of the end of the packet with errors is transmitted.

With each data word (frame) its header is transmitted. The frame header (preamble) defines the type of data to be transmitted. There are two types of frames: a data frame (preamble = "01") and a control information/data frame (preamble = "10").

The preambles "00" and "11" are considered erroneous, and when such a preamble is received by the data synchronization unit 7, a frame synchronization error is detected.

Data transmission stops when a signal is set indicating that the buffers of the receiver lines 9-9.11 are full. Data transfer resumes when this signal is cleared. During data transmission, the state of the receiver buffers 9-9.11 is constantly analyzed. In case of a change in the state of buffers 9-9.11, the corresponding information is transmitted over the channel.

The packet control unit 3 sends words to the input of the data encoding unit 4. First, the data is scrambling, i.e. the input data is converted into a pseudo-random sequence. This is necessary to ensure the balance of "0" and "1" in the serial data stream. Frame preambles are not scrambled and are used by data sync 7 to determine word alignment boundaries. The use of a scrambler does not guarantee a uniform distribution of "0" and "1" in the serial stream, however, the choice of values "01" and "10" as allowed frame preambles guarantees that at least one transition from "0" to "1" or from "1" to "0" occurs at least every 66 bit intervals. Then, the 66-bit output bus of the scrambler, accompanied by a truth signal, is converted into a 64-bit input bus of the transceiver 5. Since a two-bit preamble is transmitted along with 64-bit frames, a pause is made every 32 cycles for one cycle to avoid data loss.

The coding unit 4 transmits data to the input of the transceiver 5. The transceiver 5 converts the data from the parallel code into a serial symbol stream and transmits it over a differential pair. Upon reception, it inverts the serial data stream into parallel code.

Next, the data is fed to the input of the decoding block 6. First, frames and their preambles are formed from the received data. On a signal set by the data synchronization block 7. the frame boundary is shifted by one bit. Then the input scrambled code is converted to the original data format. The data preamble does not require descrambling and is used by data sync block 7 to determine frame boundaries.

The data synchronization block 7 analyzes the synchronizing frame headers and sets the signal to the data decoding block 6 to shift the word boundary by one bit. Allowed headers are "01" and "10". erroneous headers - "00" or "11".

The packet reception control unit 8 receives data from the decoding unit 0. After receiving the service character of the start of the packet, the control unit 8 switches to the packet reception mode, adds three service flags to each received word and writes the words to the asynchronous buffer 9. The number of the virtual channel is added to each word , indicating in which virtual channel buffer 11-11.5 to write the received packet. To align the data block switch virtual channels on the receiving side 13 to each word is added to its number in the data packet and the packet number. If there were errors during the reception of the packet or the sign of the end of the packet with errors came, then the error flag is added to the last word of the packet, together with the service flag, the end of the packet. After the line synchronization is established and the receiver synchronization signal is received from the channel, the packet reception control unit 8 sets the sign of the line readiness for data transmission and reception.

An asynchronous buffer 9 is used to transfer data from the line clock frequency to the switch clock frequency. Data is written to the buffer 9 by the packet transmission control unit 8 on a clean line, and read by the virtual channel switch on the receiving side 13 at the switch frequency.

The virtual circuit switch on the receiving 13 side performs the following functions:

- packet switching between virtual channel buffers 11-11.5;

- word formatting, depending on the mode of operation of the channel unit;

- reading data from asynchronous line buffers 9-9.11 corresponding to the mode of operation;

- word-by-word alignment of received data;

- processing information about the status of the buffers of virtual channels 11-11.5 of the receiver.

The virtual circuit switch 13 reads data from the asynchronous line buffers 9-9.11 and determines which virtual circuit buffer 11-11.5 to write them to. All six buffers 11-11.5 are identical. Upon receipt of information about the filling of the buffers of the virtual channels of the receiver 11-11.5. the switch 13 sets the data transmission stop signal. The reading of the data packet begins when data with the sign of the beginning of the packet appears in all buffers of lines 9-9.11 corresponding to the mode of operation. The number of each word and the packet number are checked. If, when reading the data, the words will have different numbers, then the virtual channel switch 15 sets a signal, but to which the channel block will be reset. If during data reception a symbol error occurs on one of the lines 1-1.11, then the sign of the end of the packet with an error 11-11.5 will be written to the virtual channel buffer. The virtual circuit switch on the receiving side 13 supports x12, x8, x4 and x1 operating modes.

The selection of the virtual channel buffer 11-11.5 for recording data on the receiving side is carried out in the virtual channel switch block 13. Therefore, in the channel block, together with each packet, the number of the virtual channel from which the packet was read is transmitted. On the receiving side, in accordance with this number, each packet is written to the corresponding virtual channel buffer 11-11.5.

Information about the status of the buffers of the virtual channels of the receiver 11-11.5 is transmitted after each packet, and if it changes, directly during the transmission of the packet. If the space in the buffer 11-11.5 runs out, then the data transmission over the channel should stop until the buffer 11-11.5 is free. Thus, there is protection against possible data loss associated with lack of space in the virtual channel buffers on the receiving side 11-11.5.

Channel 14 mode control block is responsible for switching between x12 modes. x8, x4 or x1. By default and after the reset procedure in the channel, it is set to x12 mode. If the number of synchronized (active) lines 1-1.11 is less than 12, but more than or equal to eight, then the transition to x8 mode is performed. If the number of active lines 1-1.11 is less than eight, but greater than or equal to four, then the transition to x4 mode is performed. If the number of active lines 1-1.11 is less than four, but there is at least one active line 1-1.11, then the transition to the x1 mode is performed. Switching between modes is carried out automatically in case of loss of synchronization on lines 1-1.11. and forcibly, when receiving a command. Any combination of lines 1-1.11 can be used. corresponding in number to the required mode of operation, provided that lines 1-1.11 are active. The transition to the mode with a large number of lines 1-1.11 can only be carried out after the reset procedure or after disconnecting and connecting the cable.

The fault-tolerant channel of the interprocessor exchange system with programmable and adaptive selection of data transmission lines has been tested and proved to be operable as part of the firmware of a programmable logic integrated circuit on prototyping boards.

The use of this device as part of the firmware of the interprocessor exchange system made it possible to increase the throughput of one channel by about 12 times compared to the prototype due to the use of additional lines for transmitting and receiving data and encoding 64 V / 66 V. The reliability of the system has also increased due to the introduction of additional operating modes channels x12, x8, x4, x1, as well as due to programmable and adaptive selection of data transmission lines. The introduction of virtual channel buffers provided support for both various communication network topologies and data exchanges without deadlock.

Claims (1)

A fault-tolerant channel of the interprocessor exchange system with programmable and adaptive selection of data transmission lines, containing the first control unit for transmitting and receiving data over one line, including a buffer for sending data, the output of which is connected to the input of the packet transmission control unit on the transmitting side, a transceiver, a block packet reception control on the receiving side, the output of which is connected to the input of the buffer for receiving data, characterized in that the control blocks for transmitting and receiving data on the same line are introduced, identical to the first block, while each block on the transmitting side contains a data coding block, the input which is connected to the output of the packet transmission control unit, and its output is connected to the input of the transceiver, and on the receiving side, a data decoding unit and a data synchronization unit are introduced, the input/output of which is connected to the input/output of the data decoding unit, the input of which is connected to the output of the transceiver, and the output is connected It is with the input of the packet reception control unit, on the transmitting and receiving sides there are virtual channel switch blocks, virtual channel buffers, the inputs of each buffer for sending data of all data transmission and reception control blocks over one line on the transmitting side are connected to the corresponding outputs of the virtual channel switch on to the transmitting side, the outputs of each buffer for receiving data of all data transmission and reception control blocks over one line on the receiving side are connected to the corresponding inputs of the virtual channel switch on the receiving side, an additional channel control unit is introduced, the output of which is connected to the corresponding inputs of the virtual channel switches on the transmitting and receiving sides, the inputs and outputs of which are connected respectively to the outputs and inputs of the virtual channel buffers on the transmitting and receiving sides, the inputs and outputs of which are the inputs and outputs of the device.

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