RU2748897C1 - Reconfigurable encoder of polar codes of 5g networks - Google Patents

Abstract

FIELD: electrical engineering.SUBSTANCE: invention relates to electrical engineering, to the field of digital signal processing (DSP). The invention includes using a single memory array of N elements, N/2 XOR adders, while multiplexers are absent, due to the absence of the need to reconfigure the switching with each clock cycle.EFFECT: providing a reconfigurable encoder of polar codes of 5G networks with increased performance and lower hardware costs.1 cl, 3 dwg

Description

The invention relates to electrical engineering, to the field of digital signal processing (DSP), namely to reconfigurable encoders for polar codes of 5G networks and can be used in devices for encoding polar codes.

One of the main methods to improve the reliability and efficiency of data transmission is error-correcting coding. Polar codes reach the Shannon boundary of the memoryless binary symmetric channel and are by far the most efficient. They are used, inter alia, in 5G 5G networks, which requires coding devices to be reconfigurable in length and code rate.

A widespread encoder scheme with several stages in the number of log2 (N), where N is the length of the code. Moreover, each stage is distinguished by a unique switching scheme for incoming and outgoing nodes. The structural diagram of the encoder is very similar to the fast Fourier transform computation circuit with the difference in the computational nodes. The main computational unit of the encoder is an adder modulo two; in the hardware implementation, the XOR element is "exclusive OR". The hardware implementation of such devices requires a rather complex switching circuit from stage to stage, which increases the amount of hardware resources, as well as the critical path of the circuit, and therefore reduces the performance. For fifth generation (5G) telecommunications systems, high performance and the ability to change the code length and correction ability (in the compartment code rate) are extremely important.

Known (patent EP3598674, 2018.03.24, Encoding Method, Decoding Method, Apparatus and Device) encoder circuit with a different switching structure from stage to stage.

The disadvantage of this encoder is the increased hardware costs due to the presence of a large number of multiplexers.

Closest to the claimed invention is the encoder described in the application US2015 / 0333775, 2015.11.19, Frozen-bit Selection for a Polar Code Decoder, with a unified structure from stage to stage. This encoder is selected as a prototype of the claimed invention.

The disadvantage of the prototype encoder is the presence of several switching stages, which increases the amount of hardware resources, as well as the critical path of the circuit, which means that it slows down the performance.

The technical result of the invention is the creation of a reconfigurable encoder for polar codes of 5G networks with increased speed and lower hardware costs, due to the use of one memory array of N elements, N / 2 XOR adders, as well as due to the absence of multiplexers, due to the absence of the need to reconfigure the commutation with each tact.

сумматоров (103) по модулю 2,

одноразрядных регистров (102), выполненных с возможностью хранения входных и промежуточных значений и

мультиплексоров (101), при этом нулевые входы мультиплексоров (101) являются входами кодера, входы селектора мультиплексоров (101) соединены с входом calc кодера, при этом выходы

мультиплексоров (101) соединены с входами

регистров (102), выходы с нулевого по

-ый регистров (102) соединены с первыми входами

сумматоров (103), с вторыми входами которых соединены выходы с

по

регистров (102), которые являются нечетными с первого по

выходами кодера, а четные, с 0 по

, выходы кодера подключены к выходам

сумматоров (103), при этом выходы с 0 по

кодера также подключены к первым входам

мультиплексоров (101).The stated technical result was achieved by creating a reconfigurable encoder for polar codes of 5G networks for codes of length N, containing

adders (103) modulo 2,

single-bit registers (102), configured to store input and intermediate values and

multiplexers (101), while the zero inputs of the multiplexers (101) are the inputs of the encoder, the inputs of the multiplexer selector (101) are connected to the calc input of the encoder, while the outputs

multiplexers (101) are connected to the inputs

registers (102), outputs from zero to

th registers (102) are connected to the first inputs

adders (103), with the second inputs of which the outputs are connected

by

registers (102), which are odd from the first to

encoder outputs, and even, from 0 to

, encoder outputs are connected to outputs

adders (103), while the outputs from 0 to

encoder also connected to the first inputs

multiplexers (101).

For a better understanding of the claimed invention, the following is a detailed description with the corresponding graphic materials.

FIG. 1. Conventional bit-reversed coding scheme known in the art.

FIG. 2. Unified polar code switching circuit according to the invention.

FIG. 3. Diagram of a reconfigurable encoder for polar codes of 5G networks, made according to the invention.

Elements:

101 - multiplexers;

102 - one-bit registers;

103 - adders.

Let us consider in more detail the operation of the claimed reconfigurable encoder for polar codes of 5G networks (Figs. 1 - 3).

, где

- кодовое слово;

- вектор, включающий информационные символы

и «замороженные» биты

;

- порождающая матрица, задаваемая выражением

, где

- матрица перестановки. The encoding procedure is specified by the expression

where

- codeword;

- vector including information symbols

and frozen bits

;

is the generating matrix given by the expression

where

is the permutation matrix.

A classical prior art scheme implementing this encoding expression is shown in FIG. 1, for N = 8. The circuit is structurally similar to the frequency decimation FFT (Fast Fourier Transform) circuit. The main computational node is an adder modulo two, which, when implemented in hardware, is made in the form of an XOR element - "exclusive OR".

The switching circuit in FIG. 1 is different at each stage, therefore, each stage requires its own non-unified address decoder and a complex system of multiplexers.

The claimed unified switching scheme is shown in FIG. 2. Structurally, these two schemes differ in the way of connecting computational nodes and memory elements. In the classical scheme, the commutation lines are parallel, and the result of calculating one stage falls into the same addresses from where the operands were taken for calculation (ie, the "in place" scheme), thus the read address coincides with the write address. This approach requires different logic in calculating the address from stage to stage. In the circuit of the claimed encoder, the switching lines are not parallel, and the read and write addresses are different for one computing node, however, the switching is unchanged from stage to stage. Algorithmically, these circuits are equivalent, since after the required number of stages log2 (N), all the results will be located in the same cells of both circuits.

Similarly, you can build a circuit for any N. Based on the declared unified switching circuit (N = 8) for the general case (any N), you can write an iterative expression:

(1)

(one)

– значение (входной отсчет или промежуточное значение), считываемое из

-ой ячейки памяти

-ой стадии конвейера;

– вычисленное значение, записываемое в

-ой ячейки памяти

-ой стадии конвейера;

– сумматор по модулю 2.Where

- value (input sample or intermediate value) read from

-th memory cell

-th stage of the conveyor;

Is the calculated value written to

-th memory cell

-th stage of the conveyor;

- adder modulo 2.

или

, при этом если использовать классическую схему коммутации кодера (Фиг. 1), необходимо использовать первые

элементов памяти, в остальных должны быть записаны нули, при этом количество стадий должно уменьшиться соответственно

. Таким образом, и в заявленной унифицированной схеме (Фиг. 2) требуется выполнить тоже самое, так как схемы эквивалентны по расположению входных и выходных значений.Often a shorter code length is required, namely

or

, in this case, if you use the classical encoder switching scheme (Fig. 1), you must use the first

memory elements, the rest must be written with zeros, while the number of stages must decrease accordingly

... Thus, in the claimed unified circuit (Fig. 2), it is required to do the same, since the circuits are equivalent in the arrangement of the input and output values.

The declared unified switching scheme has the following advantages.

First, the unified circuit has a single commutation between all stages of the computation and eliminates the complex multiplexing system inherent in the classical circuit.

Secondly, based on a unified scheme, an encoder can be developed for various purposes:

вычислительных узлов (элементов «исключающее ИЛИ») и элементов памяти (один элемент для хранения одного бита);- for maximum performance - fully parallel, pipelined, requiring

computing nodes ("exclusive OR" elements) and memory elements (one element for storing one bit);

, работающих параллельно, и два массива памяти объема

бит.- for target tasks - a sequentially parallel scheme, iterative, requiring several computational nodes, no more

operating in parallel, and two memory arrays of size

bit.

To reduce hardware costs, the claimed unified switching scheme allows the development of a series-parallel circuit. This circuit shown in FIG. 3 is a diagram of the claimed invention, a reconfigurable encoder for polar codes of 5G networks. Due to the unified structure from stage to stage, you can leave only one stage by adding registers (102) for storing intermediate values and input multiplexers (101) for switching input values and intermediate values. This encoder scheme is easily reconfigurable in terms of the code length by writing only the first required values, while the rest remain at zero value. To encode a word of length N, the circuit, after writing the input values, works for log2 (N) clock cycles, after the code values become available at the output of the circuit.

The claimed invention presents an encoder circuit with a single stage performing arithmetically all the stage operations required in the classical scheme. Thus, the declared encoder, after writing all N input values (including the "frozen" bits), requires log2 (N) clock cycles to encode. At the same time, the hardware requires the same amount of resources as is necessary for one stage of the classical scheme, and the critical path is extremely short, which increases the performance. Also, the claimed encoder is configurable in terms of length and code rate without additional hardware costs.

The claimed invention is intended for the development of polar codes encoding devices. The invention contains a unified (single) circuit for switching values from memory for basic computation nodes for all computation stages. The declared encoder is built on the basis of a single switching scheme with minimal hardware costs. To build the declared encoder, only one memory array of N elements, N / 2 XOR adders is required. In this case, the design of the claimed encoder does not require reconfiguration of the commutation with each such encoder, which means that multiplexers are not required.

Although the above embodiment has been set forth for the purpose of illustrating the present invention, it will be apparent to those skilled in the art that various modifications, additions and substitutions are possible without departing from the scope and spirit of the present invention as disclosed in the appended claims.

Claims (1)

Reconfigurable encoder for polar codes of 5G networks for codes of length N, containing

adders (103) modulo 2,

single-bit registers (102), configured to store input and intermediate values and

multiplexers (101), while the zero inputs of the multiplexers (101) are the inputs of the encoder, the inputs of the multiplexer selector (101) are connected to the calc input of the encoder, while the outputs

multiplexers (101) are connected to the inputs

registers (102), outputs from zero to

th registers (102) are connected to the first inputs

adders (103), with the second inputs of which the outputs are connected

by

registers (102), which are odd from the first to

encoder outputs, and even, from 0 to

, encoder outputs are connected to outputs

adders (103), while the outputs from 0 to

encoder also connected to the first inputs

multiplexers (101).

Images