RU2746237C1 - Method and system for reading the state of a magneto-resistive memory cell with stt-mram spin transfer - Google Patents

Abstract

FIELD: computer technology.SUBSTANCE: method for reading the state of a magneto-resistive memory cell with STT-MRAM spin transfer consists in generating a Vrdreading signal during the Trdtime of reading the memory cell. The Vrdsignal voltage in a given time range T2falls periodically below the set value of the stabilization pulse Vlo, and in a given time range T1reaches a Vhivalue that is higher than the Vlovalue.EFFECT: reduced probability of reading perturbation.14 cl, 11 dwg

Description

FIELD OF TECHNOLOGY

[0001] The present invention relates to the field of creating and interacting with storage devices, in particular, to a method and system for reading the state of a cell in a spin transfer magnetoresistive memory (STT-MRAM).

LEVEL OF TECHNOLOGY

[0002] A small voltage is applied and / or a small read current through the cell is applied to read the state of the STT-RAM memory cells. In this case, the value of the obtained current and / or voltage drop across the cell is compared with the reference level, thus establishing the state of the cell "0" or "1". Writing or erasing a cell occurs in a similar way, but with a large value of the applied voltage and / or current. The probability of cell switching at voltages much lower than the write voltage is small, but nonzero and exponentially depends on the voltage. Thus, there is a finite probability that the cell will switch on read voltage. This unwanted event is called Read Disturb, and the probability of the corresponding event in a single reading is called the Read Disturb Rate. For the memory to function, it is necessary to reduce the probability of disturbance by reading to 10 ^-24 or, when using error correction schemes, to 10 ^-12 . In real structures, however, it can take on large values (AV Khvalkovskiy et al., J. Phys. D: Appl. Phys. 46 (2013) 074001).

[0003] From the patent US 8107280 (Qualcomm Inc, 01/31/2012) a classical approach to constructing circuits for reading the state of storage cells is known. In this readout circuit, there is a readout amplifier and a reference signal unit. When reading through the MTJ (magnetic tunnel junction) of the memory cell, the bias current i_rd is set. For example, with nominal high and low resistance levels of 1 kΩ and 3 kΩ, it may be necessary to set the i_rd current to about 100 μA to achieve the 100 and 300 mV voltages required for stable gain to logic levels by the sense amplifier. For many cells, these applied voltages and currents result in a high reading disturbance probability of 10 ^-5 -10 ^-3 , which may require a memory and logic-intensive error correction circuit to correct. This necessitates the creation of new circuits and methods of reading memory cells in such a way as not to lead to switching the state of the memory cell.

DISCLOSURE OF THE INVENTION

[0004] To solve the above technical problem, the principle of a memory cell reading circuit is proposed, which is based on several factors set forth below.

[0005] First, for the magnetic memory cell STT-MRAM, there is a so-called thermal relaxation time of magnetization t ₀ - the characteristic time during which the magnetic state of the cell returns to the equilibrium state when disturbed. It is, depending on the parameters of the material, from fractions to units of a nanosecond (AV Khvalkovskiy et al., J. Phys. D: Appl. Phys. 46 (2013) 074001). When the duration of the read voltage through the cell t _{rd is} significantly greater than t ₀ (as a rule, more than 10t ₀ ), the probability of perturbation by reading linearly depends on the time t _rd ; For example, for some cell parameters, when t _rd decreases from 60 ns to 50 ns, the probability of perturbation by reading can drop by a factor of 1.2. This mode is called “thermally activated reading”. However, if the reading time is noticeably less than 10t ₀ , then the probability of perturbation by reading exponentially depends on the time t _rd ; For example, for some cell parameters, when t _rd decreases from 6 ns to 5 ns, the probability of perturbation by reading can fall by more than 10 times. This mode is called "precessional reading". Thus, to minimize the likelihood of cell switching, it is desirable to apply as short a read pulse as possible so that reading occurs in a precessional mode.

[0006] On the other hand, in order to increase the signal-to-noise ratio and reliably determine the states high (logical one) - low (logical zero), it is necessary to apply as long as possible a read pulse through the MTJ cells. Otherwise, noise in the read circuit can lead to incorrect determination of the logic states of the high-low cell (circuit error).

[0007] Finally, for each logical state of the cell, only a pulse of one polarity will result in a read disturbance, while a pulse of the opposite polarity, conversely, stabilizes the state of the cell.

[0008] The present invention proposes an approach that, in its most complete implementation, takes advantage of all three of the above technological features.

[0009] For this, as one solution, it is proposed to split the read operation with the total duration t _rd into several successive pulses, for each of which there is a read in the precessional mode followed by a short relaxation pulse (during which, either zero or the voltage value is noticeably lower than when reading).

[0010] As a development of this solution, it is proposed to supply pulses with the opposite signal amplitude as relaxation pulses, while integrating the resulting voltage drops, taking into account the sign of the applied action.

[0011] The technical result achieved by the implementation of the claimed invention is to significantly reduce the probability of disturbance by reading and, thus, to increase the reliability of determining the states of STT-MRAM memory cells, due to the fact that at each moment of time, either a read pulse with a very small the probability of disturbance by reading ("reading in precessional" mode), or an impulse that stabilizes the initial magnetic state.

[0012] The claimed result is achieved due to the method of reading the state of the magnetoresistive memory cell with the spin transfer STT-MRAM, which consists in generating a read signal V _rd during T _rd reading the memory cell, and the signal voltage V _rd periodically falls below the set value of the stabilization pulse V _lo in a given time range T ₂ , and above V _lo , reaching a value of V _hi in a given time range T ₁ .

[0013] In one of the particular examples of the implementation of the method, the signal level V _lo differs from the level V _hi at least 1.25 times.

[0014] In another particular embodiment of the method, V _lo is a null signal.

[0015] In another particular example of the implementation of the method, the duration of the residence time of the readout signal V _rd below the value of the stabilization pulse V _{lo is} approximately equal to the thermal relaxation time T ₀ .

[0016] In another particular embodiment of the method, T ₁ ranges from 0.1 ns to 20 ns.

[0017] In another particular example of the implementation of the method, T ₂ ranges from 0.3 ns to 10 ns.

[0018] In another particular example of the implementation of the method, the signal level V _lo has the opposite sign from the sign of V _hi and differs in amplitude.

[0019] The claimed invention is also implemented using a system for reading the state of a cell of a spin transfer magnetoresistive memory STT-MRAM, the system comprising:

- readable memory cell connected to the first and second keys, providing switching of the sign of action on the readable cell;

- generator of control signal by the sign of influence on the read cell, providing the formation of control signals that determine the period of reading the memory cell with a changing sign of the influence;

- a voltage source connected to the first switch;

- an integrator connected to the second key;

- a source of reference voltage, providing the formation of the readout voltage;

- a comparator that compares the voltage accumulated on the integrator with the voltage of the reference voltage source;

moreover

- the generator of the control signal by the sign of the influence on the read cell provides the formation of control signals that form the period of reading the memory cell with the changing sign of the influence due to the switching of the first and second keys on the signal of the current acting on the memory cell.

[0020] In one particular implementation example, the system further comprises a shunt key that provides the transfer of the state of the upper contact of the cell to the zero level.

[0021] In another particular example of the implementation of the system, the reference voltage source contains a group of keys that ensure switching the sign of the action on the read cell, and memory cells forming a set of resistances with predetermined states.

[0022] The claimed invention is also carried out using another version of the system for reading the state of the cell of the magnetoresistive memory with spin transfer STT-MRAM, wherein the system comprises:

- readable memory cell connected to the first and second group of keys, providing switching of the sign of action on the readout cell;

- generator of control signal by the sign of influence on the read cell, providing the formation of control signals that determine the period of reading the memory cell with a changing sign of the influence;

- a voltage source connected to the first group of switches;

- an integrator connected to the second group of keys;

- a source of reference voltage, providing the formation of the readout voltage;

- a comparator that compares the voltage accumulated on the integrator with the voltage of the reference voltage source;

moreover

- the generator of the control signal by the sign of the influence on the read cell provides the formation of control signals that form the period of reading the memory cell with a changing sign of the influence due to the switching of the first and second groups of keys on the signal of the current acting on the memory cell.

[0023] In one particular example of the system implementation, each key group contains four keys.

[0024] In another particular example of the implementation of the system, in each of the group of keys, one pair of keys closes on the high state of the control signal, and the second pair - on the low.

[0025] In another particular example of the implementation of the system, the reference voltage source contains two groups of keys providing switching of the sign of the action on the read cell, and memory cells forming a set of resistances with predetermined states.

BRIEF DESCRIPTION OF DRAWINGS

[0026] FIG. 1A illustrates a prior art read signal diagram.

[0027] FIG. 1B illustrates diagrams of read signals in accordance with the claimed invention.

[0028] FIG. 2 illustrates the claimed scheme for reading memory cells.

[0029] FIG. 3 illustrates a bypass key readout circuit.

[0030] FIG. 4 illustrates a readout circuit with relaxation pulses of opposite sign relative to the read pulses.

[0031] FIG. 5 to FIG. 6 illustrate diagrams of readout circuit control signals.

[0032] FIG. 7 illustrates a circuit for a voltage reference for a readout circuit.

[0033] FIG. 8 illustrates a voltage reference circuit for a readout circuit with opposite amplitude relaxation pulses.

[0034] FIG. 9 illustrates an integrator circuit.

[0035] FIG. 10 illustrates the signal diagrams at the outputs of the integrators of the reading circuit and the voltage reference.

CARRYING OUT THE INVENTION

[0036] FIG. 1A - FIG. 1B shows examples of V _rd read signal diagrams. In the current prior art approach shown in FIG. 1A, a continuous signal level S1 is used, equal to some constant value of V _hi during the entire duration of the read operation t _rd .

[0037] When implementing the claimed invention depicted in FIG. 1B, it is proposed for the readout signal S2 during the readout time of the cell state t _rd to vary the readout signal shape in such a way that:

- periodically, the signal level V _rd would fall below a certain level V _lo ("stabilization pulse");

- in this case, the signal level V _{lo of the} stabilization pulse would be less than the signal level with the reading pulse V _hi , at least 1.25 times, and sometimes much more (2 times or more), or approximately equal to the zero signal;

- the duration of the read pulse t _l , during which the level of the read signal reaches the level of the read signal V _hi (above the level V _lo ), would be much less than the time 10t ₀ , so that within this interval the reading would take place in the "precessional mode";

- in this case, the duration of the stabilization pulse t ₂ , during which the reading signal is below the level V _lo , would be of the order of the thermal relaxation time t ₀ , so that the magnetization would have time to relax to a state close to equilibrium.

[0038] For most materials, the t ₁ read pulse width can range from 0.5 ns to 10 ns, while in some applications it can range from 0.1 ns to 20 ns. In this case, the smaller t ₁ , the greater the gain from the application of this scheme, however, the more complex its implementation.

[0039] The duration of the stabilization pulse t ₂ for most materials should be on the order of 1-3 ns, while in some systems it can vary from 0.3 ns to 10 ns. In this case, for too short stabilizing pulses, the effect of stabilizing the magnetic state of the cell may not occur and the efficiency of the circuit will decrease (the magnetization does not have time to relax to the equilibrium value), and for too large values of t ₂ , the circuit noise increases at a fixed total operation time t _rd , i.e. ... its effectiveness also decreases.

[0040] As one of the implementations of the claimed invention - signal S3, the signal level V _lo in the stabilizing pulse can have a sign opposite to V _hi , and in absolute value it does not exceed V _{hi by} more than 1.25 times, while this signal is integrated through the cell , taking into account the sign of the applied impact. Thus, the current flowing during the stabilization pulse makes the same contribution to the comparator signal as the current flowing during the reading pulse, as described in more detail below.

[0041] It should be noted that the total readout time t _rd for signals S1, S2, S3 is generally different. Also, in the general case, the values of V _hi and V _lo can also be different for signals such as S1, S2, S3.

[0042] FIG. 2 shows an example of the implementation of the reading circuit (10) of the memory cell (110). The read voltage / current source (104) is used to generate the read voltage on the cell (110). The generator (103) of the signal for controlling the sign of the action on the read cell (110) provides the formation of control signals that determine the reading period of the memory cell (110) with a changing sign of the action, due to the connection to the readout voltage / current source (104). The readout voltage / current source (104) is connected through one of its inputs to the key K1 (1011). The second key K2 (1021) is connected to one input of the integrator (105). The source (104) through the second output is connected to the second input of the integrator (105) without the use of switches. A comparator (107) compares the voltage stored on the integrator (105) with the voltage of the reference voltage source (106). The state of the cell (110) is determined by the fact that the accumulated voltage level at the input "+" of the comparator (107) exceeds the level of the reference signal at its input "-".

[0043] FIG. 3 shows an embodiment of the reading circuit (11) with a bypass key K3 (1031). Key K3 closes at the moment of opening keys K1 (1011) and K2 (1021), thus transferring the state of the upper contact of the cell to the zero level.

[0044] FIG. 4 shows a variant of the circuit (12) for reading the memory cell (110), which implements the signal S3 with relaxation pulses of the opposite sign relative to the reading pulses. Unlike schemes (10) and (11), the signal of the generator for controlling the action sign (103) switches the groups of keys "Keys 1" (1071) and "Keys 2" (1081). Keys K1 and K3 in each of the groups of Keys (1071) and (1081) are closed by a high state of the control signal, K2 and K4 - by a low one. The group of keys "Keys 2" (1081) is connected to the integrator (105). The group of keys "Keys 2" (1081) is necessary in order for the integrator (105) to receive a signal of a positive sign.

[0045] The comparator (107) compares the voltage stored across the integrator (105) with the voltage of the reference voltage source (116). The state of the cell (110) is determined by the fact that the accumulated voltage level at the input "+" of the comparator (107) exceeds the level of the reference signal at its input "-".

[0046] FIG. 5 shows the waveforms of the control signals, and FIG. 6 - the resulting waveforms of the impact on the cell (110). Signal (201) sets the total duration of the changing action (203/204) on the cell (110), thus, it determines the reading period (t _rd ). The generator (103) generates a signal (202). The signal (202) controls the keys K1, K2 in the circuit (10) (Fig. 2) and other presented key schemes, setting the read (t ₁ ) and relaxation (t ₂ ) pulses to the memory cell (110). Signals (203) and (204) are examples of the resulting effect on the read cell (110). The difference between signal (203) and signal (204) is the transition of signal (203) to the negative voltage region, while signal (204) has significantly different from zero values of only one sign (positive for signal (204) shown in Fig. 6) ...

[0047] FIG. 7 shows a diagram of a reference voltage source (106). The source (106) is built on a similar principle of influencing the readable memory cells (110). In the embodiment shown in FIG. In the 7th example, the voltage reference (106) includes four cells (1064) with a predetermined state "1" and "0". Due to the series-parallel connection, the total resistance of the group of cells is:

However, it should be noted that the number of cells can be different, provided that their number is a multiple of two, for example, 2, 4, 8, 10, 20, etc. Cells are required to form a set of resistances with predefined states.

[0048] The reference voltage source (106) includes an integrator (1065) (similar to the integrator (105)), the output of which increases during the readout simultaneously with the signal at the output of the integrator (105) of the readout circuit (100). The switches (10621) and (10631) of the voltage reference circuit in FIG. 6 operate in a similar way to keys (1011) and (1021) shown in schemes (10) and (11) (Fig. 2 and Fig. 3).

[0049] FIG. 8 shows a diagram of a reference voltage source (116) containing groups of switches (1062) and (1063), which operate similarly to the groups of switches (1071), (1081) of the reference voltage source circuit in circuit (12) (Fig. 4). As well as for the reference voltage source (106), the source (116) contains memory cells that form a set of resistances with predetermined states.

[0050] FIG. 9 shows a typical circuit of an integrator, in particular integrators of a readout circuit (105) and a reference voltage source integrator (1065). The integrator includes an operational amplifier (op-amp), resistor R, capacitor C, and switches for resetting the standby state. The rate of rise of the voltage at the output of the integrator is determined by the value of the resistance, the capacitor and the magnitude of the input signal.

[0051] FIG. 10 shows a timing diagram of the signals at the output of the readout circuit integrators (105) and the reference voltage source circuit integrator (1065). At the beginning of the readout period, the reset signal is removed from the integrators (105), (1065), and the voltage at the output of the integrators begins to increase monotonically with time and in proportion to the input signal. The signal at the output of the reference voltage source is proportional to the averaged value of the resistances of the cells (1064) in the state "1" and "0", therefore, for the entire reading period, the value of the voltage at the output of the reference voltage source (106) is the same value from the signal of the readout circuit (100) independently from the state of the read cell (110). At the end of the sampling period, a strobe control signal is applied to the comparator (107) of the readout circuit (100). According to the strobe control signal, the comparator (107) amplifies the difference of the input signals to the logical states "1" and "0".

[0052] The presented description of the claimed solution discloses only preferred examples of its implementation and should not be construed as limiting other, particular examples of its implementation, not going beyond the scope of legal protection, which are obvious to a specialist in the relevant field of technology.

Claims (30)

1. A method for reading the state of a spin transfer magnetoresistive memory cell STT-MRAM, which consists in generating a read signal V _rd during T _rd reading a memory cell, and the signal voltage V _rd in a given time range T ₂ periodically falls below a predetermined stabilization pulse value V _lo , and in the predetermined time range, T ₁ reaches a V _hi value that is higher than V _lo . 2. The method according to claim 1, characterized in that the signal level V _lo differs from the level V _hi by at least 1.25 times. 3. The method according to claim 1, characterized in that V _lo is a zero signal. 4. The method according to claim 1, characterized in that the duration of the residence time of the readout signal V _rd below the value of the stabilization pulse V _{lo is} approximately equal to the thermal relaxation time T ₀ . 5. The method according to claim 1, characterized in that T1 is from 0.1 ns to 20 ns. 6. The method according to claim 1, characterized in that T2 is between 0.3 ns and 10 ns. 7. The method according to claim 1, characterized in that the signal level V _lo has the opposite sign from the sign of V _hi and differs in amplitude. 8. The system for reading the state of a cell of magnetoresistive memory with spin transfer STT-MRAM, containing - readable memory cell connected to the first and second keys, providing switching of the sign of influence on the readable cell; - generator of control signal by the sign of influence on the read cell, providing the formation of control signals that determine the period of reading the memory cell with a changing sign of the influence; - a voltage source connected to the first switch; - an integrator connected to the second key; - a source of reference voltage, providing the formation of the readout voltage; - a comparator that compares the voltage accumulated on the integrator with the voltage of the reference voltage source; moreover - the generator of the control signal by the sign of action on the read cell provides the formation of control signals that form the period of reading the memory cell with a changing sign of the action by switching the first and second keys on the signal of the current affecting the memory cell, at which the read signal V _rd is generated, thus, that the signal V _rd in a given time range T ₂ periodically falls below a set value of the stabilization pulse V _lo , and in a given time range T ₁ reaches a value of V _hi that is higher than V _lo . 9. The system according to claim 8, characterized in that it additionally contains a shunt key that transfers the state of the upper contact of the cell to a zero level. 10. The system of claim. 8, characterized in that the reference voltage source contains a group of keys that ensure the switching of the sign of the action on the read cell, and memory cells that form a set of resistances with predetermined states. 11. The system for reading the state of the cell of magnetoresistive memory with spin transfer STT-MRAM, containing - readable memory cell connected to the first and second groups of keys, providing switching of the sign of influence on the readout cell; - generator of control signal by the sign of influence on the read cell, providing the formation of control signals that determine the period of reading the memory cell with a changing sign of the influence; - a voltage source connected to the first group of switches; - an integrator connected to the second group of keys; - a source of reference voltage, providing the formation of the readout voltage; - a comparator that compares the voltage accumulated on the integrator with the voltage of the reference voltage source; moreover - the generator of the control signal by the sign of action on the read cell provides the formation of control signals that form the period of reading the memory cell with a changing sign of the action due to switching the first and second groups of keys on the signal of the current affecting the memory cell, at which the read signal V _rd is generated, thus that the signal V _rd in the predetermined time range T ₂ periodically falls below the predetermined value of the stabilization pulse V _lo , and in the predetermined time range T ₁ reaches a value V _hi that is higher than the value V _lo . 12. The system of claim 11, wherein each key group contains four keys. 13. The system according to claim 12, characterized in that in each of the groups of keys, one pair of keys closes on a high state of the control signal, and the second pair on a low. 14. The system according to claim 11, characterized in that the reference voltage source contains two groups of keys that switch the sign of the action on the read cell, and memory cells that form a set of resistances with predetermined states.

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