RU2738446C1 - Synchronizing network device for wireless communication, in particular network terminal, in wireless network - Google Patents

Abstract

FIELD: electrical communication engineering.

SUBSTANCE: invention relates to communication. To this end, the following steps are provided: receiving a synchronization frame and determining a timestamp T_AP; using the IWC clock contained in the IWC, generating a time stamp T_B, which determines the time of receiving the synchronization frame; potential change is created on IWC port, which is synchronization event; using IWC clock generates time stamp T_SE, determining moment of synchronization event; and the SED determines the synchronization event by analysing the time duration of changing the potential of the IWC port and generates the time mark T_S using the synchronized time signal T_CCG, where T_S determines the same synchronization event time as T_SE. T_AP, T_B, T_SE and T_S, determined by processing one or more synchronization event frames, are then used to synchronize the synchronized time signal T_CCG generated by the CCG system with the time signal of the master device.

EFFECT: technical result is simple synchronization of network nodes in a wireless network, implemented on low-cost hardware, while maintaining accurate synchronization.

21 cl, 7 dwg

Description

The invention relates to a technology for synchronizing a network device for wireless communication, in particular a network terminal, in a wireless network, where the network device has an Integrated Wireless Chip (IWC), a Synchronization Event Detector (SED) for detecting synchronization events , a Controllable Clock Generator (CCG) for generating a synchronized time signal T _CCG, and a clock control device (SCD) for controlling the synchronization process of a network device. In addition, the invention relates to network devices using the technology as well as a wireless network with such network devices.

Time-Sensitive Networking (TSN) is currently the most promising vendor-independent and time-dependent communication standard for industrial applications. The term TSN denotes a set of standards that the Time-Sensitive Networking Task Group, which is part of the TEE 802.1 working group, is working on. TSN includes two main components: first, the IEEE 1588 submicrosecond precision device synchronization protocol, and second, a number of technologies to provide high priority QoS (Quality of Service) scheduling of notifications. Given its benefits, TSN can be expected to replace most of today's industrial fieldbuses in the long term and offer a unified communication model for a wide range of industrial equipment. Since purely wired data networks have limitations in terms of density per unit area, connections of moving parts, and miniaturization of nodes, hybrid solutions based on wired backbones and multiple islands with wireless hubs are taken into account.

Research and development over the past decade has shown that wireless communication can be applied in a variety of industrial automation applications, including robotics, Smart Grids, large-format sensor networks, etc., even in very complex electromagnetic environments. Even in this environment, IEEE 802.11 wireless communication can achieve bandwidth comparable to wired Ethernet networks, particularly when the next generation IEEE 802.11ax (Wi-Fi 6) standards are applied. This makes the IEEE 802.11 standards promising candidates for wireless extensions to TSN.

However, the timing of multiple devices and the scheduling of high-priority messages on a wireless network can be difficult: on a wired network, each node has a dedicated cable as its own transmission medium. In contrast, devices on a wireless network share the same communication medium and control access through the Distributed Coordination Function (DCF), an IEEE 802.11 standards mechanism that regulates non-deterministic access by multiple subscribers to a corresponding wireless network. However, this kind of access can lead to unpredictable latency. The use of less popular frequency bands and channel retuning methods can partially solve such problems. But this approach tends to lead to high custom hardware costs and does not scale well for larger networks.

Mass collisions and retransmissions can be avoided by scheduling messages using specific communication protocols and an application layer at the IEEE802.11 PHY layer. Such approaches can significantly reduce the likelihood of collisions and improve real-time performance. Most scheduling techniques, with the exception of token-based scheduling, require separate timing mechanisms that are much more sensitive to packet loss than other traffic. Ethernet TSN uses IEEE 1588 based time synchronization, the accuracy of which is guaranteed by accurate time stamping in both directions of frames provided by TSN switches with stable transmission delay.

For industrial applications, budget IWCs are often used, which can be part of, for example, a computer. This kind of IWC is typically implemented as a System-on-a-Chip or SoC and can include multiple processors, A / D converter modules and D / A converter modules, modulators and demodulators, and amplifiers. to send and receive a wireless signal. The SoC integrates both PHY and MAC modules into one microchip. This ensures economical and energy efficient implementation. But at the same time, direct access of developers to the PHY module becomes impossible, which does not allow obtaining sufficiently accurate time stamps for sent and received frames, which are necessary for accurate synchronization. Accessing the PHY to timestamp given frames via external interfaces creates such large phase fluctuations that such timestamps are unlikely to be suitable for synchronization. In this case, the influence on the phase fluctuations, in particular, is exerted by the load of the network and the processor.

The solution to this problem is described in [A.M. Romanov et al. "High Precision Synchronization between Commercial WiFi- ICs and External Device", 2019 16 ^{th Workshop on Positioning, Navigation and Communications} (WPNC), pp. 1-6]. Here, a special method and corresponding hardware are indicated, which allows synchronizing the clock contained in the budget, half-duplex IEEE 802.11-IWC (Integrated Wireless Chip) technology with an external clock implemented in special external hardware. External hardware can be implemented in particular (mostly) with an FPGA (Programmable Logic Integrated Circuit). For synchronization, a high-precision IWC output function is used, which is also externally accessible. For synchronization, extremely short frames (Ultra Short Frames, USF) are generated. The USF start time is assigned both the time stamp generated by the IWC clock and the time stamp generated by the external hardware clock. These pairs of timestamp values, each identifying the same point in time (but using two different clocks), are then used to synchronize both clocks using a special algorithm.

The authors of this technology recognized that most of the commercial budget IWCs have a special characteristic that can be used for synchronization: such IWCs are designed to transmit data in half duplex. Obviously, the input port of the receiving and recording unit, where the IWC receives an analog receive signal in the receive mode, goes to zero potential in the transmit mode, probably in order to avoid receiving its own transmit signal. In receive mode, this port has a potential other than zero, for example 600 mV. The authors have found that the switching processes triggered when changing from the receive mode to the transmit mode and vice versa are performed with high accuracy. Thus, each of these switching processes can be used as a synchronization event, which is time-stamped by the IWC clock and external clock. This time stamp is generated by the IWC system with a hardware feature built into it, in which these time stamps are provided only to synchronize the IWC systems with each other, but not to synchronize the IWC system with external hardware of the same device. Thus, high-precision synchronization of the external clock with the clock of the IWC circuit can be realized.

It should be noted here that, in this specification, a time stamp is a time value, which may, for example, correspond to a counter with N digits. Thus, such a time stamp can represent a time period, the zero point of which corresponds to the moment when the corresponding counter is started. For example, a time value contained in a timestamp generated by a master device, such as a wireless access point (AP), may be set to zero during device initialization. Hereinafter, the term "timestamp", depending on the context, is understood either as the corresponding time value, or as the corresponding sequence of bits contained in the corresponding frame, for example, in a beacon frame transmitted in the IEEE 802.11 network.

Modern wireless networks or wireless networking devices have the disadvantage that when using inexpensive IWCs that do not allow external access to the timers or clocks contained in them, it is impossible to achieve sufficient accuracy when synchronized with the time signal generated by the central clock. ...

Based on this prior art, the invention is based on the problem of providing a synchronization technology for devices acting as network nodes in a wireless network, which is simple and can be implemented on economical hardware and provides sufficient synchronization accuracy. In addition, the invention is based on the problem of providing a simple and economical mechanism in the form of a network device, allowing to implement this method, as well as a wireless network with such network devices.

The invention solves these problems with the features of claims 1 and 14, as well as 17.

The invention is based on the fact that many inexpensive IWCs, especially those that operate in half duplex, have a port that, upon receipt of a sync frame, can create a potential change that can be used as a sync event or a sync event. The potential change, which is a sync event, can be the start or end edge of a pulse generated on the corresponding port in response to receiving a sync frame. Of course, this can be a positive impulse, i.e. pulse with a positive (rising) leading edge and a negative (falling) falling edge.

The corresponding port on which synchronization events are generated may be an IWC port specially provided for this purpose. In this case, in particular, each change in potential, i.e. each rising or falling edge can also be a synchronization event in which a potential change occurs in response to receiving a synchronization frame without returning to its original potential after a predetermined time.

However, a suitable IWC port that is already available for other purposes can also be used as the port on which synchronization events are generated. In this case, a sync event can be generated by generating a signal on this port that is different from all other signals generated on this port for other corresponding purposes. In particular, in this case, in response to the receipt of the synchronization frame, a pulse of a predetermined duration can be generated, the duration of which is different from the duration of all other pulses generated as signals on this port. The start or end edge of a pulse can again be used as a sync event.

For example, in many low-cost half-duplex IWCs, the potential change occurs when changing from transmit to receive mode (and vice versa) at the input port of the receive path, which is fed an analog, possibly amplified wireless input signal. For example, if in receive mode the port has a potential of 600 mV, then in transmit mode the potential of the port will change to about 0 V to avoid receiving the signal transmitted by the IWC itself.

Instead of this signal receiving port, for example, the coexistence port of the IWC interface can also be used to generate synchronization events. This interface coexistence port may be a port that has a first potential (eg, high) when the IWC is active (ie, transmitting or receiving) and a second potential when the IWC is inactive. The signal from this port of the coexistence interface is fed to another wireless transmitting and receiving device, such as a Bluetooth communication device, and this signal is used to determine which of the two communication devices can communicate (using the same frequency band).

In all such cases, a change in potential, in particular a pulse, can be generated at the corresponding port in response to the reception of a synchronization frame, a change in potential or a predetermined edge of the pulse, is interpreted as a synchronization event. As explained above, in cases where this port is also used for other purposes, a pulse can be generated with a time duration that is different from the time duration of all other pulses generated or output in this port.

Potential changes, each of which is a synchronization event, can be generated by high-level or low-level software, either by the appropriate IWC hardware in response to receiving the synchronization frame, or by an appropriate external IWC control. In any case, it must be ensured that the potential changes, which are synchronization events, have a sufficiently short switching time, i.e. correspondingly steep switching edge. In addition, it must be ensured that these potential changes are generated with a sufficiently low jigger. In this way, a change in port potential can be detected and used as a synchronization event to synchronize the external clock associated with the IWC with the time signal of the master, which is fed to the network device by transmitting synchronization frames.

The master time signal can, for example, be generated by a master clock contained in a wireless access point. In this case, the transmission of the time signal of the master device to the synchronized network device is carried out using the time stamps _TAP , which are contained in the synchronization frames. The time stamp _TAP can be generated, for example, to determine when the start or end of the synchronization frame is transmitted.

Upon receipt of the sync frame, the IWC creates a time stamp T _B using the clock contained in the IWC, where the time stamp T _B defines the same time within the sync frame as the time stamp T _AP , that is, for example, the end of the sync frame (in in this case, the moment of receiving the end of the synchronization frame). If the travel time between the device, such as the access point sending the synchronization frame, and the synchronized network device is known, the two time stamps T _AP and T _B can be used to synchronize the IWC's internal clock and the master clock. Since the distance of network devices from the corresponding access point in a wireless network is usually small, the signal transit time during synchronization can be neglected, since the signal transit time is an order of magnitude less than the admissible synchronization error. Since the signal is transmitted at the speed of light, even at a distance of 100 m between the access point and the corresponding network device, the transit time will be only 333 ns, which is much less than the usually required maximum synchronization error, for example, 2 μs. However, the purpose of the present invention is not to synchronize the master clock with the internal clock of the IWC system, but to synchronize the master clock with the CCG, since at least inexpensive TWCs do not have an interface through which the internal clock of the system can be accessed. IWC (i.e. an access that can basically be done without a jigger and without significant delay). For this reason, according to the invention, a synchronization event is generated by the IWC, which is assigned both the time stamp T _SE generated by the IWC's internal clock and the time stamp T _S generated by the CCG. Thus, the time stamps T _AP , T _B , T _SE and T _S can be used to synchronize the CCG with the master clock according to the invention.

A synchronization event is generated by switching the IWC to transmit mode and sending a synchronization event frame with a characteristic time duration, while a potential change is created on the IWC port for the duration of the synchronization event frame. The synchronization event itself can be the start or end edge of the potential change of the determining port. In this case, the IWC timestamp assigns the time stamp T _{SE to the} synchronization event. At the same time, the synchronization event is detected by the SED and the SED assigns the time stamp T _S to the synchronization event using the CCG time signal. This allows, after each acquisition of a synchronization frame, to define a set of 4 time _stamps T _AP , T _B , T _SE and T _S that will be used to synchronize the CCG-generated synchronized time signal T _CCG to the main time signal.

Thus, the invention provides high accuracy in synchronizing network devices with the time signal generated by the central clock, even if the network devices contain inexpensive IWCs that do not allow external access to the timers or clocks contained therein.

According to one embodiment of the invention, the characteristic frame timing of the synchronization event is chosen to be different from all the usual transmission frame timing that can occur during communication between a network device and a subsequent network device, and that by means of an SED analysis of the potential change timing the IWC port detects a synchronization event when the time duration of the potential change is within the specified range. This provides a relatively easy way to create unique sync events. Such timing events can be determined by estimating the time interval between two changes in the potential of the corresponding IWC port that occur when switching from receive mode to transmit mode and vice versa. Only if this time interval matches the specified time interval for a sync event frame, the start or end edge is recognized as a sync event.

According to the following embodiment, a synchronization event frame is generated immediately after receiving a synchronization frame or after a predetermined latency time, which is less than or equal to the minimum latency that can occur during communication between the network device and the next network device between receiving and sending frames, and the creation of the frame Synchronization events are primarily triggered by a function implemented in hardware and / or software in IWC.

This makes it possible for all network devices to synchronize simultaneously on the corresponding wireless on the _TAP sync _timestamp if the _TAP sync _timestamp is transmitted in a network sync frame, for example Beacon in the IEEE 802.11 transmission protocol. In this case, all network devices will simultaneously switch to transmit mode to generate the corresponding synchronization event. Although a corresponding overlap of the corresponding transmitted signals from the network devices occurs during the transmission time of the respective synchronization event frames, this is irrelevant since the synchronization event frames are not used for communication. To this end, it is possible to implement the creation of a synchronization event frame by hardware and / or software within the IWC, rather than as a result of a software command that the SCD sends to the IWC. Indeed, this requires the processing of the corresponding commands in the SCD in real time and their transmission to the IWC system. While this would be possible in principle, it would require appropriate real-time SCD performance, which would be contrary to the principle of economy in implementing SCD.

According to one embodiment of the invention, a synchronized time signal generated by the CCG, T _{CCG is} generated using the ratio

where T _SRC is the CCG timer output signal, k is the synchronization factor, and T _md is the phase shift, and the synchronization factor k and the phase shift T _{md are} determined by SCD from the time stamps T _AP , T _B , T _SE and T _S.

In accordance with a preferred embodiment of the invention, the new value for the phase shift T _SRC can be determined cyclically, while in the current cycle the new value for the phase shift T _md is determined by addition, taking into account the sign of the previous value of the phase shift T _md and the synchronization error ε determined in the current cycle , which is determined in accordance with the relation

The sync factor k can be constant during the sync phase. The sync factor k can be determined in a previously performed startup phase, as described below, and can also be stored in ROM. ROM can be provided for this purpose in both the CCG and SCD.

This means that in the synchronization phase, for each synchronization frame, a tuple of 4 timestamp elements T _AP , T _B , T _SE and T _S can be determined, from which the phase shift T _md can be determined and loaded into the CCG.

According to a further embodiment, false alarm filtering can be performed on detected timing events, preferably using time stamps T _B and T _SE , or T _BSE = T _SE -T _B and timing error ε, where time stamps T _AP , T _B , The T _SE and T _S assigned to a sync event are used for sync only if the sync event is not defined as a false trigger. For example, for the timing error ε and / or the time difference T _BSE (i.e., the time between the receipt of the synchronization frame and the synchronization event (measured with the IWC clock), upper and lower bounds can be specified, respectively, with the synchronization event and the corresponding a set of 4 elements of time stamps are used for synchronization only if these boundaries are met.

According to one embodiment of the invention, the synchronization phase is maintained (ie, the synchronization phase steps described above are performed) until a positive termination criterion is met. Once the termination criterion is met, the synchronization phase can be changed to a pre-synchronization phase. To this end, the synchronization error ε can be determined for successive synchronization events (and possibly recognized as valid through filtering) and loaded into the CCG as a value for T _md until the number N _{ps of} consecutive values of the synchronization error ε exceeds the threshold value ε _lim ... When the number N _{ps of} consecutive values of the synchronization error ε exceeds the threshold value ε _lim , the preliminary synchronization phase starts.

If a positive termination criterion is not reached within a given time or by a given number of attempts to reach the number N _sync , then the pre-sync phase can be moved to the start phase after the next form of execution.

In accordance with a preferred embodiment of the invention, the synchronization factor k is determined at the start-up stage, in which steps (a), (c) and (e) are performed for a plurality of synchronization frames according to Formula 1. Of course, false alarm filtering of detected events can also be performed here. synchronization, which may require steps (b) and (d) of Formula 1, i.e. steps for determining the time stamps T _B and T _SE , if these parameters are used for filtering. To determine the synchronization coefficient k, one or more individual values k _{i of} the synchronization coefficient can be determined in accordance with the ratio

и

where the subscripts [i] and [j] respectively denote different synchronization events and the corresponding time stamps T _AP and T _S , preferably j = i-1, i.e. for synchronization events that are triggered in response to successive synchronization frames, it is preferable to determine time differences

and

It should be noted here that it is not necessary to use every sync frame received from the IWC to generate a sync event frame, and therefore to generate a sync event. Rather, only selected sync frames, eg, only every n-th sync frame, can be used to generate or reuse a sync event or sync event frame. Alternatively, although a sync event frame may be generated in response to each sync frame received, only selected sync event frames, eg, only every nth sync event frame, can be used to generate or reuse a sync event.

To determine the synchronization coefficient k, the number N _{k of} individual values of k _i can be averaged. In this case, the individual values of k _i to be averaged can be selected using one or more filtering conditions.

According to an embodiment, individual values k _i are determined from time stamps for pairs of consecutive synchronization events, primarily for a number N _s of synchronization events, preferably successive synchronization events or synchronization events, which are respectively distributed over a constant number of intermediate synchronization events. Individual k _i values are used for further computation only if they were selected using one or more filter conditions, and the sync factor k is only computed if the default minimum number of selected individual k _i values is reached. Otherwise, it is better to reject the total number N _s of synchronization events and their associated time stamps T _AP and T _S to determine the synchronization factor k.

The value of the sync factor k determined during the startup phase can be saved and loaded into the CCG when the network device is activated or reset. Due to this, the relatively complex determination of the sync factor k does not require redetermination each time the network device is activated or reset.

The network device according to the invention can be implemented with an FPGA and an IWC computer, for example a single board computer running a non-real-time OS. FPGA can implement both CCG and SED. Potential matching may also be required between the corresponding IWC port and the FPGA port implementing the SED input port. Of course, potential matching can be realized with the appropriate additional hardware.

It should be clearly noted that the hardware to implement the IWC, SED, SCD and CCG functionality as well as other functionality can be distributed or even combined in any way. For example, the hardware for implementing the SED can also be combined with the hardware for the IWC in an integrated circuit, such as a SoC. The IWC port on which the sync event frame is output will in this case be implemented as an internal port of the corresponding IC.

Further embodiments of the invention follow from the dependent claims.

The invention is described in more detail below with reference to the exemplary embodiment shown in the drawing. The drawing shows the following:

FIG. 1 is a block diagram of the main components of a network device that implements the synchronization method in accordance with the invention, necessary for understanding the invention;

FIG. 2 is a diagram showing the general sequence of the various phases of the synchronization method;

FIG. 3 is a block diagram of the start-up phase of the implementation of the method in accordance with the invention;

FIG. 4 is a block diagram of a pre-synchronization phase of an embodiment of a method according to the invention;

FIG. 5 is a block diagram of a synchronization phase of an embodiment of a method according to the invention; and

FIG. 6 is a histogram of the synchronization error 6, measured during the experiment in a network consisting of an access point and two synchronized network devices, where in FIG. 6a shows a histogram for the first device and FIG. 6b is a histogram for the second device.

FIG. 1 is a block diagram of the components of a network device 100, which will not be described in further detail below, and with which the synchronization method in accordance with the present invention may be implemented. The network device 100 includes an IWC system 102 by which the network device wirelessly connects to an access point, which will not be described in further detail below. As a wireless transmission protocol, for example, standards according to IEEE 802.11 are taken into account. Since certain applications running on network devices require synchronization with the central clock or central time determined by the central clock, the access point may send synchronization frames at specific intervals to synchronize network devices on the wireless network it defines, and each frame will contain a tag time T _AP , generated by the central clock. For example, a central clock can be provided at the access point itself, or at any other network device that does not need to be on a corresponding wireless network. Within the IEEE 802.11 protocols, synchronization frames are called Beacons.

In addition, the network device 100 includes an SED 104 for detecting synchronization events as well as a CCG 106 for generating a synchronized time signal T _CCG and an SCD 108 that controls the synchronization method. As shown in FIG. 1, SED 104 and CCG 106 can be integrated, for example, as FPGA 110.

The received signal, which is generated by the access point, is supplied to the IWC 102 using an antenna, not shown in detail. Likewise, the IWC 102 generates a transmit signal containing data that is generated locally in the network device 100. The IWC system also contains an internal IWC clock that generates a time signal but is not directly accessible via the IWC 102 interface to other components within the network device. The IWC's internal clock, in particular, is used to generate time stamps when communicating wirelessly with other network devices. In particular, the economical IWC 102 systems do not have a dedicated port that receives a signal containing timing events that match the assigned time stamps generated by the IWC's internal clock sufficiently and without phase fluctuations.

However, the inventors have found that even an economical IWC 102 operating in half duplex also provides the ability to generate an S _sync signal that contains synchronization events that can be used to synchronize an external clock, namely in the form of CCG 106. This is an IWC port 102, which is fed with an analogue receive signal directly from an antenna or through a suitable amplifier. It was found that when switching from the IWC reception mode to the transmission mode, this port switches from the first potential, which can be, for example, 600 mV, to the second, which can be, in particular, zero potential. These switching processes are carried out with high precision and can be time-stamped by such IWCs, i.e. such an IWC 102 system is capable of generating a time stamp that identifies the corresponding switching time where the time signal of the IWC's internal clock is used.

To generate synchronization events in the form of corresponding potential changes, you can also use the coexistence port of the IWC 102 interface, which has the first potential if the IWC is active (i.e., transmission and / or reception is allowed), and the second potential if the IWC is inactive and, therefore, another wireless device is allowed.

It should be noted that the invention is not limited to such IWC embodiments in which the port for the analog input signal is “misused”. IWCs can also be used, where a corresponding separate port is provided to which a signal is output containing synchronization events, each of which is generated in response to the receipt of a synchronization frame.

In the embodiment shown in FIG. 1, this port of the IWC 102 is denoted with a reference symbol 102a and is connected to the input port of the SED 104. Hardware, not covered in detail, may also be provided for potential matching or potential separation. The structure of the SED 104 makes it possible to detect synchronization events contained in the synchronization signal S _sync supplied to it, ie, in particular, the switching processes generated as a result of switching the IWC 102 from the receive mode to the transmit mode and vice versa.

The time signal T _CCG generated by CCG 106 is provided to SED 104. As mentioned above, SED 104 and CCG 106 can be implemented in the same integrated circuit 110, such as an FPGA, excluding the potential adjustment hardware if necessary. The SED can use the T _CCG signal supplied to it to generate an appropriate time stamp when a sync event is detected.

The SCD 108 receives the corresponding time stamps from the SED 104 and is designed to control and perform all actions of the synchronization method described below. The SCD 108 can be structured like a conventional computer, and in particular like a simple single board computer. This system controls the CCG 106 so that the generated synchronized time signal T _CCG matches the setpoints determined by the SCD 108. For this, the SCD 108 loads the appropriate timing parameters into the CCG 106 (see below). The SCD 108 can also provide a T _CCG sync signal so that it can also use the synchronized time signal and, if necessary, make it available to appropriate applications, in particular software. In addition, the SCD system 108 is also connected to the IWC 102 and can request from it the time stamps generated by the IWC 102 using the internal clock of the IWC or data received from the IWC 102, in particular the time stamps contained in the synchronization frames generated by the signal time of the master. The system can also control the IWC 102 appropriately, for example, to cause the IWC to generate a timing event frame with a specific duration.

The following explains various variants of the synchronization method according to the invention. In particular, this method can reduce the requirements for the capabilities of the SCD 108 in real time. This is achieved by porting all critical operations to the IWC 102 firmware or to the SED 104 or CCG 106 hardware or firmware, while the SED and CCG can also be implemented as cost-effective FPGAs.

For example, the time signal of the master or corresponding time stamps _TAP may be transmitted using the time synchronization function defined in IEEE 802.11 as the time synchronization source of the master. In this case, the time stamps T _AP are transmitted in synchronization frames called Beacons. However, the invention also allows the use of separately generated sync frames using any transmission protocol.

The purpose of the method is to synchronize several wireless nodes, i.e. multiple wireless network devices 100 connected to the access point. To do this, each network device 110 must include the hardware infrastructure shown in FIG. one.

Every time the IWC 102 receives a valid sync frame, such as a beacon frame, it generates a sync event on port 102a. In this case, the synchronization time stamp _TAP , contained in the synchronization frame, is preserved. In addition, the IWC 102 generates and stores a time stamp T _B , which determines the reception of the synchronization frame, and a time stamp T _SE , which determines the timing of the synchronization event. The time stamps T _B and T _{SE are} respectively generated by the time signal of the IWC's internal clock.

As explained above, the synchronization event may occur on the edge of a signal (eg, voltage) that is supplied to the SED 104 via port 102a. SED 104 detects every synchronization event. It may consist of the sync edge of the sync signal, S _sync , which is generated when the sync frame is sent to port 102a. A sync event can be generated either by a (negative) sync edge generated by the IWC 102 transition from receive mode to transmit mode (i.e., the start of a sync event frame sent by IWC 102), or (a positive sync edge generated by the IWC 102 transition from transmit mode to receive mode (i.e., by the end of the frame of the sync event sent by the IWC 102).

However, a sync event can be generated in any other way on the appropriate IWC port (see explanations above).

However, the SED 104 must not only determine if there is a corresponding sync edge in the S _sync signal, but also whether it is actually a sync edge generated by the sync event frame. For this purpose, as already explained above, each frame of the synchronization event has a characteristic duration, which usually does not exist, or, at least, which is extremely rare in standard data transmission, taking into account the corresponding transmission protocol. For example, the duration of a sync event frame may be shorter than the duration of all regular frames. Therefore, the SED 104 must also have the ability to determine the intervals between the sync edges that are generated by the corresponding frames (whether they are frames during standard data transmission or frames of sync events). Since a transmitting frame in the sync signal S _{sync is} initiated, for example, by a falling sync edge and terminated by a rising sync edge, the SED 104 can determine transmit frames, which, due to their inherent duration, can only be sync event frames. From a sync event frame detected in this way, the SED 104 can determine a corresponding sync event, such as a falling or rising edge (ie, a start or end edge) in the sync signal S _sync as a _sync event.

A sync event frame for generating a sync event may be generated by the IWC 102 at any time after the sync frame is received. This can be controlled either autonomously by the hardware and / or firmware of the IWC 102, or upon request of the appropriate SCD 108 command after the IWC 102 informs the SCD 108 that it has received a sync frame. In particular, the transmission of a synchronization event frame can be performed in the same way as the transmission of any conventional frame, for example a data frame, subject to the set values of the corresponding transmission protocol. In the case of using protocols according to various IEEE 802.11 standards, IWC 102 will in particular check whether the corresponding channel is free and can thus transmit a frame without causing collisions.

However, this method generates additional traffic that is not required for data transmission as such. This is because the sync event frame is mainly only used to generate the corresponding sync event in the sync signal S _sync . Therefore, the sync event frame usually does not contain any payload. True, this is also possible. But in this case, a duration must be chosen for the sync event frame into which the payload can be intelligently integrated. At the same time, the duration of frames of synchronization events should still be characteristic. Although not excluded, in practice, depending on the protocol used, this can only be realized with increasing complexity in determining the frame length.

For this reason, it is easier to determine a value for frames of a synchronization event that will be less than the duration of all other frames of the corresponding protocol. Accordingly, such frames are unlikely to have enough space for a full-fledged data transfer. For example, if you are using the IEEE 802.11 standard protocols, you can choose 12 bytes for sync event frames at a data rate of 6 Mbps. This gives a time duration of about 16 μs for a sync event frame, which must be determined by the SED 104.

In another embodiment, the network device may generate a sync event frame immediately or after a predetermined short period of time after receiving the sync frame. The generation can be done by IWC hardware or software so that the timing of the frame triggering event can be captured with sufficient accuracy. The start time is preferably determined so that the interval between the end of the received synchronization frame and the beginning of the synchronization event frame is less than or equal to the minimum waiting time between the reception and transmission of the frame by the network device, depending on the used transmission protocol. In this way, it can be ensured that after receiving a synchronization frame, which is transmitted as a broadcast frame and therefore received and processed by all network devices, all network devices respond by transmitting a synchronization event frame. Although this results in an overlap of the corresponding sync event frames on the corresponding transmission channel, this is not a disadvantage, since in this case the sync event frames do not contain any payload, but only serve to generate a sync event on port 102a of the IWC 102. Thus, the traffic generated by the required sending of frames of synchronization events, or the corresponding loading of the transmission channel, can be minimized.

It should be noted here again that synchronization events can be generated on other ports of the IWC 102 in the form of corresponding potential changes. You only need to make sure that the potential change, which can be interpreted as a sync event, can be generated with sufficiently low jitter in response to a sync frame, or that the timing of the sync event can be captured with a sufficiently accurate time stamp T _SE .

In all embodiments, the SED 104 generates a time stamp T _S upon detection of a synchronization event using a synchronized or synchronized time signal T _CCG that is generated by the CCG.

The SCD periodically reads all time stamps T _AP , T _B , T _SE , T _S from the IWC 102 and SED 104 and, using the default timing algorithm, determines the timing parameters, which are then transmitted to the CCG 106 and which the CCG uses to synchronize the time signal T _CCG . In this case, the time signal T _CCG can be determined using the following ratio:

Here k is the synchronization factor and T _md is the phase shift. T _SRC denotes the flow rate of the precision timer contained in CCG 104. Precision timer actuation, i.e. the triggering of the T _SRC can be, for example, 1/256 µs, which is about two decimal orders of magnitude less than the synchronization error desired in practice.

As shown in FIG. 2, the synchronization algorithm implemented in SCD can be composed of three phases: a trigger phase, a pre-synchronization phase, and a synchronization phase.

At the start-up stage, only the value of the synchronization factor k is initially determined, by which it is necessary to multiply the value of the precision timer in the CCG 104 in order to calculate the synchronized or synchronized time signal T _CCG without taking into account the phase shift T _md . If it is not possible to determine the synchronization factor k using a suitable algorithm, then the determination can be repeated as often as required. Of course, a termination criterion can also be provided here, so that after a predetermined number of attempts to determine the coefficient k, an error message is generated and the starting phase is interrupted. If the value of the synchronization coefficient k has been successfully determined, then the system goes to the preliminary synchronization phase.

The starting phase can be skipped if the actual value of the synchronization factor k determined in the earlier executed starting phase has been stored in memory, preferably in ROM. When starting up, you can first check if there is a valid value for the synchronization factor k. In this case, it can be retrieved from memory and loaded into CCG 106. The pre-synchronization phase can then proceed immediately.

In the pre-synchronization step, the phase shift T _md can be determined using a suitable algorithm. The phase shift T _md can be determined recursively until the synchronization error ε for a given number of N _sn cycles falls below the limit value ε _lim . In this case, in the pre-synchronization phase, partial filtering (or a specific primary filter algorithm) can be used to determine the phase shift T _md . When the above condition for the completion of the pre-synchronization phase is reached, a transition to the synchronization phase occurs.

In the synchronization phase, the value for the phase shift T _{md is} also determined cyclically. In this case, full filtering (or a specific second filtering algorithm) can be applied. When the termination criterion is met, a transition occurs from the synchronization phase to the pre-synchronization phase. For example, filtering of false alarms for certain values by phase shift T _md can be performed as termination criterion. When N _ps false positives are detected, the system enters the pre-synchronization phase. Also move from the pre-sync phase to the start phase if the criterion for transition to the sync phase is not met after a specified number of cycles or a specified period of time.

The individual process steps in the start-up phase are explained below using the exemplary flow chart shown in FIG. 3. At the beginning of the start-up phase, it is first checked whether useful values of the synchronization factor k and the phase shift T _{md are available} from previous synchronization processes. They can be stored in the corresponding ROM, in SCD 108 or CCG 106. With such useful values, the pre-synchronization phase can be started immediately. The useful values for k and T _md are loaded from ROM, into CCG 106. If the ROM is in CCG 106, then you only need to check if there is such a valid pair of values that can be used for the pre-synchronization phase.

At the beginning of the start-up phase, the synchronization factor is first set to k = 1 (at the same time, the phase shift T _md = 0 can be set to use this initial value during the transition to the pre-synchronization phase; however, this initial value setting for T _md can be performed in the phase pre-synchronization). Every time the SCD 108 receives a new time stamp T _S from the SED 104, the SCD 108 also reads the latest set of (associated) time stamps T _AP , T _B, and T _SE from the IWC 102. Values for T _B and T _SE that are not directly are required to calculate the sync factor k, can be used to filter out false positives to eliminate invalid or unacceptable sync events. To filter false alarms, for example, a time difference condition is set

which should run for a valid sync event. This time difference is equal to the time interval between the reception of the synchronization frame (for example, the end of the synchronization frame can be defined as the defining moment) and the time at which the corresponding synchronization event is generated (for example, the end of the transmitted synchronization event frame). This time interval is equal to the duration of the sync event frame plus the waiting time between the reception of the sync frame and the transmission of the sync event frame. Taking into account the switching characteristics of the IWC system or the resulting finite slope of the synchronization edges in the synchronization signal S _sync , the lower and upper limit values of T _{BSE, low} , T _{BSE, high} can be determined for T _BSE

If the frame duration of a sync event is, for example, 40 μs and the latency is 10 μs, then, including the time to switch the IWC from transmit to receive mode, for example 2-3 μs for a valid sync event or valid 4-tuples timestamps T _AP , T _B , T _SE and T _{S the} following partial filtering condition can be defined: 52 μs≤T _BSE ≤53 μs The above upper and lower limits T _BSE must of course be adapted depending on the respective switching characteristics IWC, specified latency and timing of synchronization frames.

In accordance with this method, in order to determine the synchronization factor k in the start-up phase, a predetermined number N _{s of} valid synchronization frames are first determined and stored. In this case, there is no need to use synchronization frames that follow directly one after the other. Instead, SCD 108 may indicate that only selected sync frames are processed. For example, only every n-th sync frame can be used. This can reduce the processing speed of the SCD 108, so less expensive hardware can be used.

In the next step, SCD 108 determines a set of k _i values for the synchronization coefficient k from among N _s pairs of time _stamp values T _S [i] and T _AP [i] (1≤i≤N _S ) in accordance with the following relationship:

Here, the indices i and j generally denote any timing events to be evaluated or their associated time stamps T _S [i], T _S [j] and T _AP [i], T _AP [j]. However, it is desirable to use consecutive pairs of sync events or timestamps so that j = i-1 is effective. The k _i values thus determined for the synchronization factor k can be filtered again to improve the accuracy of the method. For example, it is possible to disregard all values of k _i for which the difference between the corresponding synchronization ratio k _i and the average value of all synchronization coefficients k _i is less than 50% of the maximum value of all differences formed by the synchronization ratio k _i and the average value of all synchronization coefficients k _i . This is an empirical way to reduce the number of peaks by numerical differentiation according to equation (2) above. The final value of the synchronization factor k can be calculated as the average of all the synchronization factors k _i , which are determined to be applicable after the empirical filtering described above.

If the number of values k _i for the synchronization coefficient remaining after this filtering method is less than a predetermined minimum number N _{k, lim} , the embodiment according to FIG. 3 stipulates that a completely new set of synchronization frames N _s must be defined, i. E. the method for determining the synchronization coefficient k will be restarted.

Of course, any other filtering method can be used to improve accuracy. You can also completely eliminate this filtering. Of course, this also applies to partial filtering of time stamps using equations (2) and (3).

After determining the value of the sync factor k, it is loaded into CCG 106 and can be additionally stored in ROM, so that the value of the sync factor k will already be available at the beginning of the next startup phase, which is started, for example, when the network device 100 is turned on or initialized or reset. Then there is a transition to the pre-synchronization phase.

It should be noted here that the sync factor k can of course be determined by any other linear interpolation method between T _SRC and T _AP .

Then it is necessary to determine the phase shift T _md in the pre-synchronization phase. FIG. 4 shows an embodiment of the pre-synchronization method. In this embodiment, a corresponding set of 4 time stamp elements T _AP , T _B , T _SE and T _{S is} cyclically determined for the consecutive or selected received synchronization frames. In this case, partial filtering (filtering of false positives), of course, can be performed using equations (2) and (3). At the next stage, the synchronization error ε is calculated in accordance with the ratio

Then, the previously valid phase shift value T _{md is} corrected for the timing error ε, i.e. a certain synchronization error ε is added to the previously valid value for the phase shift T _md (taking into account the sign). For this, the phase shift value T _{ms is} loaded into CCG 106. Of course, the SCD 108 can also calculate a new value for the phase shift T _md and then load the new calculated value into the CCG 106 if the CCG cannot do such a calculation on its own.

Then, at the next stage, it is checked whether the current calculated value of the synchronization error ε is less than the threshold value ε _lim . In this case, the corresponding counter is incremented by one. Otherwise, the counter is reset (i.e., set to zero). If the counter after the increment exceeds the specified N _sync threshold, the pre-sync phase is exited and transitioned to the sync phase. If the counter is reset as a result of exceeding the permissible threshold value ε _lim for the synchronization error, then within the termination criterion it is possible to check the necessity of transition from the pre-synchronization phase to the start phase, since the applicable value for the phase shift T _md cannot be determined. To do this, you can check, for example, how often the counter is reset in successive cycles. If the corresponding set maximum value is exceeded, you can proceed to the start-up phase.

In the synchronization phase, which is described below based on the embodiment of FIG. 5, the phase shift value T _{md is} also determined cyclically for consecutive or selected received sync frames. For this, a corresponding 4-tuple of timestamps T _AP , T _B , T _SE and T _{S is} determined. In this case, partial filtering (filtering of false positives) can be performed using equations (2) and (3) to exclude invalid synchronization events. In the next step, the synchronization error ε is calculated in accordance with equation (3). At the next stage, it is checked whether the newly determined value of the synchronization error ε is less than the threshold value ε _lim . In this case, the corresponding counter is incremented by one. If this condition is met, then the synchronization error ε or its corresponding new value for the phase shift T _md (see the description of the preliminary synchronization phase) is loaded into the CCG 106, and the counter is reset (of course, set to zero at the beginning of the method in the synchronization phase). Then another loop is executed. If the synchronization error ε is not less than the predetermined threshold value ε _lim , the counter will increment and the next cycle will be executed if the value of the increment counter T is not greater than the predetermined threshold value N _lim . Otherwise, it goes to the preliminary synchronization phase.

In the synchronization phase, in addition to the partial filtering described above, equations (2) and (3) can also be used to filter the values determined for the synchronization error ε. For filtering, for example, you can set the upper and lower limit values ε _high , ε _low for the timing error ε. Then only those synchronization events or associated time stamps T _AP , T _B , T _SE , T _S are used for which the synchronization error ε is applied, which meets the following conditions:

The limits can be selected according to the duration of the transmitted synchronization event frames. In practice, it was found that good results are achieved if the value of the synchronization error ε is less than or equal to the frame duration of the synchronization event, i.e.

where Δt _SEF is the duration of the synchronization event frame. This condition can be used, in particular, to exclude those frames that are incorrectly recognized as synchronization event frames and have a duration similar to the duration of the synchronization event frames, and are transmitted after the synchronization event frame. By using partial filtering of false alarms according to equations (2) and (3) and additional filtering of false alarms according to equation (7), it is possible to achieve sufficiently high synchronization accuracy on hardware with relatively low computing power, which, accordingly, will be economical.

Since equation (5) with equation (2) is written as

when calculating the timing error ε for T _BSE , a constant value can also be used, in particular the value obtained, for example, by averaging the T _BSE values over several cycles (eg 100). This is, of course, independent of the fact that the T _BSE value determined in each cycle can be used for partial filtering according to equations (2) and (3). Since the time stamp of the IWC 102 is relatively inaccurate or generated with a short response time of, for example, 1 µs, the accuracy can be significantly improved.

To implement and test the method described above, the inventors conducted the following experiment: Two wireless nodes or network devices were manufactured, each of which consisted of a Raspberry PI 3B embedded computer with an integrated IWC Cypress CYW43438. Each IWC was connected to an FPGA board through a high speed comparator. The first of the two networking devices used the Digilent Nexys 4 DDR development board to implement SED and CCG. This board was equipped with a Xilinx Artyx-7 FPGA operating at 50 MHz. The second of the network devices included the Lattice iCEstick debug board for the same purpose. In this debug board, a budget FPGA iCE40HXl is installed, operating at a frequency of 48 MHz. Using different FPGAs with different clock generators shows that good results are achieved using the synchronization method described above, rather than using different clock frequencies or phase shifts. As an access point, we used a budget NETGEAR N150 point, which also generated beacon frames for synchronization. A sync error was recorded on both network devices. The tests were carried out under computational load conditions on Raspberry PI 3B computer processors and under a loaded (partly occupied) communication channel.

FIG. 6 shows histograms of synchronization error ε (equation 8) for both network devices (FIG. 6a - Network device 1; FIG. 6b - Network device 2) obtained with this setting and the method described above. The measurements were taken with a CPU load of 90% on each network device. For testing, the network was loaded with additional data transmitted at a rate of 15 Mbps (UDP transmission) from the first to the second network device. For the parameter T _BSE from equation (8), a value of 53 µs was used, which was previously determined using appropriate measurements and averaging. The test took more than 12 hours. The standard deviation of the distribution in FIG. 6 was less than 500 ns. Thus, it can be shown that with the method according to the invention it is possible to achieve high synchronization accuracy even with very cheap hardware and without using a real-time operating system.

Legend List 100 Network Device

102 IWC (Integrated Wirless Circuit: integrated wireless communication chip)

102a port

104 SEC (Synchronizationsevent-Detektoreinrichtung: synchronization event detector)

106 CCG (steuerbarer Clock-Generator; Controllable Clock Generator: controlled time signal generator)

108 SCD (Synchronizationssteuereinrichtung; Synchronization Control Device: synchronization control device)

110 FPGA (Programmable Logic Integrated Circuit)

ε synchronization error

ε _lim threshold value for synchronization error

ε _{high is the} upper limit of ε

ε _{low the} lower bound of the value ε

k sync factor

T _AP sync time stamp

T _B timestamp (receive sync frame)

T _SE time stamp (create sync frame)

T _S time stamp (sync frame detection)

T _SRC precision timer value in CCG 104

T _CCG time (time signal) CCG to

T _md phase shift

Δt _SEF time duration of synchronization frame

N _S number of synchronization frames to determine k

N _{k, lim is the} minimum number of synchronization frames for determining k

N _sync number of cycles in the pre-sync phase

N _{ps is the} number of cycles in the synchronization phase.

Claims (44)

1. A method of synchronizing a network device for wireless communication, in particular a network terminal, in a wireless network, where the network device has an integrated wireless communication chip (IWC), a synchronization event detector (SED) for detecting synchronization events, a controlled time signal generator (CCG) for generating a synchronized time signal T _CCG and a synchronization control device (SCD) for controlling the synchronization process of the network device, while in the synchronization phase in the network device, the following method steps are performed: (a) receiving the synchronization frame and detecting the synchronization timestamp T _AP , which is contained in the synchronization frame and which was generated by another network device, in particular an access point, using the time signal from the master, (b) generating a time stamp T _B using the IWC clock contained in the TWC scheme, which determines the time of reception of the synchronization frame, (c) generating a synchronization event by the IWC in which a potential change at the IWC port representing a synchronization event is generated in response to the receipt of a synchronization frame, (d) generating a time stamp T _SE using the IWC clock that determines the timing of the synchronization event, (e) detecting a synchronization event by the SED by estimating the duration of the change in potential of the IWC port and generating a time stamp T _S by the SED using the synchronized time signal T _CCG , the time stamp T _S identifying the same instant of the synchronization event as the time stamp T _SE , and (f) using the time stamps T _AP , T _B , T _SE and T _S obtained by processing one or more frames of synchronization events in accordance with steps (a) - (d) to synchronize the synchronized time signal T _CCG generated by the CCG system, with the time signal of the master. 2. The method according to claim 1, characterized in that (a) the IWC port on which the potential change is generated, representing the synchronization event, is the input port of the IWC receiving part, to which an analog, possibly amplified, wireless input signal is applied, (b) in which the IWC port has a first potential in the IWC transmit mode and a second potential in the IWC receive mode, and (c) in which the IWC is controlled to generate a sync event after receiving a sync event frame in receive mode so as to generate a pulse with a duration of a specific characteristic time period on the IWC port, the start or end edge of which is defined as a sync event. 3. The method according to claim 1, characterized in that (a) the IWC port on which the potential change representing the synchronization event is generated is the coexistance port of the IWC interface, which is provided to connect to the corresponding port of another wireless communication device, (b) this IWC port in IWC active mode, in which the IWC can send and / or receive the first potential, and in the IWC passive mode, in which the IWC cannot send and / or receive one, has a second potential, and (c) in which the IWC is controlled to generate a synchronization event by transitioning from active mode to passive mode after receiving a synchronization event frame in receive mode so as to generate a pulse with a duration of a specific characteristic time period on the IWC port, the start or stop edge of which defined as a sync event. 4. The method according to one of paragraphs. 2 or 3, characterized in that the characteristic time period is chosen so that it differs from the pulse width of all other pulses that may occur in the port in question, and that by the SED, the start or end edge of one pulse generated by the port is then detected as a synchronization event if the pulse width matches a representative time period or is within a predefined tolerance. 5. The method according to one of paragraphs. 1, 2, or 4, characterized in that a synchronization event frame is generated immediately after receiving a synchronization frame or after a specified timeout that is less than or equal to the minimum timeout that can occur during communication between a network device and the next network device between receiving and sending frames, with the creation of a sync event frame primarily triggered by a function implemented in hardware and / or software in the IWC. 6. A method according to one of the preceding claims, characterized in that the synchronized time signal T _CCG generated by the CCG is generated using the ratio

where T _SRC is the CCG timer output, k is the timing factor, a T _md is the phase shift, and the timing factor k and the phase shift T _{md are} determined by SCD from the time stamps T _AP , T _B , T _SE, and T _S. 7. The method according to claim 6, characterized in that the new value for the phase shift T _md can be determined cyclically, while in the current cycle the new value for the phase shift T _md is determined by addition, taking into account the sign of the previous value of the phase shift T _md and the synchronization error ε defined in the current cycle, which is determined in accordance with the ratio

8. A method according to claim 7, characterized in that false alarm filtering can be performed on detected synchronization events, preferably using time stamps T _B and T _SE , wherein the time stamps T _AP , T _B , T _SE and T _S , assigned to a sync event are used for sync only if the sync event is not defined as a false trigger. 9. The method according to one of paragraphs. 7 or 8, characterized in that the synchronization phase is retained and certain values for T _md are loaded into the CCG until a negative termination criterion is met, and that after the first negative termination criterion for the synchronization phase is reached, a transition to the preliminary synchronization phase occurs, moreover, the synchronization error ε is determined for successive and, if necessary, selected synchronization events and is loaded into the CCG as a value for T _md until the number of consecutive values of the synchronization error ε exceeding the threshold value ε _lim exceeds N _ps . 10. A method according to claim 9, characterized in that the preliminary synchronization phase is maintained until a positive termination criterion is met, and that after the termination criterion is reached, it can be performed to enter the synchronization phase, and as a positive termination criterion, the error The timing ε is preferably determined and loaded into the CCG as a value for T _md until the number of consecutive ε timing error values exceeding the threshold ε _lim exceeds N _sync . 11. The method according to claim 10, characterized in that there is a transition from the pre-synchronization phase to the start phase if the positive termination criterion is not reached within a predetermined time or by a predetermined number of attempts to reach the number N _sync . 12. The method according to one of paragraphs. from 6 to 11, characterized in that the synchronization factor k is determined at the start-up stage, at which steps (a), (c) and (e) are performed for a plurality of synchronization frames according to formula 1, and to determine the synchronization factor k, one or several individual values k _{i of} the synchronization factor in accordance with the ratio

where the subscripts [i] and [j] respectively denote different synchronization events and the corresponding time stamps T _AP and T _S , preferably j = i-1. 13. The method according to claim 12, characterized in that to determine the synchronization coefficient k, the number N _{k of} individual values of the synchronization coefficient k _{i is} determined. 14. The method according to claim 13, characterized in that the determined individual values of the synchronization coefficient k _i are selected using one or more filtering conditions. 15. The method according to one of paragraphs. 12, 13 or 14, characterized in that the individual values of k _{i are} determined from time stamps for pairs of successive synchronization events, primarily for the number N _s of synchronization events, preferably successive synchronization events or synchronization events, which are respectively distributed over a constant number of intermediate events synchronization. Individual k _i values are used for further computation only if they were selected using one or more filtering conditions, and the synchronization coefficient k is computed only if the default minimum number of selected individual k _i values is reached, otherwise case, it is better to reject the total number N _s of synchronization events and their associated time stamps T _AP and T _S to determine the synchronization factor k. 16. A method according to one of the preceding claims, characterized in that the value of the synchronization factor is stored and loaded into the CCG upon activation and reset of the network device. 17. A network device, in particular a network terminal, for wireless communication in a wireless network (a) with an integrated wireless communication chip (IWC) that has a port on which a potential change can be generated in response to receiving a sync frame that represents a sync event and that includes the IWC's internal clock, (b) with a controlled clock generator (CCG) to generate a synchronized time signal T _CCG , which can be used for further operation of the network device (c) with a sync event detector (SED) for detecting sync events, which has an input port to which the potential of the IWC port where sync events are generated, or a potential dependent therefrom, is applied, and to which the time signal of a controlled sync generator is applied, and (d) with a timing control device (SCD) to control the timing operation of a network device that is connected to the SED, with an IWC connected to the CCG, characterized by f) that SED, IWC, CCG have a structure that allows the method to be carried out in accordance with any of the above formulas. 18. The network device of claim 17, wherein the IWC port on which the potential change representing timing events is generated is an IWC input port for providing an analog wireless receive signal. 19. The network device of claim 17, wherein the IWC port on which the potential change representing synchronization events is generated is a coexistence port of the IWC interface, which, while in IWC active mode, in which the IWC sends and / or receives, has the first potential, and in passive IWC mode, in which the IWC cannot send and / or receive, has a second potential. 20. Network device according to one of paragraphs. from 17 to 19, characterized by the fact that SED and CCG are implemented using PILS, and SCD - using a computer on which, in particular, a non-operating real-time system is running. 21. Wireless network with an access point and two or more network devices in accordance with any of paragraphs. 17 to 20, in which the access point transmits sync frames as broadcast frames.

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