RU2727710C1 - Apparatus for spatially separated reception of digital signals of systems of mobile radio communication - Google Patents

Abstract

FIELD: communication equipment.SUBSTANCE: invention relates to communication engineering and can be used in radio communication systems with mobile and stationary objects using digital types of signal modulation. Systems which adaptively tracking in real time after variation of delay, phase and signal-to-noise ratio and providing optimum summation of digital signals are used. System is based on several coupled PLL loops and an interpolating filter as a delay line. Signal processing includes the following actions, such as delay time alignment in channels based on synchronization of symbol (clock) frequencies, obtaining signal phase coherence based on carrier frequency synchronization and signal weighting based on the signal-to-noise ratio estimate result.EFFECT: technical result consists in improvement of noise immunity of operation of complex space-diversity reception in conditions of fast changes of parameters of signals of delays, phases and signal-to-noise ratio in receiving channels with obtaining of resultant signal-to-noise ratio.1 cl, 1 dwg

Description

The invention relates to radio communication systems with mobile and stationary objects using digital types of signal modulation and can be used in devices of a space-diversity reception complex performing optimal signal-to-noise ratio.

There are several known methods for optimal coherent addition:

- summation based on phase synchronization of input signals by controlling the phases of the heterodyne frequencies of the converters;

- summation based on phase synchronization of input signals using phase-locked loop (PLL) of solution-controlled detectors;

- summation based on maximizing the cross-correlation coefficient of signals used to align delays and phases.

For some technical solutions close to the claimed invention are proposed in patents (patent RU No. 478442 from 25.07.75 IPC Н04В 7/12; patent RU No. 792597 dated 30.12.80 IPC Н04В 7/00) coherent addition devices. A common disadvantage of these devices based on phase synchronization of input signals is the lack of time alignment and tracking of signal delays, which is necessary not only in conditions of movement of objects of reception and transmission, but also in conditions of fluctuations in delays and phases caused by high transmission and modulation frequencies.

In the first device (patent RU No. 478442 from 25.07.75 IPC Н04В 7/12), three coupled PLL loops are used, which equalize the phase shift of signals in the receiving channels. The disadvantage of this device is that in this device, along with the absence of time alignment, there is no signal weighting and the purpose of this device is coherent summation of signals only with analog types of angular modulation.

In the second device (patent RU No. 792597 from 30.12.80 IPC Н04В 7/00), a signal regeneration circuit is used to remove modulation and obtain a carrier wave. It is known that for complete removal of modulation, the impulse response of the modulator signal must be matched to the characteristic of the input signal. Failure to fulfill this condition leads to the fact that the carrier oscillations will contain modulation residues in the form of phase noise that cannot be eliminated by narrowband filtering. In the circuit of this device, there is no matched filtering of the regeneration signal. This factor will reduce the noise immunity of the device, especially when working with high-speed multi-position digital signals.

Separately, we note the invention (patent RU No. 2003158 from 15.11.93 IPC G04F 10/06), which proposes a method for determining the time delay of one pseudo-random signal relative to another. In a device that implements this method for determining the time delay, signals are demodulated and the phase difference between the symbol and carrier frequencies is estimated. Based on this estimate of the phase difference, the delay time is calculated.

In the optimal coherent combining method, based on maximizing the cross-correlation coefficient of signals, the correlation coefficient is calculated using a simple iterative algorithm, and discrete time reports of the signals are taken for the calculation. It is on the basis of this method in the source Comm # 11-2011 (Kuchumov A.A., Pryputin B.C., Nikolaev A.V). FPGA implementation of the optimal addition algorithm for broadband communication systems, T-Comm # 11-2011, pp. 55-57) an optimal addition algorithm is proposed. Note that the device for coherent optimal combining, created on the basis of this algorithm, generally meets the requirements for mobile radio communication systems using digital types of modulation. Therefore, we will take this device as a prototype corresponding to the functional purpose. In the described algorithm for optimal addition, a significant drawback is the lack of search for the maximum of the cross-correlation coefficient in the phase of the carrier frequencies of the signals. The difference in the phases of the carrier frequencies of the time-aligned signals is caused by different phase shifts of the signals delayed in the processing paths, which are formed, including after frequency conversion. The calculation of the algorithm requires certain computational resources and processing time, which leads to a decrease in performance, and this is the case that discrete reports of signals are taken to calculate the correlation coefficient, and interpolation of a continuous signal is required to increase the calculation accuracy.

These factors will reduce the gain of the optimal combination of signals with multi-position modes of modulation in mobile communication systems.

The technical result of the claimed invention is an increase in the noise immunity of the operation of the space-diversity reception complex under conditions of rapid changes in the parameters of delay signals, phases and signal-to-noise ratio in the receiving channels.

This result is achieved by using several circuits that adaptively track changes in delay, phase, signal-to-noise ratio in real time and provide optimal summation of signals with digital modulation modes under conditions of rapid parameter changes.

Signal processing includes the following actions:

- equalization of the time delays in the channels due to the synchronization of the symbol (clock) modulation frequencies;

- formation of the coherence of the signal phases based on the synchronization of the carrier frequencies;

- formation of signal weights based on the result of evaluating the signal-to-noise ratio.

Equalization is carried out in an adaptively controlled delay line included in the PLL loop. The delay line is a tunable interpolation filter controlled by the phase difference error signal of the symbol frequencies.

The block diagram of the device is shown in Fig. 1.

The device contains two channels of reception and demodulation (KPD-1, KPD-2) and a weight addition circuit (SHS). All basic processing is carried out in digital complex form.

The operation of the adaptive time alignment circuit in the receiving channels is based on the principle of phase synchronization of the signal modulation symbol frequencies. The circuit is based on several coupled PLL loops, one of which includes an adaptively controlled delay line. The delay line is a tunable interpolation filter controlled by a PLL that monitors the phase difference of the symbol frequencies.

The formation of the coherence of the phases of the carrier frequencies is based on the idea of mutual synchronization of the PLL loops operating in the recovery circuits of the carrier frequency of the signal. Phase control is carried out using a controlled phase shifter made in the form of a frequency converter with a complex multiplier and a numerical controlled generator.

In accordance with the diagram of FIG. 1 the input signals of the space-diversity reception of the first channel KPD-1 and the second channel KPD-2 are fed to the adjustable amplifiers 1.1; 2.1 automatic gain control (AGC) circuits, which according to the control signals of the decision circuit detectors (DSS) 1.10; 2.10 carry out automatic gain control. The signals amplified in this way come to the inputs of the analog-to-digital converter (ADC) 1.2; 2.2. The output signal of the ADC of the first channel 1.2 is fed to the controlled delay line 1.3, then to the quadrature formation circuit (FC) 1.4. In this scheme, the complex signal transferred to the near-zero frequency is subjected to matched filtering.

The ADC output signal of the second channel 2.2 is fed to an adjustable discrete time delay line 2.3, designed to eliminate the excessive signal delay between the channels, and then to the FC 2.4 circuit. In this scheme, the complex signal transferred to the near-zero frequency is subjected to matched filtering.

The signal of the first channel from the output of the quadrature shaping circuit 1.4 is fed to the frequency conversion unit, which consists of a complex phase shaping multiplier (FFP) 1.6 and a numerical controlled generator (PCG) 1.5. In KPFF 1.6, the phase of the signal is controlled; for this, the minimum frequency offset is introduced into the generator (PG) 1.5, which makes it possible to set the coherent phase using the PLL loop.

In the second channel, a similar unit for converting the frequency of the KPFF 2.6 and the Chug 2.5 is introduced to preserve the identity of the delay and frequency offset parameters, while there is no phase control.

From the outputs of nodes 1.6; 2.6 signals are applied to detecting complex multipliers (DCT) 1.7; 2.7, then to the carrier frequency recovery circuits (CHR) 1.8; 2.8.

In the second channel, carrier recovery circuit 2.8 synchronizes the signal to the carrier frequency, i.e. removes the frequency offset by affecting the error signal on the CHG 2.12 and DCT 2.7.

In the first channel, the SVN 1.8 error signal is fed to the frequency conversion unit to control the phase of the PMG 1.5 and the CPFF 1.6. Thus, the carrier phase value of the first channel is synchronized with the carrier phase of the second channel.

An analytical expression for phase synchronization might look like this:

where: S _i1 , S _q1 - quadrature components of the first channel signal;

S _i2 , S _q2 - quadrature components of the second channel signal;

M _i1 , M _q1 - modulation components of the second channel signal;

M _i2 , M _q2 - modulation components of the second channel signal;

w is the cyclic frequency of the carrier wave;

p ₁ , p ₂ - phase of the carrier frequency.

From the outputs of the detecting complex multipliers 1.7; 2.7 signals are fed to clock synchronization circuits (CTC) 1.9; 2.9.

In the second channel in the generator circuit 2.11 with the help of STS 2.9, the clock frequency of the synchronous symbol frequency of the signal is formed, then at frequencies that are multiples of this frequency, in the ADC 1.2; 2.2, the input signals are sampled and all further signal processing in the device.

In the first channel, using the PLL loop, adaptive control of the signal delay time is implemented, the condition for this is the following - the duration of the delay time should not exceed 0.5 times the duration of the signal modulation clock frequency:

where: Dt is the duration of the delay time;

F _sr - signal modulation clock frequency.

The clock synchronization circuit (CTC) of the first channel 1.9 separates the phase difference between the sample rate data and the symbol frequency of the signal. The phase difference signal is fed to a controllable delay line 1.3, made on the basis of an interpolation bandpass filter. The interpolation filter shifts the first channel signal in time by creating new data in the sample samples. Thus, the new sample rate data is synchronized with a multiple of the symbol rate. And since the sampling frequency is simultaneously synchronous to a multiple of the symbol frequency of the second channel, it follows from this that the phase equality of the symbol frequencies is achieved, which, in turn, means the alignment of the time delays of the signals in the receive channels.

An analytical expression for the alignment of signal time delays in interpolation filters is as follows:

S _out1 = S _out2 ,

where: S _out1 - output signal of the first channel filter;

S _out2 - output signal of the second channel filter;

dt - discrete time value;

S ₁ (dt _i ) - input discrete values of the first channel signal;

S ₂ (dt _i ) ^_ input discrete values of the second channel signal;

X (dt _i ) - discrete values of the impulse response;

N is the "length" of the discrete impulse response;

Dt - signal delay time.

Time-synchronous, phase-coherent undetected signals of the first and second channels from the outputs of complex multipliers KPFF 1.6; 2.6 go to controlled attenuators 3.1; 3.2 SHS schemes. Attenuators function - setting optimal signal weights. Next, the weighted signals are fed to the adder 3.3 of the CBC circuit, then the complex sum signal is fed to the output of the device. Automatic control of attenuators is carried out according to the commands of decision schemes 1.10; 2.10 estimating the signal-to-noise ratio in the receiving channels. Signals for schemes SPR 1.10; 2.10 come from complex multipliers DCT 1.7; 2.7. The composition of the schemes of the SPR 1.10; 2.10 includes an adaptive intersymbol distortion corrector, an AGC detector and a signal-to-noise ratio estimation detector.

Claims (1)

A device for space-diversity reception of signals with digital modes of modulation, used in radio communication systems with mobile and stationary objects, performing optimal coherent signal addition, containing two reception and demodulation channels (KPD-1, KPD-2) and a weight addition circuit (SHS), a channel (KPD-2), consisting of a series-connected adjustable amplifier, an analog-to-digital converter (ADC), a discrete delay line, a quadrature generator, a complex multiplier for forming a phase and a detecting complex multiplier; the detecting complex multiplier is connected in parallel to the carrier recovery circuit (CBR), clock synchronization circuit (CTS) and to the decision circuit (DSS); a fixed signal of a numerical controlled generator is connected to the other input of the complex multiplier of phase formation, the output of the SVN is connected to a numerical controllable carrier generator, which is connected to other inputs of the detecting complex multipliers of the second and first channels; the output of the STS is connected to the control input of the sampling frequency generator, the output of which is connected to the ADCs of the second and first channels, the CTS circuit is connected to an adjustable amplifier and a controllable CBC attenuator, the input of which is connected to the output of the complex multiplier of the phase formation, and the output to the adder of the CBC circuit, channel ( KPD-1), consisting of a series-connected adjustable amplifier, ADC, interpolation filter, quadrature shaper, phase formation complex multiplier and a detecting complex multiplier, which is connected in parallel to the SVN, STS and SPR circuits; the output of the SVN is connected to a numerical controlled phase generator, which is connected to the other input of the complex multiplier of the phase formation; the STS output is connected to the interpolation filter control input; the output of the SPR circuit is connected to the control inputs of the adjustable amplifier and the controlled attenuator of the SHS, the input of which is connected to the output of the complex multiplier for the formation of the phase, and the output to the adder of the SHS circuit, characterized in that an interpolation filter is used as the controlled delay line, adaptively equalizing the delay time of the signals in real time on the signal of the phase synchronization error of the modulation symbol frequencies.

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