RU2718579C1 - Fast pseudorandom interleaver - Google Patents

Abstract

FIELD: physics.SUBSTANCE: invention relates to radio engineering and can be used in digital transmitters and receivers. Device comprises a memory area arranged in form of two identical K-bit shift registers with parallel output of information and with three output states, corresponding outputs of registers are combined into K common leads, which in pseudorandom order, according to rearrangement of leads, are connected to data inputs of multiplexer. Device also has a summing counter with a translation unit K, which counts two logic AND elements on the input bit frequency, a flip-flop operating in a counting mode.EFFECT: technical result is reduction of delay and simplification of device implementation.1 cl, 6 dwg

Description

The invention relates to the field of radio engineering, in particular to the class of block data interleavers and can be used as part of digital transmitters and receivers.

A block interleaver provides for the recording of an incoming block (frame) of K data elements in a buffer and performs the same permutation of each block independently of other blocks. The block size K determines the interleaver period.

The operation of a traditional block interleaver is described in [1] on pages 486-488.

A pseudo-random interleaver is a device that takes blocks of K elements and rearranges them in a pseudo-random manner. A feature of pseudo-random interleavers is the complexity of the hardware implementation of the process of generating permutations [2].

A known pseudo-random interleaver of turbo code using linear congruent sequences described in [3].

The turbo-code pseudo-random interleaver comprises means for writing data elements sequentially in rows into a matrix of bit storage cells, means for pseudo-random reordering of data elements in each row in a matrix of bit storage cells in accordance with the recursion of a linear congruent sequence, and means for reading data elements sequentially in columns from the matrix bit storage cells.

The disadvantages of this device are the narrow scope (only one type of pseudo-random interleaving) and the high computational complexity of the control device (address generator).

In turn, a pseudo-random permutation of any kind can be written to read-only memory (ROM), and then use this permutation to address the interleaver memory.

So, the closest to the claimed invention in technical essence and the achieved result is a pseudo-random interleaver, the device of which is described in [4] on pages 327-330 and in fig. 8.11 (p. 328) shows its structural diagram.

Channel elements are sequentially written into the memory of this interleaver. After recording the entire block, these elements are rearranged by reading, carried out using pseudo-random permutation recorded in the address ROM. For the correct operation of the device, two random access memory devices (RAMs) operating in antiphase are necessary: while writing to one of the RAMs, reading from the other occurs. After completing this process, the roles of the two RAMs change.

The disadvantage of this device is due to the access time when reading from the ROM and represents a delay in the appearance of valid data at the output of the ROM regarding the supply of input address signals.

The problem solved by the invention is the improvement of the pseudo-random interleaver in the presence of restrictions on the delay time of the device.

The technical result from the use of the invention is to reduce the delay of the pseudo-random interleaver and simplify its implementation on a programmable logic integrated circuit (FPGA).

This result is achieved in that the fast pseudo-random interleaver includes a memory region with the ability to receive input bits in series, organized in the form of two shift registers with parallel output of information operating in antiphase, while the corresponding outputs of these shift registers are combined into common outputs, which are in pseudo-random order connected to the information inputs of the multiplexer, while the address inputs of the multiplexer are connected to the outputs of the totalizing counter, counting at a frequency of dying input bits.

Common features of the prototype and the proposed device are the use of a memory area with the ability to receive input bits in series, organized in the form of two memory devices operating in antiphase and a control system for selecting bits from the memory area.

Distinctive features of the proposed device from the prototype are:

1. Instead of RAM, shift registers with parallel output of information are used.

2. Instead of storing the pseudo-random permutation in the address ROM, a pseudo-random order of connecting the outputs of the shift registers to the information inputs of the multiplexer is used.

3. The role of the control system for the selection of bits from the memory area is performed by a summing counter that counts the input bits at the frequency of arrival.

Thanks to the new set of essential features, the technical result - reducing the delay of the pseudo-random interleaver and simplifying its implementation on the FPGA, is achieved by:

1. The lack of ROM, and hence the read time from the ROM.

2. Quick access to values in shift registers, which, as a rule, is several times faster than access to RAM cells.

3. Minimization of the control system for the selection of bits from the memory to the totalizing counter.

The analysis of the level of existing technology made it possible to establish that there are no analogues that are characterized by a combination of features identical to all the features of the claimed technical solution. This indicates compliance of the claimed device with the patentability condition of "novelty." The search results for known solutions in this and related fields of technology in order to identify features that match the features of the claimed object that are different from the prototype showed that they do not follow explicitly from the prior art. The prior art also did not reveal the popularity of the impact provided by the essential features of the claimed invention transformations to achieve the specified technical result. Therefore, the claimed invention meets the condition of patentability "inventive step".

выходам суммирующего счетчика 1 с модулем пересчета K (то есть по mod K), считающего на частоте поступления входных битов, причем последний n-ый выход счетчика 1 подключен к входу триггера 2, работающего в счетном режиме, прямой выход триггера 2 подключен к входу EO регистра сдвига 5 и к нижнему входу двухвходового логического элемента (ЛЭ) «И» 3, а инверсный выход триггера 2 подключен к входу EO регистра сдвига 6 и к нижнему входу ЛЭ «И» 4, при этом верхние входы ЛЭ «И» 3 и ЛЭ «И» 4 предназначены для тактовых импульсов. Регистры сдвига, мультиплексор, счетчик, триггер могут быть выполнены любым общеизвестным способом. Вместо триггера можно использовать последний выход счетчика по mod 2K.Functional diagram of the proposed device is presented in FIG. 1. Fast pseudo-random interleaver contains a memory region organized in the form of two identical K-bit shift registers 5, 6 with parallel output of information and with three output states, while the corresponding outputs of these registers are combined among themselves in K common conclusions 7; where DS (Data Serial) - serial data input; C (Clock) - clock input; EO (Enable Output) is the output enable input, that is, the presence of a logical unit (“Log. 1”) at the input of EO transfers the DO (Data Output) outputs of the register to a high-resistance third state. The pins 7 in pseudo-random order, according to the permutation of pins 8, are connected to the information inputs DI (Data Input) of the multiplexer 9, the address inputs of which A (Address) are connected to

the outputs of the totalizing counter 1 with the conversion module K (that is, according to mod K), which counts the input bits at the frequency of arrival, the last n-th output of the counter 1 is connected to the input of the trigger 2 operating in the counting mode, the direct output of the trigger 2 is connected to the input EO the shift register 5 and to the lower input of the two-input logic element (LE) "I" 3, and the inverse output of the trigger 2 is connected to the input EO of the shift register 6 and to the lower input of the LE "I" 4, while the upper inputs of the LE "I" 3 and LE "I" 4 are designed for clock pulses. The shift registers, multiplexer, counter, trigger can be performed by any well-known method. Instead of a trigger, you can use the last counter output in mod 2K.

выводов 8, подключены к информационным входам DI мультиплексора 9. Счетчик 1 в i-ый момент времени генерирует на адресных входах A мультиплексора 9 значение

. При этом мультиплексор 9 переводит бит данных с

-ого выхода DO регистра 5 на свой выход DO (выход устройства). Через каждые K тактовых импульсов триггер 2 меняет выходное состояние и переключает режим работы соответствующего регистра на противоположный, то есть регистр сдвига 5 и регистр сдвига 6 меняются ролями.Pseudo-random interleaver works as follows. The data bits arriving at the input of the pseudo-random interleaver are fed to the inputs of the DS shift registers 5, 6. Synchronously with the data bits, clock pulses are received at the counter input 1 and the upper inputs of the LE "I" 3, 4. On the direct output of trigger 2 is a logical zero (log. "0"), then at the input of the EO shift register 5 log. "0", and at the input of the EO shift register 6 log. “1”, that is, shift register 5 is in read mode, shift register 6 is in write mode and clock pulses do not arrive at input C of shift register 5 (log. “0” at the lower input of LE “3”) and are fed to input C of shift register 6 (log. "1" at the lower input of the LE "I" 4). With the arrival of a new clock pulse, the next bit of data is written to shift register 6, and the data written to shift register 6 earlier is shifted one bit to the right. The outputs of the shift register DO 6 are disconnected (in the third state) from the common terminals 7, at the same time, the outputs of the shift register DO 5 in a pseudo-random order, according to the permutation

pins 8, connected to the information inputs DI of multiplexer 9. Counter 1 at the i-th moment of time generates a value at address inputs A of multiplexer 9

. In this case, the multiplexer 9 translates the data bit from

5th DO output of register 5 to its DO output (device output). After every K clock pulses, trigger 2 changes the output state and switches the operating mode of the corresponding register to the opposite, that is, shift register 5 and shift register 6 change roles.

. Прямая задержка между перемежителем и деперемежителем равна 2K, необходимая память составляет 4 K-разрядных регистра сдвига, а именно: 2 K-разрядных регистра сдвига для перемежителя и 2 K-разрядных регистра сдвига для деперемежителя. Следовательно, предлагаемое устройство по времени задержки и сложности реализации не сильно отличается от традиционного блочного перемежителя.In the receiver, the de-interleaver is implemented similarly, with the difference that the corresponding outputs are connected to the information inputs of the multiplexer in the order according to the reverse permutation

. The direct delay between the interleaver and the de-interleaver is 2K, the required memory is 4 K-bit shift registers, namely: 2 K-bit shift registers for the interleaver and 2 K-bit shift registers for the deinterleaver. Therefore, the proposed device in terms of delay time and complexity of implementation is not much different from the traditional block interleaver.

For pseudo-random interleaver, any permutation can be used. For example, in turbo-like codes, S-random permutation [5], as well as its modifications [6, 7] and combinations [8], have excellent characteristics.

с учетом ограничения:A permutation of an S-random interleaver is a random permutation generated by a random number sensor in a range

subject to restrictions:

, то

,

if a

then

,

,

, возможна следующая перестановка:So, with

,

, the following permutation is possible:

.

.

– блок данных на входе устройства,

– блок данных на выходе устройства.In this case, for the embodiment of FIG. 1 of the device, the permutation of terminals 8 has the form shown in FIG. 2 where

- a data block at the input of the device,

- a data block at the output of the device.

To generate a permutation of the S-random interleaver, you can use the algorithm, the block diagram of which is presented in [9]. This algorithm in the MATLAB environment is as follows.

% Source data are K and S

p = randperm (K); % vector p - random permutation

for i = 1: K

       for l = 1: length (p)

           pp (i) = p (l); % pp vector - S-random permutation

           for j = 1: S

               quit = (i-j <= 0);

               if quit

                  break;

               end;

               quit1 = (abs (pp (i) -pp (i-j)) <= S);

               if quit1

                  break;

               end;

           end;

           if quit

              break;

           end;

           if quit1

           else break;

           end;

        end;

        p (l) = [];

end;

S-random permutation has important properties:

- a distance property, which means that between adjacent elements of the source block, a certain distance is maintained in the interleaved block;

- a randomness property, which means that the correlation coefficient between the elements of the output block after interleaving becomes significantly lower than the correlation coefficient between the elements of the original input block before interleaving.

In some applications, additional permutation properties may be required, such as:

- prunability, which means that the permutation must provide certain distances and degrees of randomness for smaller permutations obtained on the basis of the original;

- contention free, which is associated with the widespread use of parallel computing and means that there is no access to the same memory cells of the interleaver at the same time, conflict-free is achieved by a special selection of positions in the permutation.

There are many works in which permutations are presented that satisfy the listed properties, for example [6–8].

можно посредством дистанционного конфигурирования связей в ПЛИС на которой реализуется быстрый псевдослучайный перемежитель.In the proposed device, the property of contractility of the permutation is not required. If necessary, change the permutation, by structure and (or) size

it is possible through remote configuration of communications in the FPGA on which a fast pseudo-random interleaver is implemented.

The study of the proposed device was carried out on a personal computer through simulation in a Multisim environment. The study confirmed the claimed technical result.

) быстрого псевдослучайного перемежителя, соответствующего изобретению, рассмотрен в электронной системе моделирования Multisim 14 и поясняется иллюстрациями на которых представлены: An implementation option (on S = 1 S-random permutation

) fast pseudo-random interleaver corresponding to the invention, is considered in the electronic simulation system Multisim 14 and is illustrated by illustrations on which are presented:

FIG. 3 is a view of the apparatus of the invention in the working window of Multisim 14 according to an embodiment of the present invention;

FIG. 4 is a subcircuit view of the shift register D5 (D6) of FIG. 3;

FIG. 5 is a view of the permutation of the Permutation terminals of FIG. 3;

FIG. 6 is a timing chart of the initial phase of the operation of the device in the Multisim 14 window according to an embodiment of the present invention.

Literature

1. Sklyar B. Digital communication. Theoretical Foundations and Practical Applications, 2nd ed. / B. Sklyar; Per. from English E.G. Thunderstorms [et al.]; edited by A.V. Nazarenko - M.: Williams, 2003 .-- 1104 p.

2. Corrado-Bravo C.J., Rubio I. Algebraic construction of interleavers using permutation monomials, IEEE Communication Society. 2 (2004), pp. 911-915.

3. RF patent 2235424 class. H03M 13/27 publ. 08/27/2004. Turbo code interleaver using linear congruent sequences / Ling F., Rovitch D.N.

4. Clark J., ml. Error correction coding in digital communication systems / J. Clark, Jr., J. Kane; Per. from English C.I. Gelfand; edited by B.S. Tsybakova - M.: Radio and Communications, 1987 .-- 392 p.

5. Dolinar S., Divsalar D. Weight distributions for turbo codes using random and nonrandom permutations. 1995. TDA Progress Report 42-122, Jet Propulsion Laboratory, Pasadena, California, pp. 56-65.

6. Popovski P., Kocarev L., Risreski A. Design of flexible-length S-random interleaver for turbo codes, IEEE Commun. Letter, 2004, Vol. 8, No. 7, pp. 461-463.

7. Dinoi L., Bendetto S. Design of fast prunable S-random interleavers. IEEE Trans. Wireless Commun., 2005, Vol. 4, No. 5, pp. 1-9.

8. Gazi O. Prunable collision free random interleaver design. Wireless Personal Communications, 2012, Vol. 65, pp. 555-566.

DOI 10.1007 / s11277-011-0272-0

9. Barinov A.Yu. Interleaving in channel coding: properties, structure, application specifics. Journal of Radio Electronics [electronic journal]. 2019. №1. Access Mode: http://jre.cplire.ru/jre/jan19/13/text.pdf

DOI 10.30898 / 1684-1719.2019.1.13

Claims (1)

Fast pseudo-random interleaver, including a memory region with the ability to receive input bits in series, organized in the form of two memory devices operating in antiphase, and a control system for selecting bits from the memory region, characterized in that the memory devices are two shift registers with parallel unloading, corresponding to the outputs of these registers are combined into common outputs, which are pseudo-randomly connected to the information inputs of the multiplexer, the address inputs of this the ultiplexer is connected to the outputs of the control system for the selection of bits, and the control system for the selection of bits is a summing counter that counts the input bits at the frequency of arrival, the operation of the memory devices in antiphase is provided by a trigger operating in counting mode, and two two-input logic elements “And”, while the last output of the totalizing counter is connected to the input of the trigger, the direct output of the trigger is connected to the enable input of the output of the first shift register and to the second input of the first log logical element "And", the inverse output of the trigger is connected to the input enable output of the second shift register and to the second input of the second logical element "And", while the first inputs of the logical elements "And" are for clock pulses, and the outputs of the logical elements "And" are connected with the clock inputs of the corresponding shift registers.

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