RU2691854C1 - Asynchronous device of cordic algorithm for digital-signal processors - Google Patents

Abstract

FIELD: computer equipment.SUBSTANCE: invention relates to computer engineering. Disclosed is an asynchronous device of CORDIC algorithm for digital-signal processors, comprising a unit for increasing the number of single-type data, an initialisation and conditional transition unit of iterations, a basic unit of calculations, a shift register, a first arithmetic logic unit, a second arithmetic logic unit, a feedback register, a clock generator, a generator for reducing output data, wherein the input is at least one input of the unit for increasing the number of single-type data, the output of which is connected to the first input of the second arithmetic logic unit, output of clock signal generator is connected to first input of initialization unit and conditional switching of iterations and second input of shift register, output of which is connected to second input of initialisation unit and conditional transition of iterations, output of which is connected to first input of shift register, second input and fourth input of first arithmetic logic device, base computing unit output is connected to the first input and the third input of the first arithmetic logic unit and is connected to the second input of the second arithmetic logic unit, first output and second output of first arithmetic logic unit are connected to third input and fourth input of second arithmetic logic unit, output of which is connected to input of feedback register and input of output data reduction driver, output of feedback register is connected to input of basic unit of calculations, and output of generator of reduction of output data serves as output of device and is connected to control input of unit for increasing number of single-type data.EFFECT: reduced power consumption, simplified design and faster operation during asynchronous data exchange.1 cl, 5 dwg

Description

The invention relates to digital computing and data processing devices and is intended to be computed by an iterative method CORDIC (COordinate Rotation DIgital Computer) of converging processes, for example, square, cubic roots, division, etc.

The CORDIC approximation method is widely used in computational processes. The CORDIC algorithm has been described for a long time (J.E. Voider. The CORDIC trigonometric computing technique. IRE Trans. Electron. Comput. Sept. 1959, Vol. EC-8, No. 3, pp. 335-339). There are various methods for implementing the CORDIC algorithm, for example, based on the FPGA (Dmitry Daineko. Implementation of the CORDIC algorithm on the FPGA. Components and Technologies, # 12, 2011). In addition, this algorithmic solution is used for fast Fourier transform (Despain A.M. Fourier Transform Computations Using CORDIC Iterations. IEEE Transactions On Computers. 1974, Vol. 23, pp. 993-1001).

A CORDIC module is known for the repetitive approximation of vector rotation through a rotation angle (see, for example, US Patent US 7,606,552).

For the implementation of the CORDIC algorithm, a large number of matrices are used (Chang LW and Lee SW Systolic Arrays for the discrete Cosine Transform. IEEE Trans. On Signal Processing. Nov. 1991, Vol. 29, No. 11, pp. 2411-2418), as well as separate processor nodes for computing (Wang S. and Piuri V. A unified View of the CORDIC Processor Design. Application Specific Processors. Edited by Earl E. Swartzlander, Jr. Kluwer Academic Press. November 1996, Ch. 5, pp. 121-160 ).

The closest is the device for implementing the CORDIC algorithm when performing various mathematical operations according to XILINX, LogiCORE IP CORDIC v4.0, DS249. March 1, 2011 Product Specification.

A limitation of all known technical solutions is the substantial hardware costs, expressed in the need to use, in addition to the basic computing unit, a large number of memory tables, a large number of arithmetic logic devices, other logic devices, registers, adders, etc. It is necessary to ensure tight time synchronization of all functional units, and for this reason, the efficiency (performance) of the known technical solutions is not high enough. The known devices are characterized by a lengthy process of preparation for calculations, the need to coordinate timing diagrams and additional hardware costs.

Solved by the invention, the problem is to improve the technical and operational characteristics of the device CORDIC algorithm.

The technical result achieved with the use of the invention is to reduce power consumption, simplify the design and improve performance in asynchronous data exchange.

To solve the problem with the achievement of the claimed technical result, the asynchronous device CORDIC algorithm for digital-signal processors contains a block for increasing the number of data of the same type, an initialization and conditional iteration block, a basic computing unit, a shift register, a first arithmetic logic unit, a second arithmetic logic unit , feedback register, clock driver, driver output reduction. The input of the device is at least one input of the block for increasing the number of data of the same type, the output of which is connected to the first input of the second arithmetic logic unit. The output of the clock driver is connected to the first input of the initialization block and the conditional iteration transition and the second input of the shift register, the output of which is connected to the second input of the initialization block and the conditional iteration transition. The output of the initialization and conditional iteration transition block is connected to the first input of the shift register, as well as the second input and the fourth input of the first arithmetic logic unit. The output of the basic computing unit is connected to the first input and the third input of the first arithmetic logic unit and the second input of the second arithmetic logic unit. The first output and the second output of the first arithmetic logic unit are connected respectively to the third input and the fourth input of the second arithmetic logic unit, the output of which is connected to the input of the feedback register and the input of the output shaper. The output of the feedback register is connected to the input of the basic computing unit. The output of the driver to reduce the output data is the output of the device.

The advantages as well as the features of the present invention are explained using an embodiment of the invention with reference to the figures.

FIG. 1 shows a functional diagram of the claimed device.

FIG. 2 schematically shows the known CORDIC algorithm for the operation of the device according to FIG. one.

FIG. 3, 4, 5 are graphs of the iterative process, where:

in fig. 3 shows a graph of an iterative process, for example, for performing a division operation;

in fig. 4 shows the same as FIG. 3, but on an enlarged scale;

in fig. 5 shows the result of the division operation with various inputs (full cycles).

The list of items in FIG. one:

1 - block to increase the number of similar data

2 - block initialization and conditional transition iterations

3 - basic computing unit

4 - shift register

5 - the first arithmetic-logical device

6 - the second arithmetic-logical device

7 - feedback register

8 - clock driver

9 - shaper reduce output

10 - input (input bus)

11 - output (output signal bus)

12-22 - data bus (signal).

The asynchronous device CORDIC algorithm for digital-signal processors (Fig. 1) contains a block 1 of increasing the number of data of the same type, a block 2 of initialization and a conditional transition of iterations, a basic block 3 of calculations, a shift register 4, a first arithmetic-logical unit 5, a second arithmetic-logical device 6, feedback register 7, clock driver 8, driver 9 for reducing output data. Input 10 is at least one input of unit 1 for increasing the number of data of the same type, the output of which is connected to the first input of the second arithmetic logic unit 6. The output of the clock shaper 8 is connected to the first input of initialization unit 2 and the iteration conditional transition and the second input of the shift register 4 The output of the shift register 4 is connected to the second input of the initialization block 2 and the conditional iteration transition. The output of the initialization block 2 and the conditional iteration transition is connected to the first input of the shift register 4, the second input and the fourth input of the first arithmetic logic unit 5. The output of the basic calculation unit 3 is connected to the first input and the third input of the first arithmetic logic unit 5 and is connected to the second the input of the second arithmetic logic unit 6. The first output and the second output of the first arithmetic logic unit 5 are connected respectively to the third input and the fourth input of the second arithmetic ki-logical unit 6. The output of the second arithmetic-logic unit is connected to the feedback input of the register 7 and the input of the output reduction 9. The output of the register 7 feedback is connected to the input of the base unit 3 calculations. The output of the shaper 9 reduce the output data serves as the output device.

The proposed device is characterized by the fact that in order to implement an autonomous exchange process, simplify data reception and generate calculated results, input actions are not regulated by the arrival time, and the output response of the device is automatically determined when the iteration process is completed. The known devices are characterized by a lengthy process of preparation for calculations, the need to coordinate timing diagrams and additional hardware costs in comparison with the claimed device.

An illustration of the CORDIC algorithm is presented in FIG. 2. The algorithm is based on the sequential (iterative) approximation of the current value to the desired one. For example, for a division operation, the condition is checked:

Y⋅Z [i] -X≤0?

where Y is the divisor, X is the dividend, Z [i] is the iterative value of the desired value at the i-th step. At each iteration step, Δ [i] is subtracted or added according to the following expressions:

Z [i] -Δ [i] or Z [i] + Δ [i],

where Δ [i] at each step is halved (the actual operation is a right shift by one bit). FIG. Figure 2 shows the change in magnitude in the iterative process — V1, V2, V3, with V2-V1 corresponding to the displacement (rotation) angle twice as large as the angle corresponding to the subsequent change in V2-V3. Thus, in FIG. 2 shows the magnitude of the change in Δ [i] twice in the next iteration step.

In the inventive device, the basic computing unit 3 can perform various predefined functions, for example, division, summation, exponentiation, root extraction, etc.

The claimed device has a block 1 of increasing the number of data of the same type for repeating input actions (it can be one or two inputs depending on the type of the base unit 3), the signals to which are received from input 10 via bus 12.

Input 10 (or inputs) in asynchronous mode feeds the data for calculation. If the input buffer is involved in block 1, then the device remains in the mode of calculating the previous unfinished iterative process, and the recording of new data is not allowed. After the iteration process is completed, new data is loaded into block 1, and the next iteration process begins. In this case, the output of block 1 (on the bus 13) stores the n-number of times the data that arrived on the bus 12, where n is the number of digits in the word (word). The iterative process lasts with the number of clock cycles equivalent to the number of bits in a word.

Base unit 3 depends on the type of operation being performed. For example, to calculate the square root, the current value in the iterative process is squared in this block (word ^ 2). Thus, the bus 15 transmits the word to the first arithmetic logic unit 5, where the operation of addition / subtraction with the iteration value generated in block 2 and shift register 4 is performed. In block 2 initialization and conditional iteration of iterations at the initial stage, the maximum value Δ [i] is in the range of 0.5 from 1, which corresponds to the limit value of a positive number in the format of fixed-point numbers. This is provided by a reset signal on the first input. After the reset signal is completed, a ring consisting of block 2 and shift register 4 is turned on in the process, ensuring an iterative process and dividing the value of Δ [i] into two in each clock cycle, which corresponds to a shift to the right by one bit.

Block 2 is triggered to the specified state by the first clock signal (for example, the maximum value is the limit value of the calculation range), which in each clock cycle through the shift register 4 is halved (shift >> 1), shifting towards the lower digits by one digit . This expression is valid, for example, for data with a fixed comma in the 2 ^S complement format as a representation of numbers in the format from +1 to -1: for example, the maximum positive number is represented as 0.11111 ... 1, and the minimum number (maximum absolute value of a negative number) is as 1.0000 ... 0.

The iteration quantity Δ [i] on bus 19 is the value for addition and subtraction, constantly changing on each clock cycle, which goes to the second and fourth inputs of the arithmetic logic unit 5. On tires 16 and 17, data is generated +/- (plus / minus "), Which arrive at the third and fourth inputs of the second arithmetic logical unit 6. Depending on which value is greater - on buses 13 or 15, the comparison factor of the initial value and the value necessary for calculating is selected in the second arithmetic logical unit 6 data from the bus 16 or 17. Thus, an iterative approximation to the calculated value Δ1 [i] on the bus 18 is carried out.

The arithmetic logic unit 5 performs the function of addition and subtraction at the same time: at its first output, the addition of numbers arriving at the first and second inputs is formed ([1] + [2]). The second output is the subtraction of the numbers entering the third and fourth inputs ([3] + [4]). Arithmetic logic unit 6 is actually a subtractor with conditional formation of the result. If the number arriving at the first input is greater than the number at the second input, then the output (bus 18) generates a signal from the fourth input, otherwise from the third input.

In the shaper 9 reduce the output data is compared with the number of bits in the word. At the moment when the number of shifts in the shift register 4 is equivalent to the number of digits, an output signal is generated on bus 22 with simultaneous resolution of outputting the output to output 11. At the same time, a signal is also generated to load the following data into the input buffers of unit 1. Communication for transmitting the specified signal for loading in FIG. 1 for simplicity is shown by a dashed line, while the output of the shaper 9 reducing the output data is connected to the control input of the unit 1.

The end of the calculation process allows the processing of the following data from input 10.

Shaper 8 clock signals provides the formation of a reset signal (the beginning of the iterative process).

Feedback register 7 is a memory register for storing the current value. Register 7 provides a circuit with feedback in accordance with the principle of constructing sequential (recursive) schemes.

FIG. 3-5 are graphs of an iterative process for performing a division operation.

FIG. 3 shows the curve of the iterative process in a sequence of different values of input data arriving at the input 10. FIG. 4 shows a fragment of FIG. 3 single iteration cycles (enlarged scale along the X axis).

FIG. 5 shows the results of performing the division operation for the input data of FIG. 3

The claimed device is fully autonomous with the asynchronous principle of data exchange between data loading and the formation of the calculated result.

Thus, firstly, it was possible to develop an asynchronous device that functions in the algorithms of successive approximation of the CORDIC structure, which is effective for performing any calculations. In this case, the main result of the work is to reduce power consumption due to the asynchronous principle of operation, in which the device processes information only if there is input data. In addition, a reduction in hardware costs is achieved, since data preparation blocks are not required, the iteration process end calculations are calculated - this happens in automatic mode. Thirdly, the speed increases, because Iterative processes of calculating the quantities Δ [i] and Δ1 [i] occur simultaneously. These three factors significantly increase the efficiency of using this device.

The most successful claimed asynchronous device CORDIC algorithm for digital-signal processors is industrially applicable in separate IP blocks or directly in digital-signal processors. This device can be widely used computing environments with autonomous separation of functions in order to accelerate the computational process.

Claims (7)

Asynchronous device CORDIC algorithm for digital-signal processors, containing a unit for increasing the number of data of the same type, initialization and conditional iteration block, basic computing unit, shift register, first arithmetic logic unit, second arithmetic logic unit, feedback register, clock generator shaper reduce output data at the same time, the input is at least one input of the block for increasing the number of data of the same type, the output of which is connected to the first input of the second arithmetic logic unit, the clock driver output is connected to the first input of the initialization and iteration conditional transition and the second input of the shift register, the output of which is connected to the second input of the initialization and iteration conditional transition, the output of which is connected to the first input of the shift register, second input and the fourth input of the first arithmetic logical device the output of the basic computing unit is connected to the first input and the third input of the first arithmetic logic unit and connected to the second input of the second arithmetic logic unit, the first output and the second output of the first arithmetic-logical device are connected respectively to the third input and the fourth input of the second arithmetic-logical device, the output of which is connected to the input of the feedback register and the input of the output shaper, the output of the feedback register is connected to the input of the basic calculation unit, and the output of the shaper of the output data output serves as a device output and is connected to the control input of the unit for increasing the number of the same type data.

Images