RU2675045C1 - Microprocessor architecture with the micro controllers automatic programming function - Google Patents

Abstract

FIELD: electronic equipment.

SUBSTANCE: invention relates to the field of electronics. Technical result is achieved due to the microprocessor architecture with the automatic programming function, which contains electrically connected autonomous computing unit (ACU), configured to decode and separate data and control commands, commands transmission unit (CTU), configured to analyze the task, containing the work order definition unit (WODU), configured to determine the hybrid processors cluster synchronizer (CS) order of actions, create instructions for its operation and issuing them to the cluster synchronizer, and also the programmable logic integrated circuit (PLIC) configured to analyze the actions performed to implement the architecture interaction and system of instructions, configured to create instructions and transmit them to the hybrid processors CS, and at least two hybrid processors, at that the hybrid processors CS is configured to separate instructions into the number of hybrid processors, which are connected to the CS.

EFFECT: technical result consists in increase in speed and increase in reliability.

1 cl, 2 dwg

Description

The invention relates to the field of electronics, in particular to microprocessor architectures, namely to hybrid cluster processors.

The following terms and abbreviations are used in the description.

API (English application programming interface - application programming interface, application programming interface) - a set of ready-made classes, procedures, functions, structures and constants provided by the application (library, service) or operating system for use in external software products.

BIOS (English basic input / output system - basic input-output system), BIOS, and BSVV - a set of microprograms that implement APIs for working with computer hardware and devices connected to it.

CISC (English complex instruction set computing or complex instruction set computer) is a type of processor architecture, which is characterized by the following set of properties: non-fixed value of the length of the command; arithmetic operations are encoded in one command; a small number of registers, each of which performs a strictly defined function.

EEPROM (Electrically Erasable Programmable Read-Only Memory) is an electrically erasable reprogrammable ROM (EEPROM), one of the types of non-volatile memory.

EFI (Extensible Firmware Interface) is the interface between the operating system and the firmware that controls the low-level functions of the equipment, its main purpose is to correctly initialize the equipment when the system is turned on and transfer control to the bootloader of the operating system.

GPU (Eng. Graphics processing unit - graphics processor) - a separate device of a personal computer or game console that performs graphic rendering.

LAN (Local Area Network) is a computer network that usually covers a relatively small area or a small group of buildings (home, office, company, institute).

RISC (English reduced instruction set computer) is a processor architecture in which speed is increased by simplifying instructions so that their decoding is simpler and execution time is shorter.

WAN (Wide Area Network) is a computer network that spans large territories and includes a large number of nodes.

BAS is an autonomous computing unit.

BOD - command transfer unit.

BOPR - unit for determining the order of work.

VKEMP is a computing cluster of unified mounting computing devices.

EMP - a single mounting computing device.

SK - cluster synchronizer.

ROM (read-only memory) - non-volatile memory used to store an array of immutable data.

FPGA (programmable logic integrated circuit) is an electronic component used to create digital integrated circuits.

BS - encryption block.

СРВ - synchronization of calculation results.

The technique of generalized computing for graphics processing units is known in that the calculations are performed as non-specialized calculations or wide-profile calculations on heterogeneous equipment.

The closest analogue of the claimed invention is a unified shader architecture, in which the microprocessor is programmable. A certain part of the microprocessor calculates which instructions are most optimal for solving a specific problem, and independently programs the computing unit with those instructions and algorithms that it considers optimal for solving a specific computing problem.

The main drawback of the shader architecture is that it is a ready-made application, despite the fact that it is written and compiled for execution on the GPU. During operation, shaders access the 3D API of the GPU strictly within the framework defined by the programmer.

The technical problem to which the claimed invention is directed is to create a microprocessor with a function for automatically programming the microcontrollers of the computing system, in which when some part of the microprocessors fails, for any reason, the system as a whole will be operational. Modern computing clusters cannot provide high reliability without multiple duplication of the entire system.

The technical result of the claimed invention is to expand the functionality of the microprocessor, including increasing speed while increasing reliability, managing computing resources independently and realizing the possibility of automatic programming of microcontrollers.

The specified technical result is achieved due to the fact that the microprocessor architecture with the automatic programming function, where the microprocessor contains an electrically connected biologically active substances, made with the possibility of decryption and separation of data and control commands; BOD, made with the possibility of analyzing a task, containing BOPR, made with the possibility of determining the order of operations of SC hybrid processors, creating instructions for its operation and issuing them to the cluster synchronizer, and also configured to analyze the actions performed; FPGA to implement the interaction of the architecture and the command system, made with the possibility of creating instructions and transmitting them to the hybrid processor CPUs, and at least two hybrid processors, while the hybrid processor CPUs are capable of dividing the instructions into the number of hybrid processors that is connected to the SK.

Hybrid processors are made with the possibility of combining both RISC processors and CISC processors, and biologically active substances - with the possibility of redistributing the work of RISC and CISC processors.

The inventive architecture provides the flexibility of sharing resources without mirroring and the ability to not only provide their equipment for rent to other tasks, but also perform their computing tasks on other equipment. That is, the claimed solution allows not only to provide the resources of your computer to someone else, but also to use the resources of another computer. Such a solution does not offer any configuration of computing microprocessors, namely the dynamic separation of computing resources depending on the priorities of users and tasks.

The construction of a microprocessor with the function of automatic programming of microcontrollers, which independently decides how to carry out calculations, allows you to build scalable computer networks that will be configured independently. All this works at a lower level than the operating system, and therefore is not tied to the operating system software.

The inventive architecture of the microprocessor with the function of automatic programming of microcontrollers itself determines the operating procedure when programming microcontrollers. In the general case, it is a programmable logic integrated circuit, while the microprocessor itself programs and commutes a part of the computational module, resulting in an architecture consisting of a large number of independent microprocessors that can be controlled independently and which can replace each other during calculations, combined to increase computational performance tasks, or, but not excluding, to combine to duplicate calculations with the signs of cluster systems, which led It improves both performance and reliability.

All calculations take place in the BOD, equipped with a firmware for the interaction of the architecture and the command system. It is this microprogram that keeps the statistics of calculations, the type of data for calculations, the time taken to complete the work, which modules were used, which algorithms were used to optimize the computing process, whether a positive result was obtained from the results of the calculations already performed, application (replacement) of algorithms to find the most quick solutions to the computational problems.

In the general system for constructing a computer, the BOD is in the middle, if we consider the solution to the problem in the form of a pyramid, where tasks and data come from the top of the pyramid, and the solution is at its base, and the control system itself is built from top to bottom.

Above is a biologically active substance - a general system for ensuring functioning and communication for all other microcircuits and units, while in many ways it is quite autonomous.

BOD is located in the middle. It is he who determines the calculation algorithms, based on the choice of the originally laid down algorithms, but not limited to them. The BOD can modify the algorithms for performing tasks based on its own statistics of previous calculations and comparing the results of the work performed, both in terms of the efficiency of the program code and the use of computing resources and the time spent on the task.

When writing a program, a programmer cannot accurately predict what equipment the program will be used on, whether there are any ready-made "iron" algorithms. The programmer focuses on the API runtime, and the compiler only suggests general solutions that will work on a wide range of equipment. You have to sacrifice performance to ensure overall program compatibility. It is to solve this problem, but not only, that the self-learning microprocessor architecture is aimed at, which implements the search and application of faster algorithms for performing computational tasks, storing and analyzing the performed calculations, selecting exactly those microprocessors from the available ones that will ensure the highest speed of the computing system .

At the bottom is the BFB, in which the calculation takes place directly.

The disclosure of the claimed invention is shown using FIG. 1, 2, which depict:

FIG. 1 - block diagram of the microprocessor architecture;

FIG. 2 is a functional diagram of a microprocessor architecture.

The microprocessor architecture contains an autonomous computing unit (BAS), an instruction transmission unit, a memory (BOD), a cluster synchronizer (SC), and at least two hybrid processors (P1-P4).

In the BOD is a block determining the order of work (BOPR). BOD contains FPGA.

The microprocessor architecture works as follows. All data is encrypted during transmission between computing devices.

In BAS comes a common stream of data and commands. After decryption, the data and the task are visible, what needs to be done with this data. Data and task are sent to the BOD.

Data is directly loaded into memory, for example, EEPROM.

At the initial stage, the BOD selects what action needs to be performed, for example, video encoding, transmitting a voice signal over communication lines in real time, watching video from a WAN network, watching video from a LAN network over a dial-up channel, working with a database, working with real-time database.

The procedure determines the BOPR, which from the BOD task creates instructions for work and issues them to the SC, where the instructions are divided into the number of clusters of hybrid processors that are connected to the SC.

Then, the necessary tools are determined to complete the task based on the available instructions.

At the second stage, by means of the EMF, the user is selected, i.e. its priority in this computing system gives what task - the user priority service works.

When a user is registered in the system, they are assigned a priority in the system (hierarchy) and the duration of the priority or the conditions of actions and the change of priorities over time.

Then, an analysis of the actions performed, i.e. what exactly needs to be done, and is it possible to complete the task by dividing the task into parallel processors.

The fundamental possibility of parallelization is determined on the basis of the proposed data, i.e. to do different calculations on the same data.

If the task is simple, which is determined by the type of computational complexity, then it is sent to the RISC processor and performed at the hardware level, if it is difficult, then to the CISC processor, which performs the task at the software level depending on the instructions available, or selects an algorithm that is .

BAS 1 directly controls the operation of hybrid processors 5, combining both RISC processors and CISC processors.

Different types of data are treated differently. Depending on the type of data, the processing method is selected. It can be hardware, if there is a built-in feature, or software, for example, a single instruction stream — a multiple data stream — provides parallel calculations at the data level, performing the same operation on a variety of different data, or executing multiple commands on a single data group. In some cases, parallelization of the computational process is possible, while in others it is not.

Thus, based on the analysis of the general data stream and instructions, the biologically active substance redistributes the work between RISC and CISC processors, i.e. there is a selection of computing capabilities from existing calculators-hybrid processors.

SK sends to hybrid processors part of the instructions intended only for each hybrid processor. After executing the program on a hybrid processor, the results of the calculations are transferred to the SC, which processes them and transfers the general result of the calculations to the BOD.

The microprocessor itself programs and commutes part of the computing module, resulting in an architecture consisting of a large number of independent microprocessors that can be controlled independently and which can replace each other during calculations, combine to increase the performance of computing tasks, or, but not exclude, combine to duplicate calculations, possessing signs of cluster systems, which increases both productivity and reliability.

FPGA implements a microprogram of interaction between the architecture and the command system.

An example of processing a task.

It is necessary to encode the video, file f1 from avi1 format to avi2 format and save as f2. The task and video transcoding data from one format to another are received in the BOD. Set the priority of the task based on the priority of the user. Using BOD, tasks and possibilities are determined to conduct calculations in parallel. Free computing resources suitable for solving a computing problem are determined. They provide the construction of a matrix of hardware modules for performing the task and dividing the task into calculation modules. The task is sent to many hardware devices of CISC processors and RISC processors and receiving BAS calculation modules. Decrypt and separate data and control commands. They determine the order of work with the help of the BOPR and send tasks to the cluster of hybrid processors. Using BOD, calculation results are obtained. Calculation results are sent to peripheral devices through the BOD.

Thus, in this example, only RISC processors will be involved in video encoding, since CISC processors will be turned off when they are not needed or inefficient, and CISC processors will be used to encode key frames, since they are more efficient. In BOPR, an analysis of the computational task takes place, and on the basis of it, the algorithm of the hybrid processors is selected. Unused processors are completely turned off, which significantly increases energy efficiency and provides low thermal load on the cooling system. Thus, hybrid processors consume electricity and heat up only under load. This achieves high energy efficiency without compromising performance. But the main quality is an increase in productivity and ensuring the work of an unlimited number of processors in parallel.

Thus, the claimed architecture provides:

- increase in speed due to parallel computing;

- improving reliability, due to the claimed structure of the microprocessor;

- increased performance in the microprocessor itself, due to the separation of data streams and commands in the calculation;

- increase in speed, performance of all calculations in one memory array and the absence of the need to redirect to another VKEMP for further calculation;

- security, due to the fact that all data is sent in encrypted form via any communication channel;

- fast data encryption, due to the use of hardware encryption with an asymmetric key, which also provides high security;

- system security is ensured by dividing all processes into parallel threads and the absence of the ability of applications to intervene in the management of the operating system;

- A special system for constructing the interaction of many microprocessors, which allows you to create a powerful computing cluster.

The above examples are special cases and do not exhaust all possible implementations of the claimed invention.

The person skilled in the art should understand that various variations of the claimed invention do not change the essence of the invention, but only determine its specific embodiment.

Claims (2)

1. The architecture of the microprocessor with an automatic programming function, characterized in that the microprocessor contains an electrically connected unit of autonomous computing (BAS), configured to decrypt and separate data and control commands, a command transmission unit (BOD), configured to analyze a job, containing a block determine the operating procedure (BOPR), made with the possibility of determining the order of actions of the cluster synchronizer (SC) of hybrid processors, creating instructions for its operation and issuing download them to the cluster synchronizer, as well as configured to analyze the actions performed, a programmable logic integrated circuit (FPGA) to implement the interaction of the architecture and the command system, configured to create instructions and transfer them to the hybrid processor ICs, and at least two hybrid processors, wherein the SC of hybrid processors is configured to separate instructions into the number of hybrid processors that is connected to the SC. 2. The microprocessor architecture with the automatic programming function according to claim 1, characterized in that the hybrid processors are capable of combining both RISC processors and CISC processors, and the biologically active substances are capable of redistributing the work of RISC and CISC processors.

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