RU2674409C1 - Method for manufacturing crystals for power semiconductor devices - Google Patents

Abstract

FIELD: instrument engineering.

SUBSTANCE: invention relates to the field of design and production of power semiconductor devices and, mainly, silicon voltage limiters. In the proposed method, conditions are created for complete isolation, both on the surface and on the side cut of the metallization layers, metals, ohmic contacts of crystals when etching a damaged silicon layer.

EFFECT: technical result of the invention is the creation of a method of manufacturing crystals of power semiconductor devices with a flat pn-junction, precluding the use of precious and toxic metals, as well as the deposition of metal atoms of ohmic contacts on the pn-junction during etching the disturbed silicon layer from the side surface of the crystal formed after the separation of silicon wafers with pn structures into crystals, id est reducing the parasitic leakage current pn-junction.

1 cl, 1 tbl, 6 dwg

Description

The invention relates to the field of design and manufacture of power semiconductor devices and, mainly, silicon voltage limiters.

In FIG. 1 shows a crystal of a semiconductor diode and a brief route for its manufacture according to classical planar technology, according to which a dielectric protection 2 is applied to a semiconductor (silicon) wafer 1 doped with an admixture of one type of conductivity (p- or p-type conductivity) (Fig. 1a) ; in protection 2 by the method of photolithography create circular windows 3 (Fig. 1B); windows 3 conduct diffusion of the dopant of the opposite type of conductivity (p- or p-type) and thereby form plenary pn junctions 4 of a classical configuration with a rounded edge region 5 (Fig. 1c); on the area of the silicon wafer 1 above the pn junctions 4, local ohmic contacts 6 are applied; a continuous ohmic contact 7 is also applied to the entire area of the non-planar side of the silicon wafer 1 (Fig. 1d); a silicon wafer 1 with pn structures formed in it is separated (laser scribing, diamond needle, disk cutting, etc.) into crystals 8; Further, crystals 8 (Fig. 1e) are transferred to the assembly.

The lack of crystals 8 with "classical" planar pn junctions 4 (Fig. 1e) when used in the design of power semiconductor devices (SPPP), designed for significant operating currents and voltages, is an increased probability of thermal breakdown along the edge region 5 pn junction 4 due to increased electric field strength in this region [1]. That is, a decrease in the operational reliability of SPPP.

Also, a significant drawback of the classical pn structures in the case of SPPP is that the area of the planar pn junction 4 is smaller than the area of the crystal 8, the value of which is determined by the dimensions of the housing of the power semiconductor device into which the crystal 8 should be placed. And, as a consequence of this, a decrease in the power electrical characteristics of the SPPP, which directly depends on the size of the pn junction area.

Accordingly, in the designs of power semiconductor devices, as a rule, crystals with a flat configuration of the working part of the pn junction, preferably formed over the entire area of the crystal, are used.

In FIG. 2 shows an SPPP crystal with a flat working pn junction and a short route of its manufacture, along which dielectric protection 2 is applied over the entire area of the plate 1 (Fig. 2a); in protection 2, windows 9 are created through which protective pn junctions 10 are formed by diffusion of the dopant impurity (Fig. 2b); remove the dielectric protection 2; apply a new dielectric protection 2 over the entire area of the plate 1, in which windows 3 are created through which classical planar pn junctions 4 are formed by diffusion of the dopant, and the rounded edge regions 5 of the pn junctions 4 are then cut off -n-transitions 10 and thereby forming a flat central working part of the rn-junctions 4 (Fig. 2B); local ohmic contacts 6 are applied to the area of the silicon wafer 1 in the windows 3; on the non-planar side of the silicon wafer 1, a continuous ohmic contact 7 is applied (Fig. 2d); Further, the silicon wafer 1 with the pn structures formed in it (Fig. 2d) is mechanically separated into crystals 8 (Fig. 2e) and transferred to the assembly.

The disadvantage of planar technology for manufacturing crystals of power SPPs using protective pn junctions 10 (Fig. 2c) is an even more significant decrease in the working part of the pn junction 4 relative to the design variant of crystal 8 made according to classical planar technology (see Fig. 1e) for a given limit size of crystals 8, determined by the dimensions of the housing of the power semiconductor device into which these crystals are placed.

In FIG. Figure 3 shows an SPPP crystal with a flat pn junction and a short route of its production according to the mesa — planar technology, in accordance with which a continuous flat pn junction 11 is created in a silicon wafer 1 over the entire area; over the entire area of the plate 1, dielectric protection 2 is applied, in which, in a certain order, windows are created by a photolithographic method — cutting lines 12 (Fig. 3a) through which grooves (mesas) 13 are etched with a depth exceeding the depth of the pn junction 11; dielectric protection 2 is applied to local flat pn junctions 14 facing the lateral surfaces of mez 13 (Fig. 3b); in protection 2 above the pn junctions 14 create windows 3, inside which form local ohmic contacts 6; on the back (non-planar) side of the silicon wafer 1, a continuous ohmic contact 7 is applied (Fig. 3c); a silicon wafer 1 with pn structures formed in it is separated along the cut lines 12 by a mechanical method into crystals 8; further - crystals 8 (Fig. 3d) are transferred to the assembly.

The disadvantage of mesa is the planar technology for manufacturing crystals of 8 SPPPs (Fig. 3d) - a significant decrease in the working area of the local pn junction 14 due to the perimeter of the crystal 8 etched during the production of mez 13 along its perimeter for given limit dimensions of the crystals 8 dictated by the dimensions of the power case a semiconductor device, which in the case of SPPP, for which the power electrical characteristics directly depend on the size of the working area of the pn junction, is extremely important. The closest in technical essence and the achieved result, i.e. a prototype, we can consider a method of manufacturing crystals of semiconductor devices, presented in the description of the patent of the Russian Federation No.2012094 [2], according to which according to the first embodiment (Fig. 4) in a silicon wafer 1 form a continuous flat pn junction 11; create continuous ohmic contacts 7 on the planar and non-planar surfaces of the plate 1 (Fig. 4a), while vanadium is used as the metal of the ohmic contact 7; a layer of gold 15 is applied to the surface of vanadium (Fig. 4b), which is resistant to almost all aggressive etchants, except for aqua regia, including - to etchers for silicon; the plate 1 is mechanically separated into crystals 8 (Fig. 4B); etching the damaged silicon layer 16 (Fig. 4d); protect the local pn junction 14 overlooking the side surface of the crystal 8 with an organosilicon compound 17 of the SIEL 159-167 brand (Fig. 4e); further - crystals 8 are transferred to the assembly.

The disadvantage of this method is the use of precious metal - gold 15 (Fig. 4b), accounting and reporting on which is a big organizational problem of serial production of semiconductor devices.

Another disadvantage of the method of manufacturing crystals 8 of the SPT with the protection of the metal of the ohmic contact 7 by gold 15 is the possibility of etching the metal of the ohmic contact 7, which is protected on the surface by resistance to gold etchers 15, but open from the side, albeit thin, surface of layer 18 of metal 7, in the etching process of the damaged silicon layer 16. This amount of etched metal that has entered the etchant for silicon and, with high probability, to the pn junction 11, which extends to the side surface of the crystal 8 (Fig. 4d), may be sufficient for catastrophes oficheskogo increasing the current through the parasitic pn junction leakage 11. This effect is particularly dangerous in the case of high-voltage p-n junctions differing in the large width of the space charge. It is completely impossible to remove the metal adsorbed from the etchant solution from the silicon surface [3].

According to the second version of the patent [2] (Fig. 5), a continuous flat pn junction 11 is formed in the silicon wafer 1, continuous ohmic contacts 7 are formed on the planar and non-planar surfaces of the wafer 1 (Fig. 5a), and ohmic contacts 7 are applied a thick layer of lead 19, also characterized by resistance to etching agents for silicon (Fig. 5b), mechanically separate the plate 1 into crystals 8 (Fig. 5c), etch the damaged silicon layer 16, protect the local pn junction 14 facing the side crystal surface 8, compound 17 grade SIEL 159-167 (Fig. 5d), layers of lead 19 are pitted from the surface of the ohmic contacts 6, then crystals 8 (Fig. 5d) are transferred to the assembly.

The lack of manufacturing technology of crystals 8 power SPP according to the second version of the patent [2] (Fig. 5d), i.e. with the protection of metallic ohmic contacts to the pn structures of the power SPDs with an additional thick layer of lead 19, which, after etching the damaged silicon layer 16 of the side of the crystal 8 and protecting the pn junction 14 with compound 17, must be removed (selectively etched lead etcher) from the surface of the ohmic contact 7, - the use of lead 19, which is highly toxic in the manufacturing technology of crystals 8. For this reason, the emphasis in foreign and domestic electronic industry is on the creation of "lead-free" technologies [4].

There is also a drawback in the technology for manufacturing crystals of 8 power SPPs according to the second version of the patent [2] (Fig. 5e - the possibility of deposition on the pn junction 14 of the metal etched from the end part 18 of the local ohmic contact 7, which leads to spurious current leakages through p- n-transition 14.

The purpose of the present invention is to provide a method for manufacturing crystals of power semiconductor devices, eliminating the need to use gold or lead and preventing the metal of the ohmic contact from entering the etchant for silicon during etching of the broken silicon layer formed after the mechanical separation of silicon wafers with pn structures into crystals, and its adsorption at the exit point of the pn junction to the side surface of the silicon crystal, which leads to an increase in spurious leakage currents h Res pn junction.

This goal is achieved by a method of manufacturing a crystal 8 of a power semiconductor device (Fig. 6), by which a continuous flat pn junction 11 is formed in the semiconductor (silicon) wafer 1, continuous ohmic contacts 7 are applied to the planar and non-planar surfaces of the wafer 1 (Fig. 6a), create by the method of combined double-sided photolithography on the planar and non-planar surfaces of the plate 1 local ohmic contacts 6 (Fig. 6b), protect the plenary and non-planar sides of the plates 1 with local ohmic contacts 6 of the layer a photoresist 20, for example, resistant to silicon etchants, for example, type ФП-25, ФП-50 (Fig. 6c), photolithography using photoresist 20 opens the cutting lines 12 (Fig. g), mechanically divide the plate 1 along the cutting lines 12 into crystals 8 ( Fig. 6e), etch the violated silicon layer 16 to the protection borders of the local ohmic contacts 6 by the photoresist 20 (Fig. 6e), protect the pn junction 14, which extends to the side surface of the crystal 8, with the organosilicon compound 17 (Fig. 6g), photoresist 20 is removed, crystals 8 are washed (Fig. 6i) in deionized water, dried and transferred to the assembly.

List of figures of graphic images

FIG. 1. A brief route for manufacturing a crystal of a semiconductor device using planar technology

FIG. 2. A short route for manufacturing a crystal of a semiconductor device according to planar technology with a protective pn junction

FIG. 3. A brief route for manufacturing a crystal of a semiconductor device using the mesa - planar technology

FIG. 4. A short route for manufacturing a crystal of a semiconductor device using the technology of the prototype, the first option

FIG. 5. A short route for manufacturing a crystal of a semiconductor device using the technology of the prototype, the second option

FIG. 6. A brief route for manufacturing a crystal of a semiconductor device according to the proposed method

An example implementation of the invention

On the basis of p-type silicon of conductivity with a specific resistance of 40 Ohm-cm (KEF40), crystals of high-voltage diodes with a breakdown voltage (Uprobe) of ~ 1400 were manufactured using the proposed method (Fig. 6) and the prototype method [2] (Fig. 4) B. Two-layer metallization of Ti-Ni coated with gold (Au) was used as an ohmic contact. The parameter determining the parasitic leakage current is taken as a criterion for the quality of crystals: reverse current, Iob, with a reverse bias Ure = 400 V at this pn junction with Uprobe = 1400 V. The table shows the results of measuring the leakage current (Iob) of crystals, manufactured by the proposed and known [2] methods, demonstrating the effectiveness of the proposed method in comparison with the known method: spurious leakage currents according to the proposed method is significantly less than by the prototype method.

Literature

1. S. Grove, O. Leistiko, W.W. Hooper. Effect of Surface Fields on the Breakdown Voltage of Planar Silicon pn junctions // IEEE Trans. Electron Dev. (14) 1967

2. Patent for invention №2012094. A method of manufacturing semiconductor crystals. Kolomitsky N.G., Astapov B.A. 05/10/1995 g.

3. P.S. Agalarzade, A.I. Petrin, S.O. Isidines. Fundamentals of design and surface treatment technology pn junctions. M. "Soviet Radio", 1978

4. New European directives for electronics products. Leo Shapiro. Component Master Ltd., Israel, 2006

Claims (1)

A method of manufacturing crystals of power semiconductor devices, in which a continuous flat pn junction is formed in a semiconductor (silicon) wafer, continuous ohmic contacts are applied to the planar and non-planar surfaces of the wafer, characterized in that they create a method of combined double-sided photolithography on the planar and non-planar surfaces of the wafer local ohmic contacts, protect local ohmic contacts completely, i.e. and along the lateral part of the contacts, a layer of a photoresist resistant to etching silicon, for example, of the FP-25, FP-50 type, mechanically separate the plate into crystals, etch the damaged silicon layer to the boundaries of the local ohmic contacts by the photoresist, protect the pn junction, overlooking the side surface of the crystal with an organosilicon compound, the photoresist is removed, the crystals are washed in deionized water, dried and transferred to the assembly.

Images