RU2623660C2 - Method of detecting signals from the magnetic recorder, recorded by rll codes, and a detector for its implementation - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: method is implemented by using such features of the magnetic recording and playback path as recording at two levels and, accordingly, alternating directions of successive magnetization drops, taking into account the d-constraint of the RLL codes, and using the difference sign between successive counts at bit centers that does not change (without allowance for additive noise) under the action of multiplicative interference. The detector detects the presence of an extremum at a given bit interval using digital samples at the center of the bit intervals. In the event that the samples are sequentially incremented on (d+1) bit intervals, and in successive (d+1) bit intervals, the readings are successively reduced, the detector detects the presence of an extremum and puts "1" of the channel code in the discharge register, shifted by (d+1) bits to the higher-order bits relative to the least significant bit of the output shift register. Similarly, if the readings are successively decreased in (d+1) bit intervals, and the subsequent (d+1) bit intervals are incremented sequentially, the detector detects the presence of an extremum and puts "1" of the channel code in the discharge register, shifted on (d+1) digits in the direction of the highest digits relative to the least significant digit of the output register. The shift to (d+1) is related to the delay of the detector solution about the presence of an extremum with respect to the actual position of the extremum. After the end of the current channel code, the decision on the values of its least significant bits has not yet been made, so in parallel with the beginning of the next channel code, two short cycles are created on two counters to (d+1). One counter counts (d+1) clock pulses, and the second "freezes" with the arrival of "1" channel code, i.e. determines the position "1" in the lower bits of the previous channel code, after which "1" is entered in the corresponding lower order bit of the output register and its contents are output to the controller.

EFFECT: increased noise immunity.

2 cl, 2 dwg

Description

The present invention relates to methods for detecting (demodulating) signals from magnetic media of external storage devices and detectors for their implementation.

Currently, external storage devices on magnetic media are widely used in computers, data loggers, information retrieval systems, supercomputers (magnetic disk drives, magnetic tape drives). Despite the increase in the parameters of solid-state information storage devices and storage devices based on other physical principles of the non-electromechanical type, which play the role of external storage devices, electromechanical devices using magnetic storage media will occupy their market sector due to their inherent advantages: high surface information density, low storage cost information, resistance to external influences.

For a long time, peak detection was widely used in external storage devices, providing high reliability of data reproduction and the relative simplicity of hardware solutions. The essence of peak detection is that the reproducible response to the magnetization drop, having a bell-shaped shape of positive or negative polarity with one extremum in the interval of one bit, differentiates analogously, and the transition through zero is determined in the differentiated signal (more precisely, through a small threshold a few percent of the amplitude differentiated signal). The presence of a zero crossing is interpreted as a unit in this bit. At nominal values of the parameters of the reproduction path and a relatively low level of intersymbol interference, the output pulse generated is located in the center of the bit, which is important in both multi-channel and single-channel external storage devices. In order to simplify the device, the responses of positive and negative polarity before analog differentiation are preliminarily rectified. This method and device are considered in the article Shuvalov L.N. “Upgrading a machine’s magnetic tape drive. M. - 220 - M :, Issues of technical operation of computers, Issue. III Computing Center of the Academy of Sciences of the USSR, 1973 ”(p. 43-53), taken as an analogue of the proposed detector. The detector contains an amplifier, the input of which is connected to the output of the magnetic playback head, the output of the amplifier is connected to the input of the phase inverter, the paraphase outputs of which are connected to the input of the differentiating cascade, the output of which is connected to the input of the forming stage, the output of which is connected to the drive control device on the magnetic tape.

The disadvantage of peak detection with analog differentiation is the formation of false transitions through zero due to the addition of additive noise with a superposition of responses in areas with a slow signal change. A typical remedy against this was the formation of the strobe from the response itself at such a level that the signal changes quickly enough and the strobe occupies a certain interval in the center of the bit, and those transitions through zero that fall into the strobe “Shang X. Wang, Alex M. Taratorin Magnetic information storage technology. - Academic Press, 525 V Street, Suite 1900, San Diego, California 92101-4495, USA, 1998. - 536p ,: ISBN 0-12-734570-1 "(c. 346, 381), also accepted as an analogue of the proposed detector . The detector contains an amplifier, the input of which is connected to the output of the magnetic playback head, the output of the amplifier is connected to the input of the rectifier, the output of which is connected to the input of the gate driver and in parallel with the input of the differentiating cascade, the output of which is connected to the input of the two-input matching circuit, the second input of which is connected to the output of the driver the gate, the output of the two-input matching circuit is connected to the controller of the external storage device. This approach provides a confidence of 10 ⁸ with a relative longitudinal density of PW ₅₀ / T of 1.33 (user density). However, it has the disadvantage that under the action of multiplicative noise (deterioration of the nominal parameters of the reproduction path), the strobe disappears, which leads to the disappearance of the “unit”.

Interfering factors in the analogs are a linear shift in the position of the extrema due to intersymbol interference, multiplicative and additive interference, and non-ideal self-synchronization.

In modern external storage devices, the generally accepted detection method is PRML (Partial Response Maximum Likelihood) “Shang X. Wang, Alex M. Taratorin Magnetic information storage technology. - Academic Press, 525 B Street, Suite 1900, San Diego, California 92101 - 4495, USA, 1998. - 536p,: ISBN 0-12-734570-1 "(p.362), adopted as a prototype. PRML takes into account the change in the reference at the center of a bit due to interference with some adjacent responses under the assumption that the main parameters of the reproduction path are unchanged, i.e. the contribution of the interfering responses taken into account is known in advance. This approach allows an increase in relative longitudinal density of about 30 percent compared to peak detection “Shang X. Wang, Alex M. Taratorin Magnetic information storage technology. - Academic Press, 525 B Street, Suite 1900, San Diego, California 92101 - 4495, USA, 1998. - 536p,: ISBN 0-12-734570-1 "(p. 381). PRML uses the Viterbi detector, which is a specialized processor and is implemented on a chip with an extremely large degree of integration, to search for the most plausible channel codes. The Viterbi detector uses absolute samples to determine states in a trellis diagram that reflects the allowed channel codes and their relationship to ideal samples. Thus, PRML works well at a high level of intersymbol interference, but does not work out the multiplicative noise associated with microdefects of the storage layer, wear of the latter, and the ingress of foreign particles between the head and the carrier. Multiplicative interference causes a packet error, i.e. unwanted signal changes in a series of consecutive bits. The packet error is localized and corrected using Reed-Solomon codes within the corrective power of the code, which significantly increases the reading time.

The PRML detector, adopted as a prototype of the proposed detector, contains an amplifier, the input of which is connected to the output of the magnetic playback head, the output of the amplifier is connected to the input of the equalizer (a filter that narrows the input response), and is parallelly connected to the input of the clock generator, the output of the equalizer is connected to the input of the analog -digit converter (ADC), the ADC input that determines the quantization moment is connected to the output of the clock generator, the ADC output is connected to the input of the Viterbi detector, which contains the m branch metric, metric summarization unit, comparison with the reference ones, the selection of the most plausible states, the storage unit of the trellis diagram reference data and current data.

The main disadvantages of the prototype method and the prototype of the detector is the low noise immunity under the action of multiplicative noise and the high computing power required for operation.

The technical problem to be solved in the method of detecting signals from a magnetic information carrier recorded by RLL codes and a detector for its implementation is to increase the noise immunity under the action of multiplicative noise and reduce the required computing power, by simplifying the signal processing algorithm, with a slight decrease in noise immunity under the action of additive interference.

The technical result of the proposed method for detecting signals from a magnetic information carrier recorded by RLL codes and a detector for its implementation consists in higher noise immunity under the action of multiplicative noise and lower required computing power compared to the prototype, with a slight deterioration in noise immunity under the action of additive interference.

The technical result of the proposed method for detecting signals from a magnetic storage medium recorded by RLL codes, including amplifying a signal reproduced from a magnetic storage medium using a magnetic playback head, on an amplifier, generating from the amplified signal clock pulses at time instants corresponding to the centers of the bits of the channel code, parallel to the generation of clock pulses equalization of the amplified signal on the equalizer, conversion of the amplified signal on the ADC of a given capacity in qi Even samples at time instants determined by the sync pulses are achieved by the fact that the sync pulses immediately after generation are fed to the input of the synchronization block, in which, with the arrival of each sync pulse, a detector’s time cycle is formed, consisting of a given number of pulses spaced from each other for a period of at least at least an order of magnitude smaller than the period of the clock pulses, the digital samples from the ADC output are simultaneously fed to the sample comparison unit, on which the previous sample is subtracted from the current and restored the current sample after transmitting the sign of the subtraction result, the signal from the single output of the trigger of the sign of the result of the subtraction of the sample comparison unit, passed through the two-input matching circuit, set the trigger “more” to “1”, the signal from the zero output of the trigger of the sign of the result of the subtraction of the sample comparison unit, missed through a two-input matching circuit, set the trigger to "1" to "1", the corresponding pulse of the detector’s time cycle from bl As for synchronization, the signals from the single output of the trigger “more” are fed sequentially after each subtraction to the input trigger of the first shift register with a bit capacity (d + 1), where d is the d-restriction of the RLL code and can take values from 0 to 4, signals from the single output after the “less” trigger is fed sequentially after each subtraction to the input trigger of the second shift register with a bit capacity (d + 1), the contents of the first are shifted with the corresponding pulse of the detector’s time cycle from the synchronization block of the second shift registers with a capacity of (d + 1) to one in the direction of the higher bits, the individual outputs of the triggers of the first shift register with a capacity of (d + 1) are fed to the corresponding inputs of the first circuit with (d + 2) inputs, to (d + 2) an input which is supplied with the corresponding pulse of the detector’s time cycle from the synchronization unit, the output of the first matching circuit with (d + 2) inputs is fed to the “more and more” trigger set to “1”, the individual outputs of the triggers of the second shift register with the capacity of (d + 1) are fed to corresponding inputs of the second circuit matches on the (d + 2) inputs, on the (d + 2) input of which the corresponding pulse of the detector’s time cycle is supplied from the synchronization unit, the output of the second matching circuit on the (d + 2) inputs serves to set the “all” trigger less ”, the signal from the single output of the trigger“ more and more ”is fed to the first three-input matching circuit, the second input of which is fed the signal from the zero output of the trigger“ less is earlier ”, and the corresponding pulse of the detector’s time cycle from the synchronization block is fed to the third input, signal from the output of the first track x-input matching circuit is set to “1” trigger “more and more earlier”, the signal from the single output of the trigger “less” is fed to the second three-input matching circuit, the second input of which is fed the signal from the zero output of the trigger “more and more earlier”, and the third input serves the corresponding pulse of the detector’s time cycle from the synchronization block, the signal from the output of the second three-input matching circuit is set to the state “1”, the trigger is “less and less earlier”, the signal “1” of the channel code is generated at the third x-input matching circuit, on one input of which a signal from a single output of a trigger “more and less” is applied, a signal from a single output of a trigger “less and less earlier” is fed to a second input, and a corresponding pulse of a detector’s time cycle from a synchronization block is fed to a third input, a signal “1” channel code is also generated on the fourth three-input matching circuit, on one input of which a signal from a single output of a trigger “less and less” is fed to the second input, a signal from a single output of a trigger “more and less earlier”, and on the third input serves the corresponding pulse of the detector’s time cycle from the synchronization unit, the second output three-input matching circuit signal is reset to the “0” second shift register with a digit capacity (d + 1), the trigger is “more and more” and the trigger is “less and less earlier”, with a signal with the output of the fourth three-input matching circuit is reset to "0" the first shift register with a bit width (d + 1), the trigger is "less and less" and the trigger is "more and more earlier", the signals "1" of the channel code from the output of the third three-input matching circuit and from the fourth three-input the new coincidence circuit is combined on a two-input OR circuit, the output signal of which channel code 1 is supplied through a two-input coincidence circuit, the second input of which supplies a signal from the zero output of the “short cycle” trigger, to set the trigger shift register to “1” bit capacity L, where L is the number of bits in the channel code and can take values from 10 to 4097, located at position (d + 1) relative to the least significant bit of the output shift register with bit capacity L, the code on which is shifted to one side of the higher bits with by the output of the corresponding pulse of each time cycle of the detector operation from the synchronization unit, the clock pulses from the output of the generator of clock pulses are fed to the counter of the number of pulses of the channel code up to L through a two-input matching circuit, the second input of which supplies the signal from the single output of the trigger “resolution of the number of channel pulses”, to the input of the installation to “1” of the latter sends a signal “beginning of a sector”, and to the input of a reset to “0” a signal is sent “end of a sector” from an external storage controller, a clock from the output of the generator of clock pulses, they are fed to the first counter of the number of pulses of the channel code up to (d + 1) through a two-input matching circuit, to the second input of which a signal is sent from the single output of the “short cycle” trigger, for setting to “1” of which the counter of the number of pulses is fed channel code to L, and to set to “0” the output signal of the first counter of the number of pulses of the channel code to (d + 1), delayed by two consecutive inverters, the clock pulses from the output of the generator of clock pulses are fed to the second counter of the number channel code pulses up to (d + 1) through a two-input matching circuit to the second input of which the signal from the single output of the trigger "position count" 1 "is applied to the setting in" 1 ", which is supplied with the output of the channel code pulse count counter to L, and setting to “0” the output signal of the two-input circuit OR of “1” the channel code, the single output of the low-order trigger of the second counter of the number of pulses of the channel code up to (d + 1) is fed to one of the inputs of the first circuit with (d + 1) inputs , to the other (d-1) inputs serves the corresponding zero outputs tr igers of the next high-order bits of the second counter of the number of pulses of the channel code to (d + 1), and to the (d + 1) input, the output signal of the first counter of the number of pulses of the channel code is up to (d + 1), the output signal of the first matching circuit with (d + 1) inputs apply to the installation in “1” of the trigger of the output shift register with the capacity of L, located in the bit, shifted by d positions relative to the least significant bit of the output shift register with the capacity of L towards the higher bits, the zero output of the trigger of the least significant bit of the second pulse number counter The channel code of up to (d + 1) is fed to one of the inputs of the second matching circuit with (d + 1) inputs, the single output of the trigger of the second bit of the second counter of the number of channel code pulses up to (d + 1) is fed to one of the inputs of the second matching circuits with (d + 1) inputs to the other (d-2) inputs supply the corresponding zero outputs of the triggers of the next higher bits of the second counter of the number of pulses of the channel code to (d + 1), and to the (d + 1) input the output signal of the first counter of the number of pulses of the channel code up to (d + 1), the output signal of the second circuit coincides The signals with (d + 1) inputs are applied to set the “1” trigger of the output shift register with a bit capacity L, located in the bit shifted by (d-1) position relative to the least significant bit of the output shift register with a bit size L towards the higher bits, single trigger outputs the least significant bit and the next bit of the second counter of the number of pulses of the channel code up to (d + 1) are fed to the corresponding inputs of the third circuit matching (d + 1) inputs, to the other (d-2) inputs the corresponding zero outputs of the triggers of the next highest p the number of pulses of the second counter of the number of pulses of the channel code to (d + 1), and to the (d + 1) input, the output signal of the first counter of the number of pulses of the channel code to (d + 1), the output signal of the third matching circuit with (d + 1) inputs fed to the installation in "1" of the trigger of the output shift register with a capacity of L, located in the discharge, shifted by (d-2) position relative to the least significant bit of the output shift register with the capacity of L towards the higher digits, the output signal of the two-input circuit "OR" "1" channel code is also fed to the input of M-bit with channel code weight sensor, where M corresponds to the maximum possible weight of a given RLL code and can take values from 2 to 32, the output signal of the first channel code pulse count to (d + 1), delayed at two consecutive inverters, is fed to one of the inputs L of the output two-input matching circuits, the second inputs of which supply signals from the unit outputs of the corresponding triggers of the output shift register with a bit capacity L, the output code combination from the outputs of these two-input matching circuits is fed to external storage roller, signals from the single and zero outputs of the triggers of the M-bit counter of the channel code weight are fed to the first of the inputs M of the corresponding two-input matching schemes in accordance with all invalid values of the weight of the channel code, the second of whose inputs are output from the first counter of the number channel code pulses up to (d + 1), delayed by two consecutive inverters, the output signals of the above M two-input matching circuits are combined on the M-input OR circuit, the output one signal of which is sent to the “erased” trigger for installation in “1”, which is reset to “0” by the output signal of the first counter of the number of channel code pulses to (d + 1), delayed by two consecutive inverters, the output signal of the “erased” trigger is applied to the input of the external storage controller, signaling the erasure of the current channel code.

The technical result in the detector of signals from a magnetic medium recorded by RLL codes containing an amplifier, the input of which is connected to the output of the magnetic playback head, the output of the amplifier is connected to the input of the clock generator, and to the input of the equalizer, the output of the equalizer is connected to the input of the ADC, the input of which determines quantization frequency, connected to the output of the generator of clock pulses, is achieved by the fact that the outputs of the ADC are connected to the inputs of the unit for comparing samples, the other input of which is connected to by the corresponding output of the synchronization unit, the direct output of the sign discharge of the sample comparison unit is connected to the input of the two-input matching circuit, the second input of which is connected to the corresponding output of the synchronization unit, the output of the two-input matching circuit is connected to the input of the “more” trigger in “1”, the inverse output of the sign discharge block comparison samples connected to the input of the two-input matching circuit, the second input of which is connected to the corresponding output of the synchronization block, the output of the two-input matching circuit nen with the input of the trigger in “1” of the trigger “less”, the single output of the trigger “more” is connected to the input of the trigger in “1” of the trigger of the first shift register with bit capacity (d + 1), where d is the d-restriction of the RLL code and can take values from 0 to 4, the trigger output “less” is connected to the input of the second shift register with a bit width (d + 1), the inputs for controlling the shift circuits by 1 to the higher bits of the first and second shift registers with a bit capacity (d + 1) are connected to the corresponding output of the synchronization block , single outputs of the triggers of the first s the motor register with bit depth (d + 1) is connected to the corresponding inputs of the first matching circuit with (d + 2) inputs, (d + 2) the input of which is connected to the corresponding output of the synchronization unit, the output of the first matching circuit with (d + 2) inputs is connected to the input of the trigger is set to “more and more” in “1”, the individual outputs of the triggers of the second shift register with a bit width (d + 1) are connected to the corresponding inputs of the second matching circuit with (d + 2) inputs, (d + 2) the input of which is connected to the corresponding output block synchronization, the output of the second matching circuit with (d + 2 ) the inputs are connected to the installation input in “1” of the “less and less” trigger, the single output of the “more and more” trigger is connected to the input of the first three-input match circuit, the second input of which is connected to the zero output of the “less and less earlier” trigger, and the third input is connected to the corresponding output of the synchronization unit, the output of the first three-input matching circuit is connected to the input of the trigger in the “1” of the “more and earlier” trigger, the single output of the “less and less” trigger is connected to the input of the second three-input matching circuit, the second input of which is connected with a zero trigger output “more and more earlier”, the third input is connected to the corresponding output of the synchronization block, the output of the second three-input matching circuit is connected to the installation input in “1” of the “less and less” trigger, a single output of the “more and more” trigger is connected to the input of the third a three-input matching circuit, the second input of which is connected to the single output of the trigger "less and less earlier", and the third input is connected to the corresponding output of the synchronization block, the single output of the trigger "less and less" is connected to the input of the fourth x-input match circuit, the second input of which is connected to the single output of the trigger “more and more earlier”, and the third input is connected to the corresponding output of the synchronization block, the output of the third three-input match circuit is connected to the input of the “0” second shift register with bit resolution (d + 1) , the trigger "more and more" and the trigger "less and less earlier", the output of the fourth three-input match circuit is connected to the reset input at "0" of the first shift register with a bit capacity (d + 1), the trigger is "less and less" and the trigger is "bigger earlier", outputs t the latency and the fourth three-input matching circuit are connected to the inputs of the two-input circuit OR, the output of which is “1 channel code” is connected to the input of the two-input matching circuit, the second input of which is connected to the zero output of the “short cycle” trigger, the output of the two-input matching circuit is connected to the installation input in “1” of the trigger of the output shift register with the capacity of L, where L is the number of bits in the channel code and can take values from 10 to 4097, shifted by (d + 1) bits relative to the least significant bit, the input of the shift circuit control is 1 the high-order bits of the output shift register with a bit capacity L are connected to the corresponding output of the synchronization unit, the output of the clock generator is connected to the input of the channel code pulse count counter to L via a two-input matching circuit, the second input of which is connected to the single output of the channel resolution count of channel pulses trigger, setup input in "1" which is the input signal "start of the sector" from the controller of the external storage device, and the reset input in "0" is the input signal and the “end of sector” from the external storage controller, the output of the clock generator is connected to the input of the first counter of the number of pulses of the channel code up to (d + 1) through a two-input matching circuit, the second input of which is connected to the single output of the “short cycle” trigger, the installation input to "1" of which is connected to the output of the counter of the number of pulses of the channel code up to L, and the input to "0" of which is connected to the output of two consecutive inverters, the input of the first of which is connected to the output of the first counter of the number of pulses in the channel code up to (d + 1), the output of the generator of clock pulses is connected to the input of the second counter of the number of pulses of the channel code up to (d + 1), through a two-input matching circuit, the second input of which is connected to the single output of the trigger "position count" 1 "", the installation input in “1” of which is connected to the output of the channel code pulse count counter to L, and the reset input in “0” of which is connected to the output of the two-input circuit “OR” “1” of the channel code, the single output of the low-order trigger of the second counter of the number of channel pulses code up to (d + 1) inen with one of the inputs of the first matching circuit with (d + 1) inputs, the other (d-1) inputs are connected to the corresponding zero outputs of the triggers of the next higher bits of the second counter of the number of pulses of the channel code up to (d + 1), a (d + 1 ) the input is connected to the output of the first counter of the number of pulses of the channel code up to (d + 1), the output signal of the first coincidence circuit with (d + 1) inputs is connected to the input of the setting in “1” of the output shift register trigger with the digit capacity L, located in the discharge, offset by d positions relative to the least significant bit of the output shift of the new register with the L bit toward the higher digits, the zero output of the low-order trigger of the second counter of the number of pulses of the channel code up to (d + 1) is connected to one of the inputs of the second matching circuit with (d + 1) inputs, the single output of the trigger of the second the counter of the number of pulses of the channel code up to (d + 1) is connected to another input of the second matching circuit with (d + 1) inputs, the other (d-2) inputs are connected to the corresponding zero outputs of the triggers of the next higher bits of the second counter of the number of pulses of the channel code to (d + 1), a (d + 1) the input is connected to the output of the first counter of the number of pulses of the channel code to (d + 1), the output of the second matching circuit with (d + 1) inputs is connected to the installation input in "1" a trigger of an output shift register with a capacity of L, located in the discharge shifted by a (d-1) position relative to the least significant bit of the output shift register with a capacity of L toward the higher digits, the unit outputs of the triggers of the lower order and the subsequent discharge of the second counter of the number of channel code pulses up to ( d + 1) are connected to the corresponding by the moves of the third matching circuit with (d + 1) inputs, the other (d-2) inputs are connected to the corresponding zero outputs of the triggers of the next higher bits of the second counter of the number of channel code pulses up to (d + 1), a (d + 1) input is connected to the output of the first counter of the number of pulses of the channel code up to (d + 1), the output signal of the third matching circuit with (d + 1) inputs is connected to the installation input in “1” of the trigger of the output shift register with bit capacity L, located in the discharge shifted by (d- 2) position relative to the least significant bit of the output shear reg with bit L toward the higher digits, the output “1” of the channel code of the two-input OR circuit is connected to the input of the M-bit counter of the weight of the channel code, where M corresponds to the maximum possible weight of the given RLL code and can take values from 2 to 32, the output of the first the counter of the number of pulses of the channel code up to (d + 1), delayed on two consecutive inverters, is connected to one of the inputs L of the output two-input matching circuits, the second input of each of them is connected to a single output of the trigger of the corresponding discharge output with wig register bit L, the outputs of these two-input matching schemes are the outputs of the output code combination to the external memory controller, the single and zero outputs of the triggers of the M-bit counter of the weight of the channel code are connected to the first inputs M of the corresponding two-input matching schemes in accordance with the invalid weight of the channel code , the second inputs of the indicated M two-input matching circuits are connected to the output of the first counter of the number of pulses of the channel code up to (d + 1), delayed by two sequential inverters, the outputs of the indicated M matching circuits are connected to the corresponding inputs of the M-input circuit OR, the output of the M input circuit OR is connected to the installation input in “1” of the trigger “erased”, the reset input to “0” of which is connected with the output of the first counter of the number of pulses of the channel code delayed by two inverters to (d + 1), the trigger output “erased” is the output of the signal about the erasure of the current channel code being sent to the controller of the external storage device. Triggers “more”, “less”, “less”, “more”, “less earlier”, “more sooner”, “count of position“ 1 ”,“ short cycle ”and“ erased ”are standard triggers , and these names are entered for the convenience of understanding their functions in the device.

The circuit of the detector of signals from a magnetic storage medium recorded by RLL codes is divided into two parts, which are presented in FIG. 1 and FIG. 2. The detector, the circuit of which is shown in FIG. 1 and FIG. 2, contains the magnetic playback head 1, the output of the magnetic playback head 1 is connected to the input of the amplifier 2, the output of the amplifier 2 is connected to the input of the clock generator 3, and to the input of the equalizer 4, the output of the equalizer 4 is connected to the input of the ADC 5, an input that determines the quantization frequency which is connected to the output 6 clock generator 3, the outputs of the ADC 5 are connected to the inputs of the comparison unit 7 counts, the other input of which is connected to the output synchronization unit _{1 August} 9, an input coupled to the output of the synchro mpulsov 3, direct sign bit comparison sample 7 is connected to the input of two-input coincidence circuit unit 10, a second input coupled to an output ₈ February synchronization unit 9, the two-way circuit the output of coincidence 10 is connected to the setting input of a "1""greaterthan" the trigger 11, gating input coupled to an output synchronization unit _{3 August} 9, an inverse output of the sign comparator discharge counts 7 connected to the input of two-input coincidence circuit 12, a second input coupled to an output synchronization unit ₈ February 9, yield dvuhvhod howl coincidence circuit 12 is connected to the input of a "1" setting trigger "less than" 13, the entrance gate is connected to output _{3 August} synchronization unit 9, a single output latch "more" 11 is connected to the input for setting to "1" the flip-flop of the first shift register word length (d + 1) 14, where d is the d-restriction of the RLL code and can take values from 0 to 4; a single output of the trigger “less” 13 is connected to the input of the second shift register with a capacity of (d + 1) 15, inputs for controlling the shift circuits by 1 to the higher bits of the first and second shift registers times yadnostyu (d + 1) 14, 15 connected to the outlet _{4 August} synchronization unit 9, the unit outputs of flip-flops of the first shift register word length (d + 1) 14 are connected to respective first coincidence circuit inputs with the (d + 2) inputs 16, (d + 2 ) the input of which is connected to the output 8 ₅ of the synchronization unit 9, the output of the first matching circuit with (d + 2) inputs 16 is connected to the installation input in “1” of the “more and more” trigger 17, the gating input of which is connected to the output 8 ₆ of the synchronization unit 9 , the individual outputs of the triggers of the second shift register with a resolution of (d + 1) 15 are connected to stvuyuschimi inputs of the second circuit match the (d + 2) inputs 18, (d + 2) whose input is connected to the output ₈ May synchronization unit 9, the output of the second coincidence circuit with the (d + 2) input 18 is connected to the input for setting to "1" trigger “all less” 19, the gate input of which is connected to the output 8 of ₆ synchronization unit 9, a single output of the trigger “more” 17 is connected to the input of the first three-input matching circuit 20, the second input of which is connected to the zero output of the trigger “less before” 21 and a third input coupled to an output synchronization unit _{7 August} 9, yield first rehvhodovoy coincidence circuit 20 is connected to the setting input of a "1" latch "more before" 22 having an input gate coupled to the output ₈ August synchronization unit 9, a single output latch "less" 19 is connected to the input of the second trehvhodovoy coincidence circuit 23, the second the input of which is connected to the zero output of the trigger “more and earlier” 22, the third input is connected to the output 8 ₇ of the synchronization unit 9, the output of the second three-input matching circuit 23 is connected to the input of the setting “1” of the “less and less earlier” 21, the gate input of which connected to the output 8 of ₈ synchronization unit 9, the single output of the trigger “more and more” 17 is connected to the input of the third three-input matching circuit 24, the second input of which is connected to the single output of the trigger “all is less before” 21, and the third input is connected to the output of 8 _{9 of the} block synchronization 9, a single output flip-flop "less" 19 is connected to the input of the fourth trehvhodovoy coincidence circuit 25, the second input of which is connected to a single output latch "more before" 22, and a third input coupled to an output 8 ₉ synchronization unit 9, the output of the third trehv one match circuit 24 is connected to the input of the setting at “0” of the second shift register with a bit size (d + 1) 15, a trigger is “more and more” 17 and a trigger is “less and less earlier” 21, the output of the fourth three-input match circuit 25 is connected to the input of the set to " 0 "of the first shift register with a resolution of (d + 1) 14, a trigger of" less and less "19 and a trigger of" more and more earlier "22, the outputs of the third and fourth three-input matching circuits 24 25 are connected to the inputs of the two-input circuit" OR "26, the output of which is""1" channel code "27 is connected to the input of the two-input circuit coincides adenia 28, the second input of which is connected to the zero output of the “short cycle” trigger 29, the output of the two-input matching circuit 28 is connected to the installation input in “1” of the trigger of the output shift register with the capacity of L 30, where L is the number of bits in the channel code and can take values from 10 to 4097, shifted by (d + 1) bits relative to LSB, the shift control input circuits for higher digits 1 to the output of the shift register word length L 30 are connected to output 8 9 ₁₀ sync block, output 6 clock generator 3 is connected with WMOs ohm of the counter of the number of pulses of the channel code up to L 31, through a two-input matching circuit 32, the second input of which is connected to a single output of the trigger “resolution of the number of channel pulses” 33, the latter has a setting input of “1”, which is the input signal “beginning of the sector "From the controller of the external storage device, and the reset input to" 0 ", which is the input signal" end of sector "from the controller of the external storage device, the output 6 of the shaper of the clock 3 is connected to the input of the first counter the number of pulses of the channel code up to (d + 1) 34 through a two-input matching circuit 35, the second input of which is connected to a single output of the “short cycle” trigger 29, the input of which is set to “1” which is connected to the output of the counter of the number of pulses of the channel code up to L 31, and the input of the installation to “0” is connected to the output of two consecutive inverters 36 37, the input of the first of them is connected to the output of the first counter of the number of pulses of the channel code up to (d + 1) 34, the output 6 of the clock generator 3 is connected to the input of the second counter of the number of channel pulses code up to (d + 1) 38, through a two-input coincidence circuit 39, the second input of which is connected to a single output of the trigger “position count“ 1 ”” 40, the installation input to “1” of which is connected to the output of the counter of the number of pulses of the channel code up to L 31, and the installation input to “0” of which connected to the output “1” of the channel code "27 of the two-input OR circuit 26, the single output of the low-order trigger of the second counter of the number of pulses of the channel code up to (d + 1) 38 is connected to one of the inputs of the first matching circuit with (d + 1) inputs 41, the other (d-1) inputs are connected to the corresponding zero outputs the triggers of the next higher bits of the second counter of the number of pulses of the channel code to (d + 1) 38, and (d + 1) the input is connected by the output of the first counter of the number of pulses of the channel code to (d + 1) 34, the output signal of the first matching circuit with (d +1) the inputs 41 are connected to the installation setting in “1” of the trigger of the output shift register with a capacity of L 30 located in the discharge shifted by d positions relative to the least significant bit of the output shift register with a capacity of L 30 towards the higher bits, zero output of the trigger of the least significant bit of the second counter As the number of pulses of the channel code up to (d + 1) 38 is connected to one of the inputs of the second circuit of coincidence with the (d + 1) inputs 42, the single output of the trigger of the next second digit of the second counter of the number of pulses of the channel code up to (d + 1) 38 is connected with another input of the second matching circuit with (d + 1) inputs 42, the other (d-2) inputs are connected to the corresponding zero outputs of the triggers of the next higher bits of the second counter of the number of channel code pulses up to (d + 1) 38, a (d + 1 ) the input is connected to the output of the first counter of the number of pulses of the channel code up to (d + 1) 34, the output to The second matching circuit with (d + 1) inputs 42 is connected to the installation input in “1” of the trigger of the output shift register with a capacity of L 30, located in the discharge, shifted by (d-1) position relative to the least significant bit of the output shift register with a capacity of L 30 to the side high-order bits, the single outputs of the low-order triggers and the next bit of the second counter of the number of pulses of the channel code up to (d + 1) 38 are connected to the individual inputs of the third matching circuit with (d + 1) inputs 43, the other (d-2) inputs are connected with corresponding zero the outputs of the triggers of the next higher bits of the second counter of the number of pulses of the channel code up to (d + 1) 38, a (d + 1) the input is connected to the output of the first counter of the number of pulses of the channel code up to (d + 1) 34, the output signal of the third matching circuit with ( d + 1) the inputs 43 are connected to the installation input in “1” of the trigger of the output shift register with a capacity of L 30, located in the discharge, shifted by (d-2) position relative to the lowest bit of the output shift register with a capacity of L 30 in the direction of the higher bits, the output is “ 1 "channel code 27 two-input circuit "OR" 26 is connected to the input of the M-bit counter of the weight of the channel code 44, where M corresponds to the maximum possible weight of the given RLL code, and can take values from 2 to 32, the output of the first counter of the number of pulses of the channel code to (d + 1) 34, delayed by two sequential inverters 36 37, connected to one of the inputs L of the output two-input matching circuits 45 ₁ -45 _L , the second input of each of them is connected to a single output of the trigger of the corresponding discharge of the output shift register with a capacity of L 30, the outputs L of the output of the two-input circuits are the same Lines 45 ₁ -45 _L are the outputs of the output code combination to the controller of the external storage device, the single and zero outputs of the triggers of the M-bit counter of the weight of the channel code 44 are connected to the inputs of the corresponding M two-input matching circuits 46 ₁ -46 _M in accordance with the invalid channel weights code, one of the inputs of these matching circuits 46 ₁ -46 _{M is} connected to the output of the first counter of the number of pulses of the channel code up to (d + 1) 34, delayed by two consecutive inverters 36 37, the outputs of these matching circuits 46 ₁ -46 _{M are} connected to the corresponding inputs of the M-input circuit "OR" 47, the output of the M-input circuit "OR" 47 is connected to the installation input in "1" of the trigger "erased" 48, the input of the installation in "0" which is connected to the delayed two inverters 36 37 the output of the first counter of the number of channel pulses to (d + 1) 34, the output of the trigger "erased" 48 is the output of the signal about the erasure of the current channel code to the controller of the external storage device. In the connection diagram between the second counter of the number of pulses of the channel code up to (d + 1) 38, the first, second, and third coincidence circuits with the (d + 1) inputs 41 42 43 are presented in the form of a bus for the purpose of not blocking figure 2. For the same purpose, in in the form of a bus, the connections between the output shift register with the capacity L 30, L of the output two-input matching schemes 44 ₁ -44 _L , the M-bit counter of the weight of the channel code 44 and M of the two-input matching schemes 46 ₁ -46 _{M are} presented, the outputs in the form of bus 8 are also presented block synchronization 9. The branch from the output of the shaper syn roimpulsov 3 denotes a separate number 6, for the convenience of bringing the links to the output of Figure 2. With the same purpose a separate number 27 denotes the output two-input "OR" circuit 26. All the blocks mentioned above are known and can be performed by standard schemes. The device has power, which is not shown in the diagram.

Consider the implementation of the method for detecting signals from a magnetic medium recorded by RLL codes, and the operation of the detector for its implementation. We supply power to the detector, the magnetic carrier is set in motion, the controller finds the desired sector and from the beginning of the user data recorded by RLL codes, the signal reproduced from the magnetic data carrier by the magnetic playback head 1 is amplified by amplifier 2, clock pulses are generated from the amplified signal at times corresponding to the centers of the channel code bits on the clock generator 3, in parallel with the formation of the clock signals, the amplified signal is aligned on the equalizer 4, the signal from the output of the equalizer Lazer 4 is converted on the ADC 5 of a given bit capacity to digital samples at time instants determined by the clock pulses from the output of the clock generator 3, the clock pulses from the output of the clock generator 3 immediately after generation are fed to the input of the synchronization block 9, in which the detector’s time cycle is formed with the arrival of each clock pulse consisting of a given number of pulses spaced from each other for a period of at least an order of magnitude smaller than the period of the clock pulses, digital readings from the output of the AD 5 in parallel provided to a comparison sample 7, which is subtracted the previous frame from the current and restoring the current frame after transmission detector works subtraction result mark with a time cycle arrival of the corresponding pulse from the output ₈ January synchronization unit 9, the signal from the direct output the subtraction result sign latch block comparison samples 7 is fed to a two-input matching circuit 10, the second input of which is fed the corresponding pulse of the detector’s time cycle from output 8 ₂ block and synchronization 9, the signal from the inverted output of the sign of the subtraction result of the unit for comparing the samples of 7 is supplied to the two-input matching circuit 12, the second input of which is supplied with the corresponding pulse of the time cycle, the detector works from the output 8 of ₂ of the synchronization block 9, the signal from the output of the two-input matching circuit 10 is set in “1” the trigger is “greater” 11, the signal from the output of the two-input match circuit 12 is set to “1” the trigger is “less” 13, the gating trigger is “greater” 11 and the trigger is “less” 13 respectively the current pulse of the detector’s operating cycle from the output 8 ₃ of the synchronization unit 9, the signals from the single output of the trigger “greater than 11” are fed sequentially after each subtraction to the input trigger of the first shift register with a capacity of (d + 1) 14, where d is the d-restriction of the RLL code and can take values from 0 to 4, the signals from the single output of the trigger “less” 13 are fed sequentially after each subtraction to the input trigger of the second shift register with a capacity of (d + 1) 15, previously corresponding to the pulse of the time cycle Started detector output April ₈ sync block 9 is made shift the contents of the first 14 and second 15 shift registers word length (d + 1) by one towards MSBs, signals from individual outputs of flip-flops of the first shift register word length (d + 1) 14 are coupled to respective the inputs of the first matching circuit with (d + 2) inputs 16, to the (d + 2) input of which a corresponding pulse of the detector’s time cycle is output from output 8 ₅ of the synchronization unit 9, the signal from the output of the first matching circuit with (d + 2) inputs 16 moves to installation in "1" trig "more and more" 17, to the gating input of which a corresponding pulse of the detector’s time cycle from output 8 ₆ of synchronization unit 9 is supplied, signals from single outputs of triggers of the second shift register with a resolution of (d + 1) 15 are fed to the corresponding inputs of the second matching circuit with ( d + 2) inputs 18, to the (d + 2) input of which the corresponding pulse of the detector’s time cycle is supplied from the output 8 _of the synchronization unit 9, the signal from the output of the second matching circuit with the (d + 2) inputs 18 is fed to the setting in “1 "Trigger" less "19, on wherein a signal from the zero output of the input gate of which is supplied respective pulse cycle time of the detector output June ₈ synchronization 9, the signal from the unit output of block trigger "more" 17 is fed to the first trehvhodovuyu coincidence circuit 20, the second input flip-flop "less before "21, and a third input supplied respective pulse cycle time of the detector output from the synchronization unit _{7 August} 9, the output of the first coincidence signal trehvhodovoy circuit 20 is set to" 1 "trigger" Sun More before "22, to the input gate of which is supplied respective pulse cycle time of the detector output August ₈ synchronization unit 9, the signal from the unit output flip-flop" less "19 supplied to the second trehvhodovuyu coincidence circuit 23, the second input of which the signal from the zero output trigger "more before" 22, and a third input supplied respective pulse cycle time of the detector output from the synchronization unit _{7 August} 9, a signal output from the second trehvhodovoy coincidence circuit 23 is set in sost yanie "1" trigger "less before" 21, the input of which gate is supplied respective pulse cycle time of the detector output August ₈ synchronization unit 9, the signal "1" channel code produced by the third trehvhodovoy coincidence circuit 24, one input of which is supplied signal from the output latch unit "more" 17, a second input signal from the output of the trigger unit "less before" 21, and a third input supplied respective pulse cycle time of the detector with the output 8 ₉ 9 sync block, B the cash channel “1” of the channel code is also generated on the fourth three-input matching circuit 25, to one input of which the signal from the single output of the trigger is “less” 19, the second input is the signal from the single output of the trigger “more and earlier” 22, and to the third input receives the corresponding pulse cycle time of the detector output September ₈ sync block 9, from the output of the third trehvhodovoy circuit signal coincidence 24 is reset to "0" of the second shift register word length (d + 1) 15, the trigger "more" 17, and the trigger "all less ra earlier ”21, the signal from the output of the fourth three-input matching circuit 25 is reset to“ 0 ”the first shift register with a capacity of (d + 1) 14, the trigger is“ less and less ”19 and the trigger is“ more and more earlier ”22, signals“ 1 ”of the channel code with the output of the third three-input matching circuit 24 and the output of the fourth three-input matching circuit 25 are combined on a two-input OR circuit 26, the output signal “1” of the channel code of which is supplied through a two-input matching circuit 28, to the second input of which a signal from the zero output of the “short” trigger cycle "29, on the mustache the setting in “1” of the trigger of the output shift register with a capacity of L 30, where L is the number of bits in the channel code and can take values from 0 to 4097, located at position (d + 1) relative to the least significant bit of the output shift register with a capacity of L 30, the code is which is shifted by one in the direction of higher digits with the arrival of the corresponding pulse cycle time of the detector output _{10 August} synchronization unit 9, the clock pulses output from the clock generator 3 are fed to a counter the number of pulses to channel code L 31 through dvuhvh a matching coincidence circuit 32, to the second input of which the signal from the single output of the trigger “count the number of channel pulses” is triggered 33, the signal “beginning of the sector” from the controller of the external storage device and the reset input to “ 0 "pulse" end of sector "is supplied from the external memory controller, clock pulses from the output of the clock generator 3 are fed to the first counter of the number of pulses of the channel code up to (d + 1) 34 through a two-input matching circuit 35, to the second input which receives the signal from the single output of the “short cycle” trigger 29, which is set to “1” by the signal from the output of the channel code pulse count to L 31, and which is set to “0” and the output signal of the first counter of the channel code pulse count to (d + 1) 34, delayed by two consecutive inverters 36 37, the clock pulses from the output of the clock generator 3 are fed to the second counter of the number of pulses of the channel code up to (d + 1) 38 through a two-input matching circuit 39, to the second input of which a signal from a single on the trigger output "position count" 1 "" 40 to set to "1" which receives a signal from the output of the counter of the number of pulses of the channel code to L 31, and to set to "0" the output signal "1" of the channel code of the two-input circuit "OR »26, the signal from the single output of the low-order trigger of the second counter of the number of pulses of the channel code up to (d + 1) 38 is fed to one of the inputs of the first matching circuit with (d + 1) inputs 41, signals are sent to the other (d-1) inputs from the corresponding zero outputs of the triggers of the next higher bits of the second counter of the number and channel code pulses up to (d + 1) 38, and the input signal of the first counter of the channel code pulses up to (d + 1) 34 is fed to the (d + 1) input, the output signal of the first matching circuit with (d + 1) inputs 41 is supplied to set to “1” a trigger of an output shift register with a capacity of L 30 located in the discharge shifted by d positions relative to the least significant bit of the output shift register with a capacity of L 30 towards the higher digits, a signal from the zero output of the trigger of the lowest discharge of the second counter of the number of channel code pulses up to (d + 1) 38 fed to one of the inputs of the second matching circuit with (d + 1) inputs 42, the signal from the single output of the trigger of the next bit of the second counter of the number of pulses of the channel code up to (d + 1) 38 is fed to the other of the inputs of the second matching circuit with (d + 1 ) inputs 42, to the other (d-2) inputs signals are sent from the corresponding zero outputs of the triggers of the next higher bits of the second counter of the number of pulses of the channel code to (d + 1) 38, and the output signal of the first counter of the number is supplied to the (d + 1) input channel code pulses up to (d + 1) 34, the output signal of the second circuit with coincidence with (d + 1) inputs 42 is fed to the “1” trigger setting of the output shift register with a bit capacity of L 30 located in the bit shifted by (d-1) position relative to the lowest bit of the output shift register with a bit of L 30 towards the higher bits, the signals from the individual outputs of the triggers of the lower order and the next discharge of the second counter of the number of pulses of the channel code up to (d + 1) 38 are fed to the corresponding inputs of the third matching circuit with (d + 1) inputs 43, to the other (d-2) inputs signals with corresponding zero the outputs of the triggers of the next high order bits of the second counter of the number of pulses of the channel code to (d + 1) 38, and the input (d + 1) of the input receives the output signal of the first counter of the number of pulses of the channel code to (d + 1) 34, the output signal of the third matching circuit with (d + 1) inputs 43 is applied to set the trigger of the output shift register with a bit capacity of L 30 located in the bit shifted by (d-2) position relative to the low-order bit of the output shift register with a bit of L 30 towards the higher bits in “1” "1" channel code two-input circuit “OR” 26 is also fed to the input of the M-bit counter of the weight of the channel code 44, where M corresponds to the maximum possible weight of the given RLL code and can take values from 2 to 32, the output signal of the first counter of the number of pulses of the channel code is up to (d + 1) 34 delayed by two successive inverters 36, 37 is fed to one input of two-input L output matching circuits 45 ₁ -45 _L, the second inputs of which are supplied signals output from the respective unit triggers the output of the shift register 30, word length L, the output codewords I outputs of said two-input output matching circuits 45 ₁ -45 _L is fed to the controller of the external storage device, the signals from the unit weight and the zero output of the counter 44 triggers channel code are fed to one input of M respective coincidence circuits 46 ₁ -46 _M in accordance with all invalid values of the weight of the channel code, the input of the first counter of the number of pulses of the channel code up to (d + 1) 34, delayed by two consecutive inverters 36 37, the output signals of the above the coincidence circuit is combined on the M-input circuit “OR” 47, the output signal of which is supplied to the “1” trigger 48, which is set to “0” by the output signal of the first counter of the number of channel code pulses to (d + 1) 34 delayed by two consecutive inverters 36 37, the output signal of the trigger "erased" 48 is fed to the input of the controller of the external storage device, signaling the erasure of the current channel code.

The operation of the detector in dynamics is as follows. When a magnetic data carrier moves, the signals recorded by RLL codes and reproduced by a magnetic head are a superposition of bell-shaped responses of different polarity following each other, and the extremes of successive responses in a certain range of intersymbol interference are separated by at least (d + 1) bit intervals. The detector determines the presence of an extremum on a given bit interval using digital samples in the center of the bit intervals. If at (d + 1) bit intervals, samples are sequentially increased, and at subsequent (d + 1) bit intervals, samples are sequentially reduced, the detector detects an extremum and puts “1” channel code in the output register bit shifted by ( d + 1) bits towards the higher bits relative to the least significant bit of the output shift register. Similarly, if the samples are sequentially reduced at (d + 1) bit intervals, and the samples are sequentially increased at subsequent (d + 1) bit intervals, the detector detects the presence of an extremum and enters “1” channel code into the output register bit shifted by (d + 1) bits towards the higher bits relative to the least significant bit of the output register. The shift by (d + 1) is associated with the delay in the detector's decision on the presence of an extremum relative to the actual position of the extremum. After the end of the current channel code, a decision on the values of its least significant bits has not yet been made, therefore, in parallel with the beginning of the next channel code, two short cycles are formed on two counters up to (d + 1). One counter counts (d + 1) clock pulses, and the second “freezes” with the arrival of “1” channel code, ie determines the position of "1" in the lower digits of the previous channel code, after which "1" is entered in the corresponding least significant bit of the output register and its contents are output to the controller.

Thus, in comparison with the prototype, the proposed method for detecting signals from a magnetic storage medium recorded by RLL codes, and the detector for its implementation are more noise-resistant under the action of multiplicative noise due to solutions using the features of the magnetic recording-reproduction path. Such solutions include recording at two levels and, accordingly, alternating directions of successive magnetization drops, taking into account the d-limitation of RLL codes, and using the sign of the difference between successive samples at the bit centers, which does not change (without taking into account additive noise) under the action of multiplicative noise, unlike PRML, which uses absolute values of sequential responses. The simplification of the signal processing algorithm and, as a consequence, the reduction in the required computing power is achieved due to the fact that the proposed method and detector, unlike the prototype, do not compare the surviving code sequences on the basis of maximum likelihood. The above feature at an acceptable level reduces the noise immunity under the action of additive noise, but significantly simplifies the detector hardware.

Claims (2)

1. A method for detecting signals from a magnetic storage medium recorded by RLL codes, including amplifying a signal reproduced from a magnetic storage medium using a magnetic playback head, on an amplifier, generating from the amplified signal clock pulses at time instants corresponding to the centers of the channel code bits, parallel to generating clock pulses equalization of the amplified signal on the equalizer, conversion of the amplified signal on the ADC of the given bit depth into digital readouts at time instants, consumed by sync pulses, characterized in that the sync pulses immediately after formation are fed to the input of the synchronization block, in which, with the arrival of each sync pulse, a detector’s time cycle is formed, consisting of a given number of pulses spaced from each other by at least an order of magnitude smaller, than the period of the clock pulses, the digital samples from the output of the ADC are simultaneously fed to the block for comparing the samples, where the previous sample is subtracted from the current one and the current sample is restored after if the sign of the subtraction result is triggered by the signal from the single output of the trigger of the sign of the result of the subtraction of the sample comparison unit passed through the two-input matching circuit, the trigger is set to “1”, the signal from the zero output of the trigger of the sign of the result of the subtraction of the sign of the result of the subtraction of the sample comparison unit passed through the two-input matching circuit , set the trigger “less” to “1”, the corresponding pulse of the detector’s time cycle from the synchronization block is supplied to the second inputs of the two-input matching circuits, signals from one after the output of the “more” trigger is fed sequentially after each subtraction to the input trigger of the first shift register with a bit capacity (d + 1), where d is the d-restriction of the RLL code and can take values from 0 to 4, signals from the single output of the “less” trigger sequentially after each subtraction of the second shift register with the bit capacity (d + 1) at the input trigger, the contents of the first and second shift shift registers are shifted with the corresponding pulse of the detector’s time cycle from the synchronization block range (d + 1) to one in the direction of the higher digits, the individual outputs of the triggers of the first shift register with the bit capacity (d + 1) are fed to the corresponding inputs of the first matching circuit with (d + 2) inputs, to the (d + 2) input of which the corresponding the pulse of the detector’s time cycle from the synchronization unit, the output of the first matching circuit with (d + 2) inputs is fed to the “more and more” trigger set to “1”, single outputs of the triggers of the second shift register with bit capacity (d + 1) are fed to the corresponding inputs of the second matching schemes on (d + 2) inputs, on (d + 2) inputs for which the corresponding pulse of the detector’s time cycle from the synchronization unit is supplied, the output of the second matching circuit at the (d + 2) inputs is fed to the “less and less” trigger set to “1”, the signal from the “more and more” trigger output is fed to the first three-input a coincidence circuit, to the second input of which a signal from the zero output of the trigger “less and less earlier” is supplied, and a corresponding pulse of the detector’s time cycle from the synchronization unit is fed to the third input, the signal from the output of the first three-input matching circuit is set trigger “more and earlier” is poured into state “1”, the signal from the single output of the “less and less” trigger is fed to the second three-input matching circuit, the second input of which is fed the signal from the zero output of the “more and earlier” trigger, and to the third input the corresponding pulse of the detector’s time cycle from the synchronization unit, the signal from the output of the second three-input matching circuit is set to “1”, the trigger is “less and less earlier”, the signal “1” of the channel code is generated on the third three-input matching circuit, on one the input of which feeds the signal from the single output of the trigger “more and less”, the second input feeds the signal from the single output of the trigger “less and less earlier”, and the corresponding pulse of the detector’s time cycle from the synchronization unit is fed to the third input, channel code signal “1” is generated also on the fourth three-input coincidence circuit, to one input of which a signal from a single output of a trigger is “less and less”, the second input is fed a signal from a single output of a trigger “more and earlier”, and the corresponding signal is fed to a third input the pulse of the detector’s time cycle from the synchronization block, the signal from the output of the third three-input coincidence circuit is reset to “0” the second shift register with a bit capacity (d + 1), the trigger is “more and more” and the trigger is “less and less earlier”, the signal from the output of the fourth three-input circuit matches reset to “0” the first shift register with bit capacity (d + 1), the trigger “less and less” and the trigger “more and more earlier”, the signals “1” of the channel code from the output of the third three-input matching circuit and from the output of the fourth three-input matching circuit are combined and a two-input circuit "OR", the output signal "1" of the channel code of which is fed through a two-input matching circuit, the second input of which is fed a signal from the zero output of the "short cycle" trigger, to set the output shift register to the "1" trigger, where L L is the number of bits in the channel code and can take values from 10 to 4097, located at the position (d + 1) relative to the least significant bit of the output shift register with a bit capacity L, the code on which is shifted to one side of the higher bits with the arrival of the corresponding pulse Each time cycle of the detector’s operation from the synchronization unit, the clock pulses from the output of the generator of clock pulses are fed to the counter of the number of pulses of the channel code up to L through a two-input matching circuit, the second input of which sends a signal from the single output of the trigger “resolution of the count of channel pulses” to the installation input in “1” of the last signal “start the sector”, and the input reset at “0” signal “end of the sector” from the controller of the external storage device, clock pulses from the output of the shaper sync LSS is fed to the first counter of the number of pulses of the channel code up to (d + 1) through a two-input matching circuit, the second input of which sends a signal from the single output of the “short cycle” trigger, to set to “1” which serves the output of the counter of the number of pulses of the channel code up to L, and to set to “0” the output signal of the first counter of the number of pulses of the channel code to (d + 1), delayed by two consecutive inverters, the clock pulses from the output of the generator of clock pulses are fed to the second counter of the number of pulses of the channel code up to (d + 1) through h two-input matching circuit, to the second input of which a signal is supplied from the single output of the trigger “position count“ 1 ”” to set to “1”, which is supplied with the output of the channel code pulse count counter to L, and to set to “0” the output signal is two-input circuit "OR" "1" of the channel code, the single output of the low-order trigger of the second counter of the number of pulses of the channel code up to (d + 1) is fed to one of the inputs of the first circuit matching (d + 1) inputs, to the other (d-1) the inputs supply the corresponding zero outputs of the triggers of the next higher bits the second counter of the number of pulses of the channel code to (d + 1), and the input (d + 1) of the input signal of the first counter of the number of pulses of the channel code to (d + 1), the output signal of the first matching circuit with (d + 1) inputs apply to the installation in “1” of the trigger of the output shift register with a bit capacity L, located in the bit, shifted by d positions relative to the least significant bit of the output shift register with the bit size L towards the higher bits, the zero output of the trigger of the lowest bit of the second counter of the number of channel code pulses up to (d + 1) served on one of the inputs of the second coincidence circuit with (d + 1) inputs, a single output of the trigger following the lowest digit of the second counter of the number of channel code pulses to (d + 1), is fed to one of the inputs of the second circuit of coincidence with (d + 1) inputs to the other (d-2) inputs, the corresponding zero outputs of the triggers of the next higher bits of the second counter of the number of pulses of the channel code to (d + 1) are supplied, and to the (d + 1) input, the output signal of the first counter of the number of pulses of the channel code to (d + 1), the output signal of the second matching circuit with (d + 1) inputs is fed to an entry in the “1” trigger of the output shift register with a bit of L located in the discharge shifted by a (d-1) position relative to the least significant bit of the output shift register with a bit of L toward the higher digits, the unit outputs of the triggers of the lower order and the next bit of the second number counter the channel code pulses up to (d + 1) are fed to the corresponding inputs of the third matching circuit with (d + 1) inputs, to the other (d-2) inputs, the corresponding zero outputs of the triggers of the next high-order bits of the second counter of the number channel code pulses up to (d + 1), and at (d + 1) the input provides the output signal of the first counter of the channel code pulses up to (d + 1), the output signal of the third matching circuit with (d + 1) inputs is fed to the installation in “1” of the trigger of the output shift register with a bit of L located in the discharge shifted by a (d-2) position relative to the least significant bit of the output shift register with the bit of L toward the higher bits, the output signal of the two-input OR circuit “1” of the channel code is also sent to the input of the M-bit channel code weight counter, where M corresponds to the maximum possible weight of the given RLL code and can take values from 2 to 32, the output signal of the first counter of the number of pulses of the channel code to (d + 1), delayed by two consecutive inverters, is fed to one of the inputs L of the output two-input matching circuits, to the second the inputs of which supply signals from the unit outputs of the corresponding triggers of the output shift register with a bit capacity L, the output code combination from the outputs of these two-input matching circuits is supplied to the external memory controller devices, signals from the single and zero outputs of the triggers of the M-bit counter of the channel code weight are fed to the first of the inputs M of the corresponding two-input matching schemes in accordance with all invalid values of the weight of the channel code, the second of the inputs of which give the output signal of the first counter of the number of channel code pulses to (d + 1), delayed by two consecutive inverters, the output signals of the above M two-input matching circuits are combined on the M-input circuit "OR", the output signal of which is fed to setting the trigger “1” to “erased”, which is reset to “0” by the output signal of the first counter of the number of channel code pulses to (d + 1), delayed by two consecutive inverters, the output signal of the trigger “erased” is fed to the input of the external memory controller signaling that the current channel code is worn out. 2. A detector of signals from a magnetic information carrier recorded by RLL codes, comprising an amplifier, the input of which is connected to the output of the magnetic playback head, the output of the amplifier is connected to the input of the clock generator, and with the input of the equalizer, the output of the equalizer is connected to the ADC input, the input of which determines the frequency quantization, connected to the output of the generator of clock pulses, characterized in that the outputs of the ADC are connected to the inputs of the block comparison samples, the other input of which is connected to the corresponding output of the block synchronization, the direct output of the sign discharge of the sample comparison unit is connected to the input of the two-input matching circuit (10), the second input of which is connected to the corresponding output of the synchronization unit, the output of the two-input matching circuit (10) is connected to the installation input in the “1” trigger “more”, inverse the sign discharge of the sample comparison unit is connected to the input of the two-input matching circuit (12), the second input of which is connected to the corresponding output of the synchronization unit, the output of the two-input matching circuit (12) is connected to the input m of the setting in “1” of the trigger “less”, the single output of the trigger “more” is connected to the input of the setting in “1” of the trigger of the first shift register with a bit capacity (d + 1), where d is the d-restriction of the RLL code and can take values from 0 up to 4, the trigger output “less” is connected to the input of the second shift register with bit width (d + 1), the inputs for controlling the shift circuits by 1 to the higher bits of the first and second shift registers with bit capacity (d + 1) are connected to the corresponding output of the synchronization block, unit the outputs of the triggers of the first shear p a bit capacity histogram (d + 1) is connected to the corresponding inputs of the first matching circuit with (d + 2) inputs, (d + 2) the input of which is connected to the corresponding output of the synchronization block, the output of the first matching circuit with (d + 2) inputs is connected to the input settings in the “1” trigger “more and more”, the individual outputs of the triggers of the second shift register with a bit width (d + 1) are connected to the corresponding inputs of the second matching circuit with (d + 2) inputs, (d + 2) the input of which is connected to the corresponding output of the block synchronization, the output of the second matching circuit with (d + 2) inputs with is dined with the installation input to “1” of the “less and less” trigger, the single output of the “more and more” trigger is connected to the input of the first three-input match circuit, the second input of which is connected to the zero output of the “less and less earlier” trigger, and the third input is connected to the corresponding output synchronization unit, the output of the first three-input matching circuit is connected to the input of the trigger in “1” of the “more and more earlier” trigger, the single output of the “less and less” trigger is connected to the input of the second three-input matching circuit, the second input of which is connected to zero in during the trigger “more and earlier”, the third input is connected to the corresponding output of the synchronization block, the output of the second three-input matching circuit is connected to the installation input in “1” of the “less and earlier” trigger, the single output of the “more and more” trigger is connected to the input of the third three-input circuit coincidence, the second input of which is connected to the single output of the trigger “less and less earlier”, and the third input is connected to the corresponding output of the synchronization block, the single output of the trigger “less and less” is connected to the input of the fourth three-input coincidence circuit, the second input of which is connected to the single output of the trigger “more and more earlier”, and the third input is connected to the corresponding output of the synchronization block, the output of the third three-input matching circuit is connected to the setting input of “0” of the second shift register with bit capacity (d + 1), “more and more” trigger and “less and less earlier” trigger, the output of the fourth three-input match circuit is connected to the reset input “0” of the first shift register with bit capacity (d + 1), “less and less” trigger and “more and earlier sooner”, outputs third and even the third of three-input matching circuits are connected to the inputs of the two-input OR circuit, the output of which is “1 channel code” connected to the input of the two-input matching circuit (28), the second input of which is connected to the zero output of the “short cycle” trigger, the output of the two-input matching circuit (28) connected to the installation input in the “1” trigger of the output shift register with a bit capacity of L, where L is the number of bits in the channel code and can take values from 10 to 4097, shifted by (d + 1) bits relative to the least significant bit, the shift circuit control input is 1 to senior the bits of the output shift register with bits of L are connected to the corresponding output of the synchronization block, the output of the generator of clock pulses is connected to the input of the counter of the number of pulses of the channel code up to L via a two-input matching circuit (32), the second input of which is connected to the single output of the trigger “resolution of the number of channel pulses” , the installation input to "1" of which is the input signal of the "beginning of the sector" from the controller of the external storage device, and the reset input to "0" is the input of the signal " end of sector ”from the external memory controller, the output of the clock generator is connected to the input of the first counter of the number of pulses of the channel code up to (d + 1) through a two-input matching circuit (35), the second input of which is connected to the single output of the“ short cycle ”trigger, the setup input in “1” of which is connected to the output of the counter of the number of pulses of the channel code to L, and the input to “0” of which is connected to the output of two consecutive inverters, the input of the first of them is connected to the output of the first counter of the number of pulses channel code to (d + 1), the output of the generator of clock pulses is connected to the input of the second counter of the number of pulses of the channel code to (d + 1), through a two-input matching circuit (39), the second input of which is connected to a single output of the trigger “position count“ 1 ” ", The input of the installation in" 1 "of which is connected to the output of the counter of the number of pulses of the channel code to L, and the reset input in" 0 "of which is connected to the output of the two-input circuit" OR "" 1 "of the channel code, a single trigger output of the least significant digit of the second number counter channel code pulses up to (d + 1) s is dined with one of the inputs of the first matching circuit with (d + 1) inputs, the other (d-1) inputs are connected to the corresponding zero outputs of the triggers of the next higher bits of the second counter of the number of pulses of the channel code up to (d + 1), a (d + 1 ) the input is connected to the output of the first counter of the number of pulses of the channel code up to (d + 1), the output signal of the first coincidence circuit with (d + 1) inputs is connected to the input of the setting in “1” of the output shift register trigger with the digit capacity L, located in the discharge, offset by d positions relative to the least significant bit of the output shear of the gigabyte register with bit L toward the higher digits, the zero output of the low-order trigger of the second counter of the number of pulses of the channel code up to (d + 1) is connected to one of the inputs of the second matching circuit with (d + 1) inputs, the single output of the trigger of the second the counter of the number of pulses of the channel code up to (d + 1) is connected to another input of the second matching circuit with (d + 1) inputs, the other (d-2) inputs are connected to the corresponding zero outputs of the triggers of the next higher bits of the second counter of the number of pulses of the channel about the code to (d + 1), a (d + 1) the input is connected to the output of the first counter of the number of pulses of the channel code to (d + 1), the output of the second matching circuit with (d + 1) inputs is connected to the installation input in "1 »A trigger of an output shift register with a capacity of L, located in the discharge shifted by a (d-1) position relative to the least significant bit of the output shift register with a capacity of L toward the higher digits, the individual outputs of the triggers of the lower order and the next discharge of the second counter of the number of channel code pulses up to (d + 1) are connected to the corresponding the inputs of the third matching circuit with (d + 1) inputs, the other (d-2) inputs are connected to the corresponding zero outputs of the triggers of the next higher bits of the second counter of the number of pulses of the channel code up to (d + 1), a (d + 1) input is connected to the output of the first counter of the number of pulses of the channel code up to (d + 1), the output signal of the third matching circuit with (d + 1) inputs is connected to the installation input in “1” of the trigger of the output shift register with bit capacity L, located in the discharge shifted by (d- 2) position relative to the least significant bit of the output shear re a histogram of bit L toward the higher digits, the output "1" of the channel code of the two-input circuit "OR" is connected to the input of the M-bit counter of the weight of the channel code, where M corresponds to the maximum possible weight of this RLL code and can take values from 2 to 32, the output of the first the counter of the number of pulses of the channel code up to (d + 1), delayed on two consecutive inverters, is connected to one of the inputs L of the output two-input matching circuits, the second input of each of them is connected to a single output of the trigger of the corresponding discharge output a shift register with a bit capacity of L, the outputs of these two-input matching schemes are the outputs of the output code combination to the external memory controller, the single and zero outputs of the triggers of the M-bit counter of the channel code weight are connected to the first inputs M of the corresponding two-input matching schemes (46 ₁ , 46 _M ) in accordance with the invalid weight of the channel code, the second inputs of the indicated M two-input matching circuits (46 ₁ , 46 _M ) are connected to the output of the first counter of the number of pulses of the channel code to (d + 1), delayed on two consecutive inverters, the outputs of the indicated M matching circuits are connected to the corresponding inputs of the M-input OR circuit, the output of the M input OR circuit is connected to the installation input in the “1” trigger “erased” , the reset input at “0” which is connected to the output of the first counter of the number of channel code pulses delayed by two inverters up to (d + 1), the trigger output “erased” is the output of the signal about the erasure of the current channel code to the controller of the external storage device; the triggers "more", "less", "less", "more", "less earlier", "more sooner", "position count" 1 "," short cycle "and" erased "are standard triggers , and these names are entered for the convenience of understanding their functions in the device.

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