RU2617881C2 - Integral scheme of a quick-working matrix receiver of optical radiation - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: integrated circuit of a high-speed matrix receiver of optical radiation contains an electrical circuit consisting of a radiation receiving phototransistor and amplifying transistor, the collectors of transistors are connected to the power bus, the phototransistor base through the resistance of the phototransistor in the base circuit is connected to the common bus, the phototransistor emitter is connected to the base of the amplifying transistor, which is connected to the common bus through the resistance in the base circuit of the amplifying transistor, its emitter It is connected to the output bus which is connected to the common bus through the load resistance, the structure comprising a plurality of phototransistors forming a 2-dimensional rectangular column matrix of phototransistors and a plurality of amplifying transistors forming a 2-dimensional rectangular matrix of columns of phototransistors, and a plurality of amplifying transistors forming a row of a matrix, wherein the phototransistor emitters are connected to respective bit lines that are connected to the base regions of the row of the amplifying transistors by respective columns, the amplifiers of the amplifying transistors being connected to the output line. In this case, the design of the integrated circuit of a high-speed matrix optical radiation receiver consists of a silicon semiconductor substrate of the n(p) type of conductivity, on the reverse surface of which is n⁺ (p⁺)-layer, a dielectric, contact windows, an output line, a phototransistor and a reinforcing transistor, of the p(n)-type conductivity region are disposed on the face of the plate, and a plurality of phototransistors are formed on the front surface of the substrate, columns of a 2-dimensional matrix, and a plurality of amplifying transistors forming a row of a matrix having a common collector region in which the base regions of the p(n)-type conductivity are located, wherein their area is equal to the one of the light beam, in them, respectively, n⁺ (p⁺) regions of emitters are placed on which are connected their electrodes connected to the corresponding bit lines of the columns connected to the electrodes of the corresponding bases of the row of amplifying transistors whose emitters have emitter electrodes connected to the output bus.

EFFECT: increased speed and sensitivity of photodetectors.

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Description

The present invention relates to the field of photoelectric detectors (PEC) of optical range radiation for applications in modern systems of ranging, control of stationary and moving objects, sensing of clouds, monitoring of terrain, optical communication lines, etc.

Known traditional solar cells implemented on the basis of PIN diodes, avalanche diodes [1. D. Patti ot ab "Semiconductor particle detector and method for IIS Manufacture; 2. Skrylev P.S. and others, KMDP-PHOTO RECEIVER. RF patent 2251760 from 08/05/2002], MOS structures [3. C. Sechen, M. Thompset. Charge transfer devices. M .: Mir, 1978, p. 12-14], bipolar phototransistors [4. RF patent No. 2133524 from 07.20.1999].

Such devices have disadvantages: the PIN diode does not enhance the radiation power, the avalanche-span diode does not provide a linear dependence of the output signal on the radiation power, the MOS structures of charge-coupled devices have low speed when sampling the signal, the bipolar phototransistor has a significant stray capacitance of the emitter junction, which significantly reduces its speed, while the device has a low gain at low optical radiation power per unit light absorbing surface.

A common drawback of the above known devices is the lack of maximum local signal amplification when a small part of the light-absorbing surface is exposed, which leads to a decrease in the PEC gain and a decrease in its speed. This disadvantage is manifested to a lesser extent in the scheme and design of a composite bipolar photodetector [5. US Patent 2011/0079708], which is chosen as the prototype.

The electric circuit (Fig. 1a) contains a radiation-receiving photodiode, a parasitic vertical bipolar n-p-n-transistor, which are formed in a single CMOS process, while the n-region of the photodiode is connected to the collector of the transistor, and the p-region to the region of the p-base of the transistor. The phototransistor emitter is connected to a common bus.

The design (Fig. 1b) contains a silicon semiconductor substrate of p-type conductivity. On the front surface of the plate are a dielectric, the p-region of the photodiode, the n-region of the photodiode, a deep n-pocket, which is the collector region of the stray transistor. An n-pocket is formed in it, which is the base of the transistor. An n-emitter region is formed in the p-pocket.

The disadvantage of the prototype is the lack of local signal amplification when optical radiation enters a small part of the photosensitive region of the device, which leads to a decrease in the gain of the photoelectric optical radiation receiver and a decrease in its speed.

The objectives of the invention is to increase the speed, gain, radiation power and sensitivity of the photoelectric receiver.

The goals are achieved due to the original circuitry and the photodetector design of the matrix integrated circuit containing functionally integrated pixel bipolar structures having a common collector region.

The FEP electric circuit (Fig. 2a) contains a lot of phototransistors forming a two-dimensional rectangular matrix of columns from phototransistors, and a lot of amplifying transistors forming a row of a matrix, while the emitters of phototransistors of one column are connected through the discharge buses to the base of the amplifying transistor.

In FIG. 2b shows the design of an integrated circuit in which a plurality of phototransistors are arranged on the front surface of the substrate, forming columns of a two-dimensional matrix, and a plurality of amplifying transistors, forming a matrix row, and having a common collector region in which the base regions are located, while their area is equal to the area of the incident optical beam. Phototransistor emitters are connected to amplifying transistor bases, and amplifying transistor emitters are connected to a common bus.

The electrical circuit of the proposed photomultiplier is shown in FIG. 2a, it contains a two-dimensional matrix of bipolar phototransistors T _F , the collectors of which are connected to the power bus V _DD , the base through the resistances of the base circuit R _bf to the common bus, the emitters T _{F are} connected to the bases of the amplifying transistors T _U. The emitters of the transistors T _{U are} connected to the output bus OUT and through the load resistance R _H to the common bus.

The design and topology (top view) of the photomultiplier integrated circuit are shown respectively in FIG. 2b, c and contain a semiconductor substrate - 1 p (n) -type of conductivity, on the back surface of which there is an n ⁺ (p ⁺ ) layer - 2, on the surface of which there is a power bus electrode - 3, on the front surface of the plate there are a dielectric - 4 , contact windows - 5, common bus - 6, output bus - 7, bit buses - 8, base regions of the p (n) -type of the phototransistor - 9 and amplifying transistor - 10, respectively, regions of the n (p) -type of conductivity of their emitters - 11 and 12, respectively, base electrodes 13 and 14, emitter electrodes 15 and 16, polysilicon resistors in the chain of the phototransistor - 17, the amplifying transistor - 18 and the load transistor - 19.

Manufacturing technology

According to the invention, it can be manufactured using the relatively simple bipolar VLSI technology shown in FIG. 3, which consists in the sequence of the following operations.

1. On the surface of silicon wafers KEF-5000 with an orientation of (100) oxide is grown 0.6-0.8 μm thick, oxide is removed from the reverse side and phosphorus is diffused at a temperature of T = 900 ° C for 1 hour, then the oxide formed is removed and phosphorus-silicate glass and oxide is grown at a temperature of T = 900 ° C with a thickness of 0.8 μm on the front side of the plate.

2. Polysilicon is deposited on the front surface of the plate and doped with boron at a dose of D = 10 μC with an energy of E = 30 keV.

3. By conducting the first photolithography and ion doping of phosphorus with a dose of D = 500 μC, polysilicon resistors are formed.

4. In the oxide, open the windows for the p-regions of the transistor bases and conduct ion doping of boron with a dose of D = 3 μC, then the silicon surface is oxidized to a thickness of 0.3 μm;

5. Open contact windows to the bases and emitters of transistors.

6. The contacts to the resistors and base are aligned with ion doping of boron with a dose of D = 300 μC with an energy of E = 30 keV.

7. The emitter is formed by ion doping of arsenic with a dose of D = 1000 μC with an energy of E = 30 keV.

8. Conduct thermal annealing of radiation defects at a temperature of T = 850 ° C for 30 minutes.

9. Precipitate aluminum and conduct photolithography of wiring - connections of integrated circuit elements.

10. Carry out the burning of aluminum at a temperature of T = 475 ° C for 15 minutes.

Operating principle

As can be seen from FIG. 2b, c, with approximately the same size of the transistor in the matrix pixel, local illumination of a small area of the working surface occurs. In this case, a small part of the primary current enters through the resistance in the base circuit of the phototransistor R _bf to the common power bus, the second, most part, enters the emitter pn junction, where it amplifies approximately 50-100 times and enters the discharge bus of the corresponding matrix column, creating _bu voltage drop U across the resistance circuit R _buoy base of the amplifying transistor, which is operating in an emitter follower mode, amplifies the signal power and virtually the same as the voltage on the output line OUT, reducing the amount of incidence apryazheniya across the base-emitter voltage of the amplifying transistor. It is important to note that the row of amplifying transistors of the matrix operates in the logical "OR" mode, while on the output bus OUT there can be a signal coming from only one column.

Technical Advantages of the Invention

Since the laser beam enters a small transistor in the matrix, a higher level of injection is achieved than in one large phototransistor, which is equal in area to the matrix array, thereby increasing the gain.

Obviously, the dark current supplied to the output from only one column (determines the sensitivity threshold of the device) for the matrix will be N times fewer columns than for the "large" transistor. In this case, an increase in performance is achieved by reducing the recharging times of the total base-emitter and base-collector capacities.

It should be noted that in order to simplify, it is possible to exclude the common bus matrix from the design (Fig. 3), in this case the photomultiplier contains only two outputs and is a two-terminal device.

Claims (2)

1. An integrated circuit for a high-speed matrix optical radiation detector, comprising an electrical circuit consisting of a radiation receiving phototransistor and an amplifying transistor, while the collectors of the transistors are connected to the power bus, the base of the phototransistor is connected to a common bus through the resistance of the phototransistor in the base circuit, and the emitter of the phototransistor is connected to the base the amplifying transistor, which is connected through a resistance in the base circuit of the amplifying transistor to a common bus, its emitter is connected to the output bus, which is connected via a load resistance to a common bus, characterized in that it contains many phototransistors forming a 2-dimensional rectangular matrix of columns from phototransistors, and many amplifying transistors forming a matrix row, while the emitters of the phototransistors are connected to the corresponding discharge buses that are connected to the base areas of the line of amplifying transistors with the corresponding data columns, while the emitters of the amplifying transistors are connected to the output oh bus. 2. An integrated circuit for a high-speed matrix optical radiation detector containing a structure consisting of a silicon semiconductor substrate of an n (p) -type of conductivity, on the back surface of which there is an n ⁺ (p ⁺ ) -layer, on the surface of which there is a power bus electrode, on the front the dielectric surface, the contact windows, the output bus, the phototransistor and the amplifying transistor, the regions of the p (n) -type of conductivity of resistors, characterized in that there are many on the front surface of the substrate, are located the set of phototransistors forming columns of a 2-dimensional matrix, and the set of amplifying transistors forming a row of a matrix having a common collector region in which the base regions of the p (n) -type conductivity are located, while their area is equal to the area of the light beam, they are respectively located n ⁺ (p ⁺ ) -regions of emitters, on which their electrodes are placed, connected to the corresponding discharge buses of columns connected to the electrodes of the corresponding bases of the line of amplifying transistors, on the emitters of which are located mitter electrodes connected to the output bus.

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