RU2609067C2  Method and apparatus for transmitting and receiving information in broadcasting/communication system  Google Patents
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 RU2609067C2 RU2609067C2 RU2014112217A RU2014112217A RU2609067C2 RU 2609067 C2 RU2609067 C2 RU 2609067C2 RU 2014112217 A RU2014112217 A RU 2014112217A RU 2014112217 A RU2014112217 A RU 2014112217A RU 2609067 C2 RU2609067 C2 RU 2609067C2
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 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
 H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
 H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/63—Joint error correction and other techniques
 H03M13/635—Error control coding in combination with rate matching
 H03M13/6362—Error control coding in combination with rate matching by puncturing
 H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
 H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
 H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
 H03M13/1102—Codes on graphs and decoding on graphs, e.g. lowdensity parity check [LDPC] codes

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
 H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
 H03M13/13—Linear codes
 H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, BoseChaudhuriHocquenghem [BCH] codes

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
 H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
 H03M13/13—Linear codes
 H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, BoseChaudhuriHocquenghem [BCH] codes
 H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, BoseChaudhuriHocquenghem [BCH] codes using error location or error correction polynomials
 H03M13/152—BoseChaudhuriHocquenghem [BCH] codes

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/63—Joint error correction and other techniques
 H03M13/635—Error control coding in combination with rate matching
 H03M13/6362—Error control coding in combination with rate matching by puncturing

 H—ELECTRICITY
 H04—ELECTRIC COMMUNICATION TECHNIQUE
 H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
 H04L1/00—Arrangements for detecting or preventing errors in the information received
 H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
 H04L1/0056—Systems characterized by the type of code used
 H04L1/0057—Block codes

 H—ELECTRICITY
 H04—ELECTRIC COMMUNICATION TECHNIQUE
 H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
 H04L1/00—Arrangements for detecting or preventing errors in the information received
 H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
 H04L1/0056—Systems characterized by the type of code used
 H04L1/0067—Rate matching
 H04L1/0068—Rate matching by puncturing

 H—ELECTRICITY
 H04—ELECTRIC COMMUNICATION TECHNIQUE
 H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
 H04L1/00—Arrangements for detecting or preventing errors in the information received
 H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
 H04L1/0072—Error control for data other than payload data, e.g. control data
Abstract
Description
Technical field
[1] The present invention generally relates to the transmission and reception of information in a broadcasting system / communication system, and more particularly, to a method and apparatus for controlling a code rate in accordance with the transmission and reception of signaling information in a broadcasting system / communication system.
State of the art
[2] A broadcast / communication system may experience poor line performance due to noise, fading, and intersymbol interference (ISI). Thus, to implement highspeed digital broadcasting / communication systems that require high bandwidth and reliability, it is necessary to develop a technique to overcome noise, fading, and ISI. To solve these problems, an error correction code, such as a low density parity check code (LDPC) code, is currently being investigated to improve broadcast / communication reliability by effectively restoring information distortion to its original state.
[3] More specifically, an LDPC encoder receives LDPC information bits (either an LDPC information word or an unencoded LDPC block) containing K _{ldpc} bits to form LDPC encoded bits (or an LPDC codeword or encoded LDPC block) containing N _{ldpc} bits. If the length of the LDPC information bits input to the LDPC encoder, K _{ldpc} , is shorter than the length of the input information bits (or input information word) to be encoded, K _{sig} , then the transmission side performs encoding after the reduction process. If the number of parity bits used by the transmission side, i.e. the parity bit length, N _{tx_parity} , is shorter than the length of the parity bits output from the encoder (N _{parity} = N _{ldpc} K _{ldpc} ), then the transmission side excludes the parity bits output from the encoder by (N _{parity}  N _{tx_parity} ).
[4] If the length of the contraction bits increases, then the code rate decreases, so that the characteristic of the frequency of occurrence of erroneous bits (BER) / frequency of occurrence of erroneous frames (FER) can be improved compared to the code before the abbreviation. However, if the length of the exception bits increases, then the code rate also increases, so that the BER / FER characteristic may degrade compared to the code before the exception. Therefore, in order to maintain a similar characteristic regardless of the length of the information word for system stability, a technique is needed to select the appropriate number of exception bits in accordance with the length of the information word.
Disclosure of invention
Technical problem
[5] Accordingly, the present invention is designed to solve at least the problems and / or eliminate the disadvantages described above, and provide at least the advantages described below.
[6] An aspect of the present invention is to provide a method and apparatus for transmitting and receiving information in a broadcast / communication system.
[7] Another aspect of the present invention is to provide a method and apparatus for controlling code rate in a broadcast / communication system.
[8] Another aspect of the present invention is to provide a method and apparatus for selecting a rate of reduction / exclusion according to the length of an information word in a broadcast / communication system.
[9] Another aspect of the present invention is to provide a method and apparatus for determining the number of bits to be excluded in accordance with the length of an input information word in a broadcast / communication system.
Solution
[10] In accordance with an aspect of the present invention, a method for transmitting information in a broadcast / communication system is provided. The method includes comparing the number of bits of the information word to be transmitted with a predetermined threshold value, determining the first pair of parameters if the number of bits of the information word is less than the threshold value, determining the second pair of parameters if the number of bits of the information word is not less than the threshold value, determining the number of bits to be excluded based on one of the first pair of parameters and the second pair of parameters, and the exclusion of a certain number of bits Be excluded, with respect to the parity bits of the codeword generated by encoding the information word.
[11] In accordance with another aspect of the present invention, there is provided an apparatus for transmitting information in a broadcast / communication system. The device includes an encoder for encoding an information word to be transmitted, and deriving a code word; a controller for comparing the number of bits of the information word with a predetermined threshold value, determining a first pair of parameters if the number of bits of the information word is less than a predetermined threshold value, determining a second pair of parameters if the number of bits of the information word is not less than a predetermined threshold value, and determining the number of bits to be excluded based on one of the first pair of parameters and the second pair of parameters; and an exclusion block to exclude a certain number of bits to be excluded with respect to the parity bits of the codeword.
[12] In accordance with another aspect of the present invention, a method for receiving information in a broadcast / communication system is provided. The method includes comparing the number of bits of the information word transmitted by the transmitting side with a predetermined threshold value, determining a first pair of parameters if the number of bits of the information word is less than a predetermined threshold value, determining a second pair of parameters if the number of bits of the information word is not less than a predetermined threshold value, determining the number of bits to be excluded based on one of the first pair of parameters and the second pair of pairs ters, the formation of values corresponding to the bits excluded transmitting side, and filling formed values of the modulated signal of the received signal to form the input of the decoder, using the determined number of bits to be deleted, and decoding the input data of the decoder to recover the information word bits.
[13] In accordance with another aspect of the present invention, an apparatus for receiving information in a broadcast / communication system is provided. The device includes a demodulator for demodulating the received signal; a controller for obtaining information on the number of bits of the information word transmitted from the transmission side, comparing the number of bits of the information word transmitted by the transmission side with a predetermined threshold value, determining a first pair of parameters if the number of bits of the information word is less than a predetermined threshold value, determining a second pair parameters, if the number of bits of the information word is not less than a predetermined threshold value, and determining the number of bits, which matured be excluded on the basis of one of parameters of the first pair and the second pair of parameters; an exclusive processor for generating values corresponding to bits excluded by the transmitting side using a certain number of bits to be excluded and filling the demodulator output signal with the generated values; and a decoder for receiving and decoding the output values of the exclusive processor to recover the bits of the information word.
Brief Description of the Drawings
[14] The above and other aspects, features and advantages of some embodiments of the present invention will become more apparent from the following detailed description in conjunction with the accompanying drawings, in which:
[15] FIG. 1 is a graph illustrating a change in code rate in accordance with an embodiment of the present invention;
[16] FIG. 2 and 3 are graphs illustrating the effectiveness of an LDPC code in accordance with an embodiment of the present invention;
[17] FIG. 4 is a graph illustrating a change in effective code rate in accordance with an embodiment of the present invention;
[18] FIG. 5 is a graph illustrating the effectiveness of an LDPC code in accordance with an embodiment of the present invention;
[19] FIG. 6 is a flowchart illustrating a procedure for eliminating parity bits based on information bit lengths in accordance with an embodiment of the present invention;
[20] FIG. 7 is a diagram illustrating a frame structure for transmitting two types of parity bits in accordance with an embodiment of the present invention;
[21] FIG. 8 is a diagram illustrating a structure of an LDPC code for supporting transmission of parity bits in accordance with an embodiment of the present invention;
[22] FIG. 9 is a graph illustrating a change in effective code rate in accordance with an embodiment of the present invention;
[23] FIG. 10 is a flowchart illustrating a procedure for determining the number of two types of parity bits in accordance with an embodiment of the present invention;
[24] FIG. 11 is a block diagram illustrating a transmission side in accordance with an embodiment of the present invention; and
[25] FIG. 12 is a block diagram illustrating a receiving side according to an embodiment of the present invention.
Embodiments of the invention
[26] Next, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. Wellknown functions and structures will not be described if they can complicate the understanding of the essence of the present invention. In addition, the terms used in this document are defined based on the functions in the present invention and may vary according to users, the intention of the operator, or established practice. Therefore, definitions of terms should be made depending on the content throughout the description of the invention.
[27] Although the following description of the present invention is based on a 2nd generation digital terrestrial video broadcasting system (DVBT2), which is the European digital broadcasting standard, and a next generation portable digital video broadcasting system (DVBNGH), which is being standardized in the present time, the present invention is equally applicable to other systems.
[28] Moreover, although the following description controls the code rate corresponding to the transmission of signaling information, the present invention is also applicable to the transmission of other information.
[29] On the transmission side of the broadcast / communication system, the LDPC encoder receives K _{ldpc} LDPC information bits, generates N _{parity parity} bits, and outputs N _{ldpc} (= K _{ldpc} + N _{parity} ) LDPC encoded bits. In the following description, for convenience, input and output of “bits” will be described, but the same description also applies to input and output of characters.
[30] When variablelength signal bits are input to the encoder, the transmit side may perform reduction and / or exclusion (hereinafter referred to as “reduction / exclusion”). Namely, if the length of the LDPC information bits in the LDPC encoder is K _{ldpc} , and the signal bits having the bit length K _{sig} are input to the LDPC encoder, then the (K _{ldpc} K _{sig} ) bits are reduced. In this document, the abbreviation means filling (K _{ldpc} K _{sig} ) with “0” bits of the signal bits for LDPC encoding, and after LDPC encoding, deleting the filled “0” bits or decreasing the size of the parity check matrix in LDPC an encoder that has the same effect as shrinking based on filling and deleting. In addition, an exception means the removal of certain coding bits, mainly parity bits, from transmission.
[31] The transmission side of a broadcast / communication system may use two cascade encoders. For example, an encoder that cascades a Bose, Chowdhury, Hawkingham (BCH) code with an LDPC code, that is, a BCH / LDPC encoder, receives BCH information bits (BCH information or information bits) containing K _{bch} bits, and outputs encoded BCH bits (or a BCH codeword, or an encoded BCH block) containing N _{bch} bits. N _{bch} is equal to the number of LDPC information bits, K _{ldpc} and N _{bch} bits may also be referred to as LDPC information bits (or an uncoded LDPC block), which are information input to the LDPC encoder. The coded BCH bits, i.e., LDPC information bits, are input to an LDPC encoder and output as coded LDPC bits, an encoded LDPC block, or an LPDC codeword having a length of N _{ldpc} .
[32] When an information word, which includes signal bits having a variable length, is input to the encoder, the transmit side performs a reduction / exclusion with respect to the code word output from the encoder. That is, signal bits having a bit length of K _{sig} are input to a BCH / LDPC encoder, and (K _{bch} K _{sig} ) bits are shortened. As described above, the abbreviation means that (K _{bch} K _{sig} ) "0" bits are filled into the input signal bits and encoded by BCH / LDPC, and then the filled "0" bits are deleted.
[33] As described above, the reduction reduces the code rate, so that when the number of bits to be reduced is increased (that is, the length of the reduction bits), the encoding efficiency is increased. However, when signaling information is encoded, it is preferable that the encoding efficiency does not change with the length of the input information. That is, when the receiver power is constant, it is preferable that the efficiency does not vary with the length of the input information word. Therefore, by adjusting the number of bits to be excluded (i.e., the length of the exception bits) in accordance with the number of bits to be reduced, a stable coding efficiency is provided. The number of bits to be excluded is determined according to the bit length of the input information word, that is, the number of bits of the input information word, so the number of bits to be excluded depends on the number of bits of the input information word.
[34] Embodiments for determining an input parameter used for exclusion, that is, the number of N _{punc} bits to be excluded, will be described below.
[35] In one embodiment, the N _{punc} can be calculated using one of Equations (1) through (4).
[36] Equation (1) is used when the BCH code is cascaded, and Equation (2) is used when the BCH code is not cascaded. That is, when the BCH code is cascaded, the number of bits to be reduced is (K _{bch} K _{sig} ), so the N _{punc} can be calculated using Equation (1).
[37]
[38] ... (1)
[39] When the BCH code is not cascaded, the number of bits to be reduced is (K _{ldpc} K _{sig} ), so that N _{punc} can be calculated using Equation (2).
[40]
[41] ... (2)
[42] In Equations (1) and (2), A indicates the ratio of the number of bits to be reduced to the number of bits to be excluded, and (K _{bch} K _{sig} ) and (K _{ldpc} K _{sig} ) indicate the number of bits, which should be reduced. K _{bch} indicates the number of BCH information bits (i.e., the length of information bits) input to generate BCH coded bits including K _{ldpc} bits by BCH coding. K _{ldpc} indicates the number of LDPC information bits introduced to form the encoded LDPC bits. K _{sig} indicates the bit length of the information word input to the encoder before abbreviation. B indicates the correction factor. Operation
indicates the function "nearest smaller integer" and means the largest integer less than or equal to x.[43] When the number of bits to be excluded is calculated based on Equations (1) or (2), it is possible to obtain a code rate less than when the reduction and exclusion are not performed. In the above description, if B is 0, then it can be omitted.
[44] Alternatively, when N _{punc is} calculated using Equations (3) or (4), it is possible to obtain a code rate less than when reduction and exclusion are not performed.
[45] More specifically, when the BCH code is cascaded, the number of bits to be reduced is (K _{bch} K _{sig} ), so that N _{punc} can be calculated using Equation (3).
[46]
[47]
... (3)[48] When the BCH code is not cascaded, the number of bits to be reduced is (K _{ldpc} K _{sig} ), so that N _{punc} can be calculated using Equation (4).
[49]
[fifty]
… (four)[51] In Equations (3) and (4), A indicates the ratio of the number of bits to be reduced to the number of bits to be excluded, and (K _{bch} K _{sig} ) and (K _{ldpc} K _{sig} ) indicate the number of bits, which need to be reduced. K _{bch} indicates the number of BCH information bits (i.e., the length of information bits) input to generate BCH coded bits consisting of K _{ldpc} bits by BCH coding. K _{ldpc} indicates the number of LDPC information bits introduced to form the encoded LDPC bits. K _{sig} indicates the bit length of the information word input to the encoder before abbreviation. B indicates the correction factor. K _{sig_min} indicates the bit length of the shortest information word among the information words that can be entered into the encoder.
[52] In Equations (3) and (4), the N _{punc is} less than the number of parity bits, N _{parity} , only when the condition B <N _{parity} A (K _{ldpc} K _{sig_min} ) is _{satisfied} .
[53] In Equations (1) through (4), the N _{punc} may vary in accordance with parameters A and B. Accordingly, the code rate may vary in accordance with A and B. When K _{ldpc} bits are _{input} and N _{ldpc} encoded bits are output, the code rate of the LDPC code, R, can be calculated using Equation (5).
[54]
… (5)[55] For the K _{sig} bits of the input information word, the effective code rate R _{eff} after reduction and exclusion is calculated using Equation (6).
[56]
... (6)[57] In Equation (6), N _{bch_parity} indicates the number of parity bits of the BCH code, which is 0 when the BCH code is not used.
[58] FIG. 1 is a graph illustrating a change in effective code rate in accordance with an embodiment of the present invention. In particular, FIG. 1 illustrates a code rate change for K _{bch} = 2100, K _{ldpc} = 2160 and N _{ldpc} = 8640, when A = 1.35 and B = 3320 are applied in Equation (3), and when A = 1.32 and B = 3320 are applied in Equation (3). As shown, the code rate for transmitting information changes with A, that is, when A increases, the code rate also increases.
[59] FIG. 2 illustrates the frequency of occurrence of error frames (FER) of a codeword with respect to different information bit lengths: 280, 396, 880, 1350, 1550, 1670 and 1900 for A = 1.35 and B = 3320.
[60] Referring to FIG. 2, when the number of input information bits, K _{sig} , is 280, a decrease in efficiency occurs. Therefore, for FER = 10e4, the difference in efficiency between the best efficiency and the worst efficiency is 0.7 dB.
[61] FIG. 3 illustrates the FER of a codeword with respect to different information bit lengths: 280, 396, 880, 1350, 1550, 1670, 1900 for A = 1.32 and B = 3320.
[62] Referring to FIG. 3, the code rate is less than that in FIG. 2, so that an increase in overall efficiency is achieved. In particular, when the number of input information bits, K _{sig} , is 1350, the efficiency is much better than in other cases. It is also seen that for FER = 10e4, the difference in efficiency between the best efficiency and the worst efficiency is 0.7 dB.
[63] As described above, it is preferable that the coding efficiency does not vary greatly with the length of the input information bits. Thus, a method is needed to control A and B in Equations (1) through (4) in accordance with the length of the input information bits.
[64] Therefore, in accordance with an embodiment of the present invention, N _{punc} is determined using Equations (7) and (8).
[65]
... (7)[66]
… (8)[67] In Equations (7) and (8), different values of A and B, that is, A _{1} and B _{1} or A _{2} and B _{2} , are used in accordance with the length of the input information bits.
[68] If B _{1} is an integer, then Equation (7) can be reduced to the following Equation (7a).
[69]
... (7a)[70] If A _{1} = C + D (where C is an integer and D is a real number), then Equation (7) can be reduced to the following Equation (7b).
[71]
[72]
... (7b)[73] Equation (8) can also be changed similarly to Equations (7a) and (7b).
[74] In Equations (7) and (8), the case of the length of the input information bits is less than the predetermined threshold value K _{th} and the case of the length of the input information bits is greater than the threshold value K _{th is separated} . However, a plurality of threshold values may be used to separate the length case of the input information bits, so that two or more pairs A and B can be used.
[75] K _{th} can be determined empirically so as not to cause differences in coding efficiency with N _{punc} . In particular, the value corresponding to the case where the efficiency is relatively good, or the case where the efficiency is relatively poor, is defined as K _{th} . Moreover, different pairs of parameters (A _{1} , B _{1} ) and (A _{2} , B _{2} ) are determined so that for K _{sig} = K _{th the} values of N _{punc} are equal to each other.
[76] As described above, the number of bits to be eliminated is preferably adjusted in accordance with the number of bits to be reduced, and the number of bits to be reduced is determined in accordance with the bit length of the input information word. Thus, A _{1} and A _{2} indicating the ratio of the number of bits to be reduced to the number of bits to be excluded can be constant values determined in accordance with the bit length of the input information word. Therefore, B _{1} and B _{2} can be defined as constant values.
[77] Once the N _{punc} is determined as described above, the transmission side excludes the parity bits from the encoded bits generated by encoding the input information bits using the N _{punc} .
[78] FIG. 4 is a graph illustrating a change in effective code rate in accordance with an embodiment of the present invention, where A = 1.35 and B = 3320 in Equation (3), and A = 1.32 and B = 3320 in Equation (3) are compared with using Equations (7) and (8), which is marked as “Proposed”.
[79] In particular, “Proposed” indicates that K _{bch} = 2100, K _{ldpc} = 2160, N _{ldpc} = 8640, A _{1} = 1.3, B _{1} = 3357, A _{2} = 1.35, B _{2} = 3320 and K _{th} = 1350 are applied in Equation (7). As illustrated in FIG. 4, when K _{sig is} greater than 1350, which is equal to K _{th} , the “Proposed” case shows the same code rate as with A = 1.35 and B = 3320 in Equation (3).
[80] FIG. 5 is a graph illustrating an FER in accordance with an embodiment of the present invention. In particular, FIG. 5 illustrates the FER characteristic with respect to different information bit lengths: 280, 396, 880, 1350, 1550, 1670, and 1900.
[81] Referring to FIG. 5, for an input information bit length of 280, the code rate is less than that illustrated in FIG. 2, so the efficiency is better. For an input information bit length of 1350, the code rate is greater than that illustrated in FIG. 3, so that a decrease in efficiency occurs. Therefore, the difference in overall efficiency is 0.3 dB, and the difference in coding efficiency is reduced compared to FIG. 2 and 3.
[82] In the above description, the number of N _{punc} bits to be excluded is calculated using the above equations. However, in the following description, the value obtained using the above equations is assumed to be an intermediate value of N _{punc} , that is, an intermediate number of N _{punc_temp} bits that need to be excluded, and through several processes N _{punc is} obtained more precisely.
[83] According to an embodiment of the present invention, the transmitting side, when executing an exception using N _{punc,} can more accurately adjust the N _{punc} according to additional parameters, for example, the number of BCH parity bits, modulation order, etc. The procedure for calculating the final will be described below. the number of bits to be excluded using N _{punc_temp} .
[84] Stage 1:
[85] The intermediate number of N _{punc_temp} bits to be excluded is calculated using Equation (9), which is substantially the same as the above Equation (7) and the associated description.
[86]
…(9)[87] An LDPC code cascaded with a BCH code is used, and in Equation (9), the values (A _{1} , B _{1} ) = (1,3, 3357) and (A _{2} , B _{2} ) = (1.35) are used , 3320) of FIG. four.
[88] Stage 2:
[89] The intermediate number of N _{post_temp} bits to be encoded is calculated using N _{punc_temp} , as shown in Equation (10).
[90]
…(10)[91] In Equation (10), K _{sig} indicates the number of input information bits, as described above, and may indicate, for example, the number of bits of signal information. N _{bch_parity} indicates the number of BCH parity bits, and N _{ldpc_parity_ext_4K} indicates a constant value determined in accordance with the type of LDPC code.
[92] Stage 3:
[93] Given the N _{post_temp} and the modulation order, the final number of bits to be encoded (the number of bits of each LDPC block) is calculated using Equation (11a):
[94]
... (11a)[95] In Equation (11a), η _{MOD} indicates a modulation order that is 1, 2, 4, and 6 for onoff phase shift keying (BPSK), quadrature PSK (QPSK), 16position quadrature amplitude modulation (16QAM), and 64 positional QAM (64QAM), respectively.
[96] Determining the number of encoded bits of each block of the information word, N _{post} , as shown in Equation (11a), causes N _{post to} be a multiple of the number of columns in the block interleaver. Block interleaver, although not shown and not further described, is used when the bits of each LDPC block are later bitwise interleaved.
[97] When the block interleaver is not used, for example, when only BPSK and QPSK are used, Equation (11a) can be converted to Equation (11b).
[98]
... (11b)[99] Step 4:
[100] The number of N _{punc} bits to be excluded from the parity bits of each LDPC block is calculated using Equation (12).
[101] N _{punc} = N _{punc_temp}  (N _{post}  N _{post_temp} ) ... (12)
[102] FIG. 6 is a flowchart illustrating a procedure for eliminating parity bits based on the length of input information bits in accordance with an embodiment of the present invention.
[103] Referring to FIG. 6, in step 600, the number of input information bits is determined, including signaling information for transmission (i.e., the length of the input information bits). At 602, the transmit side checks the parameters to calculate the number of bits to be excluded, i.e., the length of the exception bits. Namely, the transmission side determines whether to select (A _{1} , B _{1} ) or (A _{2} , B _{2} ), in accordance with the length of the input information bits, using Equations (7) and (8). Although not shown, one of two or more predefined parameter pairs may be selected according to the length of the input information bits. Alternatively, at block 602, the transmission side may obtain the parameter values (A _{1} , B _{1} ) = (1,3, 3357) or (A _{2} , B _{2} ) = (1.35, 3320), which must be used in Equation ( 9), in accordance with the result of comparing the length of the input information bits with a predetermined threshold value equal to 1350.
[104] At step 604, the number of parity bits to be excluded (that is, the length of the parity bits to be excluded) is calculated based on certain parameters, for example, using Equations 7 and 8 or Equations (9) through (12). At 606, the codeword parity bits are excluded based on the calculated exception parity bit length.
[105] Parity bits generated with respect to the signal bits, which are input information bits, may be transmitted in a distributed manner by the same frame as the frame in which the signal bits are transmitted and the previous frame. Parity bits transmitted by the same frame as the frame that carries the signal bits in this document will be called first parity, and parity bits transmitted by the previous frame in this document will be called second parity or additional parity.
[106] FIG. 7 is a diagram that illustrates a frame structure for transmitting two types of parity bits in accordance with an embodiment of the present invention.
[107] Referring to FIG. 7, the Level1 signaling bits are transmitted by the ith frame 702; a first parity 710 generated for the signal bits is transmitted by the ith frame 702 together with the signal bits; and additional parity 712 is transmitted by the (i1) th frame 700.
[108] According to an embodiment of the present invention, the receiving side performs decoding based on the signal bits and the first parity 710 received by the ith frame 702. If decoding fails, the receiving side also performs decoding using the additional parity 712 received by (i1) th frame 700.
[109] According to another embodiment of the present invention, if decoding with respect to signal bits and first parity 710 fails, then the receiving side determines that decoding with respect to signal bits fails, retains the additional parity included in the ith frame 702, and then takes the (i + 1) th frame.
[110] According to another embodiment of the present invention, the receiving side always stores the additional parity 712 received by the (i1) th frame 700, and performs decoding based on the signal bits and the first parity 710 received by the ith frame 702, and stored additional parity 712.
[111] A method for determining the number of bits of additional parity will be described in more detail below.
[112] According to an embodiment of the present invention, the number of bits of additional parity may be expressed using Equation (13).
[113]
…(13)[114] In Equation (13), α · I _{l} indicates the ratio of the number of bits of the first parity to the number of bits of additional parity, where α can be a constant value, I _{i} can be selected between 0 and L1, and L1 indicates the ratio of additional parity L1. I _{i} can be transmitted via a separate signaling "L1_AP_RATIO". When I _{i} = 0, bits of additional parity are not used. N _{tx_parity} indicates the number of parity bits transmitted by the same frame as the frame for the information word (i.e., first parity bits), and may also indicate the number of parity bits to actually be transmitted. In this case, N _{tx_parity} can be calculated as N _{parity}  N _{punc} .
[115] FIG. 8 is a diagram illustrating an LDPC code for supporting parity transmission in accordance with an embodiment of the present invention.
[116] Referring to FIG. 8, the LPDC codeword includes K _{ldpc} information bits 800 LDPC, N _{parity parity} bits 802 and M _{IR} parity bits 804 with increasing redundancy (IR). For convenience, the N _{parity parity} bits 802 and the M _{IR} parity bits 804 with IR are collectively referred to as parity bits in this document. The LDPC code structure illustrated in FIG. 8 is being designed with parity bits 802 in mind. Therefore, when excluded, parity bits 804 with IR are excluded. The LDPC code of FIG. 8 may be expressed as parity bits without distinguishing between parity bits 802 and parity bits 804 with IR.
[117] To encode the signal bits 806, the LDPC information bits 800 may include signal bits 806, parity bits 807 for the BCH code, and "0" fill bits 808 for reduction. Parity bits 802 and IR parity bits 804 include nonexcluded parity bits 810 and excluded parity bits 812. In this document, the exact position (i.e., index) of each bit is not essential for the subject of the present invention, namely, which bits between parity bits 802 and parity bits 804 with IR need to be excluded, and which bits between them should not be excluded. Accordingly, a specific exclusion pattern will not be described in this document.
[118] BCH parity bits 807 exist when a cascade code of a BCH code and an LDPC code is used, and BCH parity bits 807 will be discarded when only the LDPC code is used.
[119] The signal bits 806, BCH parity bits 807, and nonexcluded parity bits 810 form a first portion 814, which is transmitted later by the ith frame 702, as illustrated in FIG. 7. Some of the excluded parity bits 812 form an additional parity 816, which is transmitted later by the (i1) th frame 700, as illustrated in FIG. 7. That is, some of the excluded parity bits 812 are the same as the additional parities 807 and 712.
[120] Additional parity 708 may be determined in various ways. For example, excluded parity bits 812 may preferably be selected as supplementary parity.
[121] For K _{bch} = 2100, K _{ldpc} = 2160, N _{ldpc} = 4320 and M _{IR} = 4320, R _{ldpc} = K _{ldpc} / N _{ldpc} = 1/2 and R _{IR} = K _{ldpc} / (N _{ldpc} + M _{ldpc} ) = 1/4. In this case, in accordance with an embodiment of the present invention, N _{punc} can be calculated based on Equation 7 using Equation (14) below.
[122]
…(fourteen)[123] In Equation (14), A _{1} = 1.3, B _{1} = 3357, A _{2} = 1.35, B _{2} = 3320, and K _{th} = 1350. Therefore, N _{punc} parity bits based on Equation (14) are excluded from the parity bits 802 and the parity bits 804 with IR.
[124] According to another embodiment of the present invention, N _{punc} parity bits obtained based on the N _{punc_temp} in Equation (9) can be excluded using Equations (10) through (12).
[125] The exact parameter values used to calculate the N _{punc} can be determined in accordance with the modulation scheme used for transmission and the number of orthogonal frequency division multiplexing (OFDM) symbols. For example, when 2 ^{n} quadrature amplitude modulation (QAM) is used as a modulation scheme, the number of bits (K _{sig} + N _{bch_parity} + N _{parity} + M _{IR} N _{punc} ) that must be transmitted is a multiple of n. In this document, K _{sig} indicates the number of input bits of the signal information, N _{bch_parity} indicates the number of parity bits of the BCH code, and n indicates the order of the modulation scheme.
[126] The number of bits of additional parity 712 of FIG. 7 or additional parity 816 of FIG. 8 can be calculated using Equation (15).
[127]
…(fifteen)[128] In Equation (15), I _{0} = 0, I _{1} = 1, I _{2} = 2, and I _{3} = 3. In addition, α = 0.35 is used in Equation (13), where α is a value selected to satisfy Equation (16) below.
[129]
[130] ... (16)
[131] That is, α is defined as the maximum value among the values in which the sum of the number of bits of the first parity, N _{tx_parity} , and the number of bits of additional parity, N _{add_parity} , which are transmitted when I _{l} is the maximum value of I _{L1} and K _{sig} is the maximum length among the input information bits, K _{sig_max} , that is (N _{tx_parity} + N _{add_parity} ), is the maximum, and this amount is less (N _{parity} + M _{IR} ).
[132] When the maximum length among the input information bits, K _{sig_max} , is 2100, N _{punc} = 3320, so N _{tx_parity} = 3160, and when I _{l} is the maximum value I _{L1} = I _{3} = 3, N _{add_parity} = 0 , 35 × 3 × 3160 = 3318, so N _{tx_parity} + N _{add_parity} = 6478, which is less than N _{parity} + M _{IR} = 6480.
[133] An embodiment will be described below to obtain a more accurate N _{add_parity} taking into account the modulation scheme used for transmission based on N _{add_parity} obtained by the above equations.
[134] Equation (16) assumes that a BPSK modulation scheme is used. That is, α is determined so that the number of first parity bits and the number of additional parity bits transmitted using the BPSK modulation scheme is less than N _{parity} + M _{IR} . Therefore, when another modulation scheme is used, for example QPSK, 16QAM or 64QAM, a correction is required for N _{add_parity} so that the number of bits of the first parity and the number of bits of additional parity are less than N _{parity} + M _{IR} . Therefore, the number of intermediate bits of additional parity can be obtained using Equation (17).
[135]
... (17)[136] In Equation (17), K indicates an additional parity ratio L1 and is another expression I _{i} from Equations (13) and (15). According to an embodiment of the present invention, K may be transmitted from the transmitter to the receiver by means of L1_AP_RATIO signaling. For example, “L1_AP_RATIO” is a 2bit parameter, and when this parameter is “00”, K = 0; for parameter "01" K = 1; K = 2 for parameter "10"; and K = 3 for parameter "11".
[137] Considering the N _{add_parity_temp} from Equation (17) and the modulation order, the final number of bits of additional parity can be calculated using Equation (18a).
[138]
... (18a)[139] In Equation (18a), η _{MOD} indicates the modulation order, which is 1, 2, 4, and 6 for BPSK, QPSK, 16QAM, and 64QAM, respectively.
[140] The number of extra parity bits, N _{add_parity} , is adjusted in Equation (18a) to _{direct} N _{add_parity to} be a multiple of the number of columns in a block interleaver. Block interleaver is used when each bit of additional parity is interleaved bitwise.
[141] When the block interleaver is not used, for example, when only BPSK and QPSK are used, Equation (18a) can be converted to Equation (18b).
[142]
... (18b)[143] N _{add_parity} is determined in accordance with the number of OFDM symbols used for transmission.
[144] Information on the number of bits of additional parity may be transmitted from the transmitter to the receiver via the signal parameter "L1_AP_SIZE". If multiple encoded LDPC blocks are used for transmission, then L1_AP_SIZE indicates the product of the number of encoded blocks and N _{add_parity} . For example, when two coded blocks are used, L1_AP_SIZE may indicate 2 × N _{add_parity} . The receiver can find out the number of bits of extra parity from this signal parameter.
[145] FIG. 9 is a graph illustrating a code rate when the number of bits of additional parity is calculated using Equation (15), in accordance with an embodiment of the present invention.
[146] In particular, the code rate is calculated using Equation (19).
[147]
…(19)[148] In Equation (19), N _{tx_parity} indicates the number of parity bits in the first part 814 of FIG. 8, and N _{ldpc} + M _{IR}  N _{punc} = 6480N _{punc} . N _{add_parity} indicates the number of bits of additional parity in part 816 of FIG. 8.
[149] In FIG. 9 Additional parity (AP) = 0 corresponds to a code rate for I _{0} = 0, at which additional parity is not used, AP = 1 corresponds to a code rate for I _{1} = 1, AP = 2 corresponds to a code rate for I _{2} = 2, and AP = 3 corresponds to the code rate for I _{3} = 3.
[150] According to another embodiment of the present invention, IR parity bits 804 in the LDPC code of FIG. 8 can be used selectively. That is, parity bits 802 are preferably generated for bits of the input information word, and parity bits 804 with IR can only be generated when parity with IR is needed, thereby increasing the encoding / decoding efficiency.
[151] As described above, parity bits 802 are preferably generated for input information bits, and for parity bits 802, the N _{punc} can be calculated based on Equation (7), as shown in Equation (20).
[152]
…(twenty)[153] In Equation (20), if N _{punc} is a positive integer, then only parity bits 802 are generated, and only N _{punc} parity bits are excluded from the parity bits 802. However, if N _{punc} is a negative value, then parity bits 802 and parity bits 804 with IR are generated, and then only (M _{IR} + N _{punc} ) bits are _{excluded} from the parity bits 804 with IR.
[154] In accordance with another embodiment of the present invention, N _{punc} (obtained using Equations (10) to (12) based on Equation (20)) of parity bits is excluded.
[155] FIG. 10 is a flowchart illustrating a procedure for determining the number of two types of parity bits in accordance with an embodiment of the present invention.
[156] Referring to FIG. 10, in step 1000, the number of parity bits to be excluded is calculated using Equations (7) and (8) or Equations (9) through (12). At step 1002, the parameters α, I _{l} and N _{tx_parity are determined} , which are used in Equation (13), (15) and (17). At step 1002, the already defined α or I _{l} can be used, and I _{l} is expressed as K in Equations (17) and (18). As described above, K may be indicated by a separate signaling "L1_AP_RATIO".
[157] In step 1004, the number of additional parity bits, N _{add_parity} , is determined based on Equation (13) or Equations (17) and (18) using the parameters determined in step 1002. In step 1006, the additional parity bits are configured in accordance with the calculated number of bits of extra parity.
[158] FIG. 11 is a block diagram of a transmission side in accordance with an embodiment of the present invention.
[159] Referring to FIG. 11, the transmission side includes an encoder 1101 excluding a block 1103, a controller 1105, a modulator 1107, a radio frequency (RF) processor 1109 and, optionally, an additional parity configuration block 1111.
[160] Encoder 1101 outputs encoded bits generated by encoding bits of an information word for transmission. For example, when a BCH / LDPC code is used, encoder 1101 encodes BCH information bits containing K _{bch} bits to form a BCH codeword containing K _{ldpc} bits. After that, the encoder 1101 performs LDPC encoding on the BCH codeword, respectively generating and outputting the LPDC codeword containing N _{ldpc} bits.
[161] Alternatively, the encoder 1101 generates and outputs a codeword LPDC containing (N _{ldpc} + M _{IR} ) bits.
[162] Although not illustrated, BCH information bits containing K _{bch} bits can be configured by filling (K _{bch}  K _{sig} ) with the “0” bits K _{sig of the} input information bits. Filled (K _{bch}  K _{sig} ) "0" bits should not be transmitted.
[163] The exclusion block 1103 excludes the codeword provided from the encoder 1101 in accordance with the exception pattern and the exception bit length (K _{bch}  K _{sig} ) that are provided from the controller 1105. The controller 1105 calculates the exception bit length according to the number of information bits for controlling the exclusion block 1103. For example, the controller 1105 determines A and B in accordance with the number of input information bits (or the number of signal bits) for transmission on the transmission side and provides specific A and B exclusive in 1103.
[164] Alternatively, the controller 1105 obtains the number of bits that need to be excluded from certain parameters A and B and provides the exclusive unit 1103 with the received number of bits that need to be excluded. The modulator 1107 in accordance with the corresponding modulation scheme modulates and outputs the signal provided from the exclusion unit 1103. The RF unit 1109 converts the modulated signal provided from the modulator 1107 to a highfrequency signal and transmits a highfrequency signal via an antenna.
[165] If additional parity bits are to be transmitted, then the controller 1105 determines the number of additional parity bits, as illustrated in FIG. 10, and provides a certain number of bits of additional parity to block 1111 configuration of additional parity. The additional parity configuration unit 1111 configures the additional parity bits and provides them to the modulator 1107. It should be noted that the additional parities generated in the current frame are transmitted by the previous frame.
[166] Assuming the LDPC coding (N _{ldpc} , K _{ldpc} ), (K _{ldpc}  K _{sig} ) bits are shortened for the length of the input information bits K _{sig} . If the BCH code is cascaded, then the (K _{bch}  K _{sig} ) bits are shortened for the length of the BCH information bits K _{bch} .
[167] FIG. 12 is a block diagram of a receiving side according to an embodiment of the present invention.
[168] Referring to FIG. 12, the receiving side includes an RF unit 1200, a demodulator 1202, a reduction / exclusion processor 1204, a decoder 1206, a controller 1208 and, optionally, an additional parity processing unit 1210.
[169] The RF unit 1200 receives a signal transmitted from the transmission side RF unit 1109, and provides this signal to a demodulator 1202.
[170] A demodulator 1202 demodulates a signal provided from the RF unit 1200 using a demodulation scheme corresponding to the modulation scheme used in the transmission side modulator 1107. For example, demodulator 1202 obtains a logarithmic likelihood ratio (LLR) by logarithm the probability ratio that each bit is 1 to the probability that each bit is 0 for each of the reduced / excluded encoded bits and extra parity bits transmitted from modulator 1107 , and provides the LLR received to the reduction / exclusive processor 1204 and the additional parity processing unit 1210. An additional parity processor 1201 is optional in that it is not used when additional parity is not received.
[171] The abbreviation / exclusion processor 1204 receives the output signal of the demodulator 1202, generates values corresponding to the abbreviation and exclusion with respect to the bits abridged and excluded by the transmit side, and fills the output signal of the demodulator 1202 with these values. For example, for the abridged bit, the LLR value is ( +) or () the maximum value among the input values of the decoder, and for the excluded bit, the LLR value is "0". The abbreviation / exclusion processor 1204 receives information from the controller 1208 about the number of abbreviated and excluded bits and the index. That is, the controller 1208 calculates the length of the exception bits in accordance with the number of information bits of the transmit side encoder 1101 and controls the reduction / exclusion processor 1204.
[172] For example, the controller 1208 determines A and B according to the number of bits of signaling information for transmission on the transmission side, as illustrated in FIG. 6, and provides specific A and B to the abbreviation / exclusive processor 1204.
[173] Alternatively, the controller 1208 obtains the number of bits to be excluded from certain parameters A and B and provides the reducing / excluding processor 1204 with the obtained number of bits to be excluded. Information on the number of input information bits input to the encoder of the transmit side can be transmitted to the controller 1208 of the receiver through, for example, additional signaling.
[174] The decoder 1206 receives and decodes the output values of the reduction / exclusive processor 1204 to recover bits of the information word. For example, when a BCH / LDPC code is used, decoder 1206 receives N _{ldpc} or (N _{ldpc} + M _{IR} ) LLR values and performs LDPC decoding on them to recover K _{ldpc} bits, and then restores K _{bch} bits of the information word by BCH decoding.
[175] When the additional parity bits are transmitted, the controller 1208 determines the number of additional parity bits, as illustrated in FIG. 10, and provides a certain number of bits of additional parity to block 1210 processing additional parity. The additional parity processing unit 1210 receives LLR values for the additional parity bits generated by the transmit side from the demodulator 1202 and provides LLR values to the decoder 1206. The decoder 1206 decodes using the values provided from the reduction / exclusive processor 1204 and the values provided from the block 1210 processing additional parity. It should be noted that the additional parities received in the current frame are used when decoding the next frame in accordance with the processing at the transmitter. That is, when decoding the code received in the current frame, the additional parity bits received in the previous frame are used.
[176] In accordance with the abovedescribed embodiments of the present invention, by adaptively selecting a reduction / elimination rate based on the channel status information needed in the broadcast / communication system, similar efficiency is maintained regardless of the length of the information word, thereby maintaining system stability.
[177] Although the present invention has been shown and described in detail with reference to some of its embodiments, it will be understood by those of ordinary skill in the art that various changes in form and detail can be made therein without departing from the spirit and scope of the present inventions as defined by the following claims and their equivalents.
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RU2014112217A (en)  20151010 
IN2014CN02200A (en)  20150529 
JP5964969B2 (en)  20160803 
AU2012302460A1 (en)  20140306 
AU2012302460B2 (en)  20160908 
JP2014525710A (en)  20140929 
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