RU2604331C2 - Artificial neuron (versions) - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: invention relates to bionics and computer engineering and can be used as structural and functional element of artificial neural networks for simulating biological neural networks, as well as for designing of parallel neural computers and other computer systems for various applications, including tasks of image recognition, data classification, image processing, mathematical operations and creation of artificial intelligence. Device comprises information and modulating inputs, information outputs, computing core consisting of processor device, application non-volatile memory, random access memory and non-volatile data memory interacting through system bus.

EFFECT: technical result is providing most complete emulation of biological neuron functioning, as well as application versatility and multiplicity, which provides significant saving of hardware resources.

5 cl, 3 dwg

Description

The invention relates to bionics and computer engineering and can be used as a structural and functional element of artificial neural networks for modeling biological neural networks, as well as for building parallel neurocomputers and other computing systems designed to solve various applied problems, including image recognition problems , data classification, image processing, mathematical operations and the creation of artificial intelligence.

Known artificial neuron and method of its use (patent EP 0629969, published 21.12.1994), where the artificial neuron as a central element contains a multiplier that multiplies the incoming signals, synaptic weight and generates an output signal.

The disadvantage of this artificial neuron is that it is a processor device with a hardware-implemented algorithm of operation, incapable of implementing adaptive behavior, which, in turn, is characterized by determining the type of incoming signals, the ability to memorize the synapse weights and briefly store incoming information signals with subsequent attenuation . Thus, this device has great limitations in terms of the complete emulation of the functioning of a biological neuron. The rigidly embedded algorithm also makes this device highly specialized, not having the ability to modernize the functioning algorithm without changing the electronic circuitry of the device.

Known artificial neuron (US 7672918 from 02.03.2010), which is a processor device having several signal inputs, a threshold value input and one output.

The disadvantage of this artificial neuron is that it is a highly specialized processor device with a hardware-implemented functioning algorithm, incapable of implementing adaptive behavior and fully emulating the functioning of a biological neuron.

The closest analogue of the invention is an artificial neuron (patent US 7080054 from 07/18/2006), designed to simulate a biological neuron. The device is equipped with information inputs, which are divided into exciting and inhibitory types, a modulating input and one output of the action potential. The device is implemented on CMOS transistors.

The disadvantage of this device is also the highly specialized for a specific functioning algorithm, the lack of adaptive behavior that allows you to adjust and memorize synaptic weights for a short or long time, which is the basis for organizing short-term or long-term memory of a neural network close to a biological prototype. Also, a significant drawback in terms of emulating a biological neuron is that the logic is implemented in hardware, which prevents its modification, which, in turn, excludes the possibility of organizing heterogeneous neural networks and changing the functioning algorithm.

The objective of the invention is the creation of a universal programmable artificial neuron with the ability to individually configure parameters (number, types and weights of synapses; time parameters of incoming and outgoing signals, thresholds, etc.) and repeatedly change the functioning algorithm by reprogramming.

The technical result of the claimed invention consists in the possibility of programming and reprogramming each elementary artificial neuron that is part of an artificial neural network to perform a particular functioning algorithm, which in turn expands the functionality in terms of implementing various types and models of neural networks, as well as provides wide independence of the functioning algorithm from the hardware architecture of the artificial neuron and makes it possible without changing the electronic circuit or structure of the neural network, create functionally both homogeneous neural networks where all neurons have the same functioning algorithms and heterogeneous neural networks where all or several neurons have different functioning algorithms.

The task and technical result are achieved due to the fact that the claimed artificial neuron is an electronic computer, containing, in addition to information and modulating inputs, information outputs, a computing core consisting of a processor device, non-volatile program memory, random access memory and non-volatile data memory interacting between by itself through the system bus.

The proposed artificial neuron is universal, i.e. allows you to create an artificial neural network of any type, including perceptrons, cognitrons, recurrence networks, convolutional networks, Hopfield networks, Kohonen networks, spike networks, etc.

The proposed artificial neuron has one or more information inputs, one or more modulating inputs and one or more information outputs. Through informational and modulating inputs and informational outputs, an artificial neuron is connected to other artificial neurons or other devices for data exchange, forming an artificial neural network.

The computing core of the proposed artificial neuron may include analog-to-digital converters on information and modulating inputs and digital-to-analog converters on information outputs, which allows the claimed device to work with analog signals. Also, information inputs and modulating inputs can receive signals through optical receivers, and information outputs can transmit signals through optical transmitters. This provides the artificial neuron with the ability to receive and transmit data through optical communication channels, for example via fiber optic lines.

The processor device executes machine instructions written in the form of program code, and can have any possible architecture, including CISC, RISC, MISC, URISC.

Non-volatile program memory stores machine program code that implements an artificial neuron functioning algorithm.

RAM allows you to store the executable machine code of the program, as well as input, output and intermediate data processed by the processor device, including a short-term value of the output signal level.

Non-volatile data memory provides long-term storage of data, including long-term value of the output signal level.

In turn, the structure of non-volatile program memory, non-volatile data memory and RAM can be organized according to any possible architecture, including von Neumann and Harvard.

The system bus provides data exchange between information and modulating inputs, information outputs, a processor device, non-volatile program memory, random access memory and non-volatile data memory.

The artificial neuron functioning algorithm can be set entirely in a loaded program or partially set in a loaded program and partially in the form of a logical structure of a computing core.

The invention is illustrated in scheme 1 and scheme 2.

In diagram 1 is a structural diagram of the inventive device.

The circuit contains the following blocks:

Information inputs - 1;

Modulating inputs - 2;

Information outputs - 3;

Computing core - 4;

Processor device - 5;

Non-volatile program memory - 6;

RAM - 7;

Non-volatile data memory - 8;

System bus - 9.

Figure 2 shows a structural diagram of the inventive device with the presence of analog-to-digital converters and digital-to-analog converters:

Analog-to-digital converter - 10;

Digital-to-analog converter -11.

Figure 3 gives a structural diagram of the inventive device with the presence of optical receivers and optical transmitters:

Optical receivers - 12;

Optical Transmitters -13.

The inventive device is implemented as follows. The computing core (4) is powered. The program describing the functioning algorithm of an artificial neuron, which is a sequence of machine instructions, is loaded into the non-volatile memory of program (6). Data exchange between all nodes of the computing core is carried out through the system bus (9). The program is read by the processor device (5) for subsequent execution.

According to the standard algorithm for the functioning of a neuron, the signal received at the information input (1) is recognized by the processor device (5) as a type and, depending on the recognition result, classified into an exciting or inhibitory data type, its level is determined.

In the same way, signals are processed at other available information inputs (1).

The levels of the inhibitory and exciting signals received at the information inputs (1), which are lower than the action potential generation threshold, are stored by the processor device (5) in the memory cells (7) with subsequent attenuation. The sensitivity of the information input (1), the typology of the incoming signals and the attenuation rate of their levels are set in the program in the form of constants.

If the signal is available at only one information input (1) and the received signal is exciting and has a level equal to or higher than the threshold for generating an action potential, then processor device (5) proceeds to generate an output signal called an action potential.

The threshold value at which an artificial neuron generates an action potential is specified in the program as a constant.

If signals are available at several information inputs (1) or subsequent signals arrived before the first incoming signal is completely attenuated, then the processor device (5) performs an algebraic summation of the incoming signals, the essence of which is to calculate the difference between the sums of the exciting and inhibitory signals. If the result of the summation of the signals is equal to or higher than the threshold for generating the action potential, then the processor device (5) proceeds to generate the action potential.

Then, the processor device (5) interrogates the modulating inputs (2). Each modulating input (2) controls its specific information output (3). If there is no signal at the modulating input (2), then the signal of the generated action potential is output to the information output (3) without changes based on the current level settings of this information output (3).

If there is a signal at the modulating input (2), the signal is recognized by type, classified, its level is determined and, depending on this level, the processor device (5) modulates the level of the action potential and outputs it through the information signal dependent on this modulating input (2) output (3). The modulation level for this information output (3) is stored by the processor device (5) in the RAM (7) for a certain short time, then the level comes to the initial settings. If a signal of one level is periodically repeated a predetermined number of times on one modulating input (2), then the modulation level of the dependent information output (3) is stored by the processor device (5) in a non-volatile data memory (8). Thus, short-term and long-term memory of a biological neuron is emulated.

After modulation is completed, the action potential is output through the information outputs (3).

When implementing the inventive device equipped with analog-to-digital (10) and digital-to-analog converters (11), an artificial neuron receives analog signals through information inputs (1) and modulating inputs (2). After that, the analog signal enters the analog-to-digital converter (10) and is digitized. The digitized signal enters the processor device (5) and is processed as described above, and the output signal of the generated action potential enters the digital-to-analog converter (11) and is converted into an analog signal, which is output through the information outputs (3).

When implementing an artificial neuron that receives and transmits data via optical communication channels, incoming signals are transmitted through the optical communication channel in the form of light to the input optical receiver (12), which is a photocell, and the output signal of the generated action potential is fed to the optical transmitter (13), which is a light emitter that converts a signal into light.

Thus, the claimed invention provides the most complete emulation of the functioning of a biological neuron, and its versatility and repeated use gives significant savings in hardware resources.

Claims (5)

1. An artificial neuron containing information inputs, modulating inputs, information outputs and a computational core operating according to a certain functioning algorithm and consisting of a processor device, non-volatile program memory, random access memory and non-volatile data memory interacting via the system bus. 2. The artificial neuron according to claim 1, characterized in that the computational core includes analog-to-digital converters at the information inputs and modulating inputs and digital-to-analog converters at the information outputs. 3. The artificial neuron according to claim 1, characterized in that the computing core includes optoelectronic receivers at the information inputs and modulating inputs and optoelectronic transmitters at the information outputs. 4. The artificial neuron according to claim 1, characterized in that the functioning algorithm is specified by the program loaded into the non-volatile memory of the program. 5. The artificial neuron according to claim 1, characterized in that the functioning algorithm is determined by the logical structure of the computing core, and the program loaded into the non-volatile memory of the program sets the variables and constants necessary for functioning.

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