RU2585988C1 - Device for encrypting data (versions), on-chip system using (versions) - Google Patents

Abstract

FIELD: information technology; cryptography.

SUBSTANCE: device for encrypting data according to GOST 28147-89 is characterised by that it includes direct memory access controller for loading data array of memory for encrypting data encryption device and preservation of crypto converted data back into memory, computing unit with possibility of implementing data encryption in accordance with selected algorithm, data registers for storing lookup table, data registers for storage of encryption keys, registers for initialisation vectors storing and message authentication code, as well as control unit.

EFFECT: faster data crypto conversion processes.

12 cl, 6 dwg

Description

The invention relates to data encryption devices that can be used as part of computing systems, for example, systems on a chip (SoC) for encrypting data coming from the Internet, from hard drives or from other information storages.

State of the art

The invention is known according to the patent of the Russian Federation 2412479 (copyright holder Siemens, IPC G06F 21/00 G06F 1/00, 2006) relating to an integrated data protection system containing a functional encryption module by which data or program codes can be encrypted and decrypted, while the scheme assumes both the possibility and the lack of the ability to store keys in it, a built-in real-time clock to control frequency changes, an integrated power source for destroying keys. In the known solution for encryption, separate computing devices are used as part of a single integrated circuit. The known solution is the closest to the claimed invention a device of the same purpose, however, it has significant disadvantages due to the fact that:

a) at the hardware level, it does not support the execution of individual encryption algorithms, such as: simple replacement mode, gamming and gamming modes with feedback, as well as the mode of generating an insert (these modes are provided, for example, GOST 28147-89),

b) it has a single mode of operation: reading data from memory, encrypting and writing the result to the internal register of the central processor or the built-in cache memory;

c) it does not provide a mode of operation with stream encryption of data located in external memory (for example, external RAM), followed by the placement of decrypted / encrypted data back into external RAM, as provided for in the claimed device;

d) there is no possibility of reducing the total time required for encrypting the data array, which is carried out in the claimed solution, which was made possible thanks to a scheme that directly specifies the reduction of the total time required for encrypting the data array by using built-in equipment that allows the simultaneous transfer of data from memory to encryption / decryption with the subsequent return of the encryption results back to memory.

Other well-known computing systems without the encryption device of the present invention carry out a process of encrypting data by software using only the resources of the central microprocessor.

Disclosure of invention

The claimed solution is a data encryption device (2 options), implemented as an integrated circuit with functional modules, and SoC using it (2 options).

The encryption device works in the following cryptographic conversion modes, namely: in the simple replacement mode, in the gamming and gamming modes with feedback, in the replacement mode with engagement, as well as in the mode of generating an insert. These modes can be used to implement a symmetrical block encoder that uses the technology of replacing open data with other elements according to certain rules (for example, in accordance with GOST 28147-89).

In the description of the invention, by encryption we mean the process of cryptographic conversion (either encryption or decryption) of data occurring in the encryption device. The symmetry property means using the same secret key for encryption and decryption. The difference is only in the sequence of application of the various components of the key during encryption and decryption. This sequence is determined algorithmically and does not change. These algorithms implement the block type of encryption, which means that the array of encrypted data is divided into blocks of the same size. The processing of each block is carried out similarly to each other.

The encryption device (7) can receive data from any available information storage in a format that meets the requirements for the algorithms implemented in the claimed invention, for example, in blocks of 64 bits each, from (external to the encryption device) memory (6) (for example , serial RAM) connected via a standard interface. After the end of the operation, the encryption device (7) sends the crypto-converted data back to the memory (6) (to the recipient, for example, to serial RAM) connected via a standard interface.

The purpose of creating an encryption device is to increase the speed of cryptographic data conversion processes using the simple replacement mode, gamma and gamma modes with feedback, replace mode with engagement, and the mode of generating an insert. Improving the performance of cryptographic data conversion processes (encryption acceleration) is achieved through the use of separate computing devices that process streaming data directly from external memory in relation to the encryption device as part of the encryption device, and not by using specialized software that uses the resources of the central processor, especially if This encryption device is used as part of SoC.

In this case, the encryption acceleration in the claimed encryption device (7) is achieved due to the following factors:

1) Unlike the standard approach, the encryption device provides data encryption without the direct involvement of the central processor, thereby freeing its resources for other operations. When using the claimed encryption device (7) as part of the SoC, the central processor plays the role of a system arbiter when the device is turned on and off, controls interrupts and is responsible for managing its operation modes. Autonomous operation of the encryption device (7) from the central processor is ensured by the controller (4) integrated in the SoC, which provides direct access to the memory.

2) The encryption of each data block is performed sequentially, in particular, satisfying the requirement for the operation of block encryption algorithms implemented in this device. In the claimed solution, the cryptoconversion time of one block is fixed, independent of the load on the central processor of the SoC.

3) Data for encryption and encryption results can be transferred (see Fig. 1, 2) between the internal switching unit (3), the direct memory access controller (4) and the computing device (8) or devices (8), (9) depending on the adopted configuration of the encryption device (7) via internal buses (12), (13), (14), (15), (16) in packets consisting of frames. The frame size corresponds to the size of the block of processed data (for example, 64 bits), its size remains unchanged during operation. The frames from the packet are also transmitted to computing devices by the stream, ensuring the uninterrupted operation of the encryption process.

4) The internal switching unit (3) is capable of simultaneously transmitting data in both directions: to the controller (4) of direct access to and from the memory. Data can be accumulated in the controller's built-in repositories (4) to eliminate delays that may occur when working with external memory.

5) To provide encryption, either one computing module (8) (Fig. 1, 5) or two independent computing modules (8) and (9) (Figs. 2, 6) can be included in the encryption device (7). The computing module (8) is used to implement the basic encryption cycle in accordance with the selected mode of operation, if only one is present in the encryption device (7), while it is used sequentially both to calculate the result of encryption of the data block and to calculate the insert (Fig. . fifteen). When using two independent computational modules (8) and (9), both the result of encrypting the data block using the base cycle module (8) and the result of generating the insert using the module (9) to generate the insert (II) are simultaneously calculated (Fig. 2 , 6). The use of a separate computing unit (9) for generating an imitation insert can further improve the performance of the entire encryption device (7) due to the fact that the main computing module (8), in this case, is used only for the encryption process.

The encryption algorithms supported in the claimed device contain the requirement of recursive block processing of the data array, in other words, the encryption of the next block requires the result of processing the previous one. Using well-known approaches, the total execution time of the encryption process increases in direct proportion to the amount of encrypted data.

The claimed encryption device (7) allows not only to reduce the encryption time, but also to reduce the cost of software resources of the SoC, in which it can be used, in particular, to isolate secret keys used in the process of data encryption from crypto attacks and usually stored in main memory on a universal basis. Private keys in this case are stored in the internal registers (18) of the encryption device (7), which do not allow the reading of their contents by software.

SoC, working using the device (7) described in this application in 2 versions, can significantly reduce the execution time of the encryption process in comparison with known computing systems in which the data encryption process is carried out by software using the resources of the central microprocessor. In such systems, the processing of each data block requires the execution of a small subroutine that loads the data, performs the necessary calculations, and records the result of the crypto conversion.

The claimed SoC (1) (2 options), which includes the claimed encryption device (in 2 versions), is a system on a chip (SoC) with the possibility of using internal memory (6) with respect to the SoC (which is part of the SoC) (according to the first option - Fig. 1, 5) or external memory (6) with respect to the SoC (connected to the SoC via the standard interface according to the second option - Fig. 2, 6) (for example, as a memory, serial RAM can be used in both cases. SoC includes:

- a general purpose central processing unit (2) that can execute programs;

- encryption device (7), thanks to which data can be encrypted and decrypted;

- internal switching unit (3), which provides data exchange between system elements;

- memory access controller (5) (6).

Brief Description of the Drawings

FIG. 1 - SoC architecture using the claimed encryption device (7) (using the first embodiment of the encryption device) based on one computing module (8), when the memory is external to the SoC.

FIG. 2 - architecture of the SoC using the claimed encryption device (7) (using the second version of the encryption device), including an additional computing module (9) for generating an insert when the memory is external with respect to the SoC.

FIG. 3 is a diagram of the operation of the encryption device (7) of the present invention.

FIG. 4 - description of a simple replacement mode with engagement during encryption (a) and decryption (b).

FIG. 5 - SoC architecture using the claimed encryption device (7) (using the first embodiment of the encryption device) based on one computing module (8), when the memory is internal memory included in the SoC.

FIG. 6 - SoC architecture using the claimed encryption device (7) (using the second version of the encryption device), including an additional computing module (9) for generating an insert when the memory is internal memory included in the SoC.

The implementation of the invention

The claimed device for encrypting (7) data according to algorithms, simple replacement, simple replacement with engagement, gamming and gamming with feedback, as well as calculating an insert, includes a direct memory access controller (4) (6), which provides data for encryption from memory external to the encryption device (6) (e.g., serial RAM), which can be used in the particular case of the invention considered in two ways below, but without limiting it only to the cases considered using the used memory, into the encryption device (7) and encrypted or decrypted data from the encryption device (7) back to the memory (6) (for example, sequential RAM, which can be either external to the SoC or enter the SoC), a computing module (8) that provides data encryption in accordance with the selected mode of operation, a module for calculating the self-insert (9) (this module is not used in the encryption device (7) according to the first embodiment), as well as control registers that store information necessary for the encryption register, (17) (for example, 512-bit), into which the substitution table is loaded, register (18) (for example, 256-bit), in which the encryption key is loaded, register (19) (for example, 64 -bit), into which the initialization clock vector is used, which is used for encryption in the gamming and gamming modes with feedback, as well as register (20) (for example, 64-bit), into which the initialization vector of the insertion code is loaded. The above devices are interconnected as shown in FIG. 1, 5 (for the first embodiment of the encryption device (7)) and in FIG. 2, 6 (for the second embodiment of the encryption device (7)). As a controller (4) for direct memory access, which simultaneously processes requests for reading / writing data from / to memory, a well-known (IP) solution from Synopsys or other equipment can be used, the main requirement for which is the possibility of simultaneous operation of the channel reading data from the memory (6) (for example, internal or external serial RAM) to the encryption device (7) and the channel for writing crypto-converted data from the encryption device (7) back to the memory (6) (for example, serial RAM). To transfer data for encryption to computing modules (8) and (9), the address-data bus (14) can be used, for example, satisfying the ANV (Advanced High-performance Bus) standard. To transfer crypto-converted data to the direct access controller (4) in memory (6), an address-data bus (15) can be used that satisfies, for example, the ANV (Advanced High-performance Bus) standard. Computing module (8) has the ability to implement algorithms that provide the implementation of simple replacement mode, gamma mode and gamma mode with feedback provided, for example, GOST 28147-89.

- «исключающее ИЛИ»). Этот режим отличается от режима простой замены, который описан, например, в ГОСТ 28147-89, тем, что каждый следующий блок данных перед началом обработки «зацепляется» с результатом, полученным при обработке предыдущего блока данных, путем сложения по модулю 2, как представлено на фиг. 4.For encryption in the simple replacement with engagement mode, the computing (8) module is supplemented by equipment for addition modulo 2 (operation

- “exclusive OR”). This mode differs from the simple replacement mode, which is described, for example, in GOST 28147-89, in that each subsequent data block before the start of processing is “hooked” with the result obtained by processing the previous data block by adding modulo 2, as shown in FIG. four.

To optimize the encryption process, the encryption device (7) according to the second embodiment is supplemented by a computing module (9), which has the ability to parallelly implement the algorithm for generating an insert (provided, for example, GOST 28147-89).

The encryption device includes a control unit (21), which is implemented as a state machine, which is in a state of waiting for a command to be transferred, which transfers the encryption device (7) to one of the operating modes. By selecting the operating mode of the encryption device (7) presented in this invention, it is understood that one of the encryption algorithms is activated by programming the control unit (21) in the encryption device (7).

After setting one of the operating modes, the encryption process begins. At the end of the encryption, the central processor (2) puts the encryption device (7) back into standby mode.

The control unit (21) also generates control and status signals necessary for the operation of the encryption device (7). At least the following types of signals are generated:

operation status of the encryption device (7) (encryption completed / encryption continues);

- signals that control the transfer of data to computing devices (8), (9) from the controller (4) and cryptoconverted data back to the controller (4), satisfying, for example, the standard of the ANV (Advanced High-performance Bus);

- signals that control the writing and reading of data to / from the control unit (a) (21), satisfying, for example, the ARV standard (Advanced Peripheral Bus).

To transfer data for encryption to computing modules (8) and (9), the address-data bus (14) can be used, for example, which satisfies the ANV standard. To transfer crypto-converted data to the direct memory access controller, the data-address bus (15) can be used, for example, satisfying the ANV standard.

Computing modules (8), (9) are connected to the registers (17), (18), (19), (20) and the control unit (21) for unidirectional or bi-directional data buses, for example, 64 bits wide.

Depending on the performance requirements, the encryption device (7) may not contain a computing device dedicated only to calculate the insert (9), as shown in FIG. 1. Part of the encryption algorithms implemented in the claimed invention of the device (7) does not require the calculation of an insert, therefore, such an implementation may be the best option.

If the user wants to carry out encryption with the calculation of the insert, the encryption device (7) (Fig. 1) can be switched to the mode accompanied by the calculation of the insert, and its calculation will be performed in the computing device (8) after the end of the main encryption process. The control unit (21) redirects the corresponding operands to the computing device (8). The result of computing the insert, regardless of the configuration of the encryption device (7), is stored in the data register (20).

The operation algorithm of the data encryption device (7) is presented in general form in FIG. 3. The encryption device (7) is in the standby mode of the arrival of control commands.

Before setting the active mode of operation of the device (7), condition-1 is checked as to whether updating the replacement table in the register (17), which is used for encryption in accordance with the standard GOST 28147-89, is required. By default, the control unit (21) can store the standard value of the replacement table. If “Yes”, then the table is loaded, if “No”, then condition-2 is further checked as to whether the encryption key needs to be loaded into the register (18). In the general case, the same key can be used for several data blocks and its updating is not required. If “Yes”, then the key is loaded, if “No”, then condition-3 is checked further as to whether it is necessary to load the initialization clock vector into register (19), which is used only in part of the operating modes provided for by the standard GOST 28147-89. If “Yes”, then the sync vector is loaded, if “No”, then condition-4 is further checked as to whether the initialization vector of the insert must be loaded into register (20), used only in part of the operating modes provided for by the standard GOST 28147-89. If “Yes”, then the insert vector is loaded, if “No”, then the encryption working mode is set further.

Next, condition-5 is checked as to whether the operation mode with direct memory access is set.

If the mode of operation with direct access to memory is set (6), then the central processor (2) performs programming of the controller (4) with at least an address in memory from where the data for encryption must be downloaded, addresses in memory, at which crypto-converted data must be saved, and the size of the data array for encryption. Then, as data is received from the memory, they arrive in blocks in a computing device (8) or device (8), (9), depending on the operating mode and configuration of the encryption device (7). After encryption, the data is transferred back to memory at a known address. Then, condition-6 is checked as to whether the block just processed is the last in the data array. If “Yes”, then the encryption device finishes its operation and waits for a command from the central processor (2), which puts the encryption device (7) into standby mode, if “No”, then the next data block is processed as described above.

If the mode is set without direct access to the memory, then the encryption device (7) expects the central processor (2) to download the data block for encryption, according to the set operation mode. At the end of the encryption, the encryption device (7) expects a command from the central processor (2) to read the crypto-converted data. After reading the result, the device is put into standby mode.

Claimed SoC (1) using a data encryption device (7) and with the ability to access the memory included in the SoC (internal), or memory that can be connected to SoC using the standard protocol (external), in the particular case as any memory serial RAM (6) can be used, in addition to the encryption device (7) it includes a central processor (2), through which programs can be executed and external interrupts can be processed, an internal switching unit (3) that provides information exchange (yes) GOVERNMENTAL) between the functional blocks of SOC (1) according to a common protocol between the device (7) encryption, the CPU (2) and memory (6) through a standard controller (5) a memory (6). As an internal switching unit (3) and as a memory controller (5), well-known (IP) solutions from Synopsys can be used. Data exchange between the central processor and the rest of the SoC nodes is carried out through the internal switching unit using the address-data bus, for example, satisfying the Advanced extensible Interface (AXI) standard.

The functioning of the SoC (1) is carried out by programming the central processor (2), for which, for example, the MIPS P-5600 microprocessor system from Imagination Technologies can be used and the commands from which are transmitted through the configuration interface (11), which includes at least the address bus, data bus and control bus of the transmitted information. The control signals are sent to the controller (4) direct access to the memory and to the control unit (21) of the encryption device (7).

Similar to the control of the operating modes of the control unit (21), which is part of the encryption device (7), through the commands from the central processor (2), the controller (4) for direct access to the memory is programmed, setting the addresses where it is necessary to take data for encryption from the memory (6) (for example, external or part of the SoC of serial RAM) and return (save, send) back to the memory (6) data crypto-converted by the encryption device (7), and the rules for generating interrupts at the end chi data to / from the memory (6).

When using both versions of the encryption device (7) as part of the SoC, the encryption result is accumulated in the control unit (21) of the encryption device (7) and, depending on the selected operating mode, is sent back to the memory (6) (for example, an external or sequential SoC component) RAM) through the controller (4) direct access to the memory, or stored in the control unit (21), waiting for a request to "read" from the central processor (2), when using an encryption device as part of a computing system. The result of the development of the insert is also read on request from the central processor (2) from the corresponding register (20). In this case, the address-data configuration bus (11) can be used to control the operation of the encryption device, for example, satisfying the ARV standard. To transfer crypto-converted data to the internal switching unit, the address-data bus (12) can be used, for example, satisfying the AXI standard. To transfer data for encryption to the direct memory access controller (4), the address-data bus (13), for example, satisfying the AXI standard, can be used. To transfer data for encryption to computing modules (8) and (9), the address-data bus (14) can be used, for example, which satisfies the ANV standard. To transfer crypto-converted data to the direct memory access controller (4), an address-data bus (15) can be used, for example, satisfying the ANV standard. Data from the memory is transferred to the memory controller (5) and back via the standard interface. To transfer data to / from the memory controller (5) to / from the internal switching unit (3), the address-data bus (16), for example, satisfying the AXI standard, can be used.

Depending on the operating mode of the encryption device (7), the data for encryption can either be received in streaming form directly from the memory (6) (for example, serial RAM) through the direct memory access controller (4), or received as a single data block by command CPU (2). In the latter case, the result of the crypto conversion becomes available to the central processor for reading through the internal switching unit. In the case of a streaming operation mode, preliminary programming of the controller (4) is required with the address at which the data is located in memory (6) (in external or part of the SoC serial RAM), the address at which the crypto-converted data should be stored (sent) back into memory (6), as well as data size for crypto conversion. In the case of a single block of data loaded into the encryption device (7) by the command of the central processor, preliminary programming of the controller (4) is not required.

When using the first embodiment of the encryption device shown in FIG. 1, we obtain the first variant of SoC, and when using the second version of the encryption device shown in FIG. 2, we obtain the second version of SoC. The functioning of the SoC in both cases is carried out similarly, with the exception of the encryption processes occurring in the encryption device (7). In this case, the second version of SoC is preferable to use to speed up the encryption process in the modes accompanied by the calculation of the self-insert using the encryption unit (9) of the encryption device (7), which allows it to be computed in parallel with the main encryption process occurring in the computing unit (8).

As the memory (6) for both embodiments of the encryption device (7) and the SoC using these options, an external serial RAM (for example, SRAM, DDR, DDR2, DDR3, etc.) can be used.

The main scope of the device is secure connections using TLS (Transport Layer Security - a cryptographic protocol that provides secure data transfer between nodes on the Internet). The invention can also be widely applied in SoCs, controllers that encrypt data coming from the Internet or on hard drives.

Claims (12)

1. The data encryption device according to GOST 28147-89, characterized in that it includes a direct memory access controller that provides loading of the data array from the memory for encryption by the data encryption device and storing the crypto-converted data back to memory, a computing unit with the ability to implement data encryption in accordance with the selected algorithm, data registers for storing lookup tables, data registers for storing keys for encryption, registers for storing synchronization vectors and and plug-ins, as well as the control unit. 2. The data encryption device according to claim 1, characterized in that the memory uses serial RAM connected via a standard interface. 3. A data encryption device according to GOST 28147-89, characterized in that it includes a direct memory access controller that provides loading an array of data from memory for encryption by a data encryption device and storing crypto-converted data back to memory, a computing unit with the ability to implement data encryption in accordance with the selected algorithm, an additional computing unit designed to calculate the insertion parallel to the main encryption process, data registers for storage eniya lookup tables, data registers for storing keys for encrypting registers for storing vectors and sinhroposylki authentication code, and a control unit. 4. A data encryption device according to GOST 28147-89 according to claim 3, characterized in that a serial RAM connected via a standard interface is used as memory. 5. The system on a chip (SoC) for data encryption according to GOST 28147-89, characterized in that it includes a data encryption device according to GOST 28147-89 according to claim 1, a central processor that controls the operation of the entire system as a whole, internal memory , an internal switching unit that provides the ability to exchange data via a single protocol through the address-data bus between the encryption device, the central processor and the internal memory, while the data for encryption is received in the encryption device from the internal memory through MODULES memory, converts the serial data into a format used inside the switching unit, and the result kriptopreobrazovaniya directed into the internal memory of the encrypting device through an internal switching unit and a memory controller. 6. The system on a chip (SoC) for data encryption according to GOST 28147-89 according to claim 5, characterized in that serial memory is used as memory. 7. A system on a chip (SoC) for data encryption according to GOST 28147-89, characterized in that it includes a data encryption device according to GOST 28147-89 according to claim 1, a central microprocessor that controls the operation of the entire system as a whole, an internal unit switching, providing the ability to exchange data via a single protocol through the address-data bus between the encryption device, the central processor and external memory, while the data for encryption is received in the encryption device from the external memory through the memory controller, odyaschy SoC part and converting the received serial data into a format used inside the switching unit, and kriptopreobrazovaniya result is sent from the encryption device into the external memory via internal switching unit and a memory controller. 8. The system on a chip (SoC) for data encryption according to GOST 28147-89 according to claim 7, characterized in that the memory uses a serial RAM connected via a standard interface. 9. The system on a chip (SoC) for data encryption according to GOST 28147-89, characterized in that it includes a data encryption device according to GOST 28147-89 according to claim 3, a central microprocessor that controls the operation of the entire system as a whole, internal memory , an internal switching unit that provides the ability to exchange data via a single protocol through the address-data bus between the encryption device, the central processor and the internal memory, while the data for encryption is received in the encryption device from the internal memory Through a memory controller that converts serial data to the format used by the internal switching unit, and the result of the crypto conversion is sent to the internal memory from the encryption device through the internal switching unit and the memory controller. 10. The system on a chip according to claim 9, characterized in that serial memory is used as the memory. 11. The system on a chip (SoC) for data encryption according to GOST 28147-89, characterized in that it includes a data encryption device according to GOST 28147-89 according to claim 3, a central microprocessor that controls the operation of the entire system as a whole, an internal unit switching, providing the ability to exchange data via a single protocol through the address-data bus between the encryption device, the central processor and external memory, while the data for encryption is received in the encryption device from the external memory through the memory controller, which is part of the SoC and converts the incoming serial data to the format used by the internal switching unit, and the result of the crypto conversion is sent from the encryption device to the external memory through the internal switching unit and the memory controller. 12. A system on a chip for encrypting data according to GOST 28147-89 according to claim 11, characterized in that the memory uses serial RAM connected via a standard interface.

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