RU2549134C1 - Device for decoding ldpc codes - Google Patents

Abstract

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to computer engineering and telecommunication systems. The device for decoding LDPC codes includes: a control device, first through third memory units, an arithmetic unit, first and second stacks, first through fifth counters, a first latch register, a T flip-flop, first through sixth switches, a code comparator circuit, first and second AND elements, a first adder.

EFFECT: high throughput of LDPC code device due to the exclusion of codeword symbols, reliability of which is higher than a given threshold, from LDPC code checking levels at each iteration of the decoding algorithm.

2 cl, 3 dwg

Description

The invention relates to telecommunication systems and computer technology and may find application in devices for receiving information from a transmission channel or reproducing information with a high level of errors.

A known device for decoding LDPC codes (see US patent 7181676. IPC ⁷ H03M 13/45. Layered decoding approach for low density parity check (LDPC) codes / Dale E. Hocevar - claimed 11.02.2005 No. 11/056755; publ. 20.02 .2007), containing: random access memory, adders, check update blocks, symbol update blocks, direct permutation block, reverse permutation block.

The known device implements an iterative decoding algorithm in layers, which allows to improve the convergence of the algorithm.

The disadvantage of this device is the relatively high computational complexity of the algorithm used, which limits its application.

The closest in technical essence to the claimed invention is a prototype device for decoding LDPC codes (see US 2005/0283707. IPC ⁷ H03M 13/00. LDPC decoder for decoding a low density parity check (LDPC) codewords / Eran Sharon, Simon Litsyn - announced 02/18/2005 No. 11/061232; publ. 12/22/2005), comprising: two random access memory blocks, test node processors, a switching circuit, read-only memory that stores the graph structure, a convergence check block.

The prototype device performs the sequential decoding of LDPC codes, correcting a larger number of errors.

The disadvantage of the prototype can be considered relatively large computational complexity of the decoding algorithm.

An object of the invention is to reduce the computational complexity of the decoding algorithm used, which provides lower hardware costs and a higher decoder throughput.

The stated technical problem is solved in that in the device for decoding LDPC codes containing the first and second memory blocks, according to the invention, a third memory block, an arithmetic device, first and second stacks, first to fifth counters, a first register latch, a T-trigger, first to sixth switches, code comparison circuit, first and second AND elements, first adder, wherein the second inputs of the sixth switch are inputs of the LDPC code decoding device, the outputs of the sixth switch are connected to the data inputs of the first block The outputs of the first memory block are connected to the data inputs of the first stack, to the first data inputs of the arithmetic device and the second inputs of the code comparison circuit, the outputs of the first stack are connected to the second data inputs of the arithmetic device, the outputs of the arithmetic device are connected to the first inputs of the sixth switch and the third inputs of the device control, the first output of the code comparison circuit is connected to the first input of the first logical element AND, the second output of the code comparison circuit is connected to the first input of the second of the logical element AND, the output of the first logical element And is connected to the decrement input of the fifth counter and the T-input of the T-trigger, the output of the second logic element And is connected to the recording inputs of the first and second stacks and the first control input of the arithmetic device, the outputs of the fifth counter are connected to the least significant bits the first inputs of the first switch and the first inputs of the control device, the output of the T-trigger is connected to the senior bit of the first inputs of the first switch, the third control input of the arithmetic device and in by the input of the control device, the outputs of the first switch are connected to the data inputs of the second memory block, the least significant bits of the outputs of the second memory block are connected to the data inputs of the fifth counter, the highest bit of the outputs of the second memory block is connected to the data input of the T-trigger, the outputs of the second stack are connected to the second inputs the second switch and the second inputs of the fifth switch, the outputs of the second switch are connected to the data inputs of the third memory block, the outputs of the third memory block are connected to the data inputs of the first register latches, the outputs of the first register-latches are connected to the data inputs of the second stack and the third inputs of the fifth switch, the outputs of the fifth switch are connected to the address inputs of the first memory block, the outputs of the first counter are connected to the second inputs of the third switch, the outputs of the second counter are connected to the first inputs of the third switch , the outputs of the third counter are connected to the second inputs of the fourth switch, the outputs of the fourth counter are connected to the third inputs of the fourth switch and second inputs of the first sum the torus, the outputs of the third switch are connected to the address inputs of the second memory block, the outputs of the fourth switch are connected to the address inputs of the third memory block, the outputs of the first adder are connected to the data inputs of the fourth counter, the first outputs of the control device are connected to the first inputs of the code comparison circuit, the second output of the control device connected to the reading inputs of the first and second stacks and the second control input of the arithmetic device, the third output of the control device is connected to the second inputs of the of the second and second logical elements AND, the fourth outputs of the control device are connected to the second inputs of the first switch, the fifth output of the control device is connected to the control input of the first switch, the sixth output of the control device is connected to the reset input of the fifth counter, the seventh outputs of the control device are connected to the third inputs of the third switch , the eighth outputs of the control device are connected to the third inputs of the sixth switch, the ninth outputs of the control device are connected to the fourth inputs of of that switch, the tenth output of the control device is connected to the reset input of the first counter, the eleventh outputs of the control device are connected to the control inputs of the sixth switch, the twelfth output of the control device is connected to the increment input of the first counter, the thirteenth outputs of the control device are connected to the control inputs of the third switch, the fourteenth output of the device control is connected to the reset input of the second counter, the fifteenth output of the control device is connected to the recording input of the second block and the memory, the sixteenth output of the control device is connected to the increment input of the second counter, the seventeenth output of the control device is connected to the recording input of the first memory block, the eighteenth outputs of the control device are connected to the first inputs of the first adder, the nineteenth output of the control device is connected to the load input of the fourth counter, the twentieth output the control device is connected to the reset input of the fourth counter, the twenty-first output of the control device is connected to the input of the increment of the third count sensor, twenty-second output of the control device is connected to the reset input of the third counter, twenty-third outputs of the control device are connected to the first inputs of the fourth switch, twenty-fourth outputs of the control device are connected to the control inputs of the fourth switch, twenty-fifth outputs of the control device are connected to the control inputs of the fifth switch, the twenty-sixth outputs of the control device are connected to the first inputs of the fifth switch, the twenty-seventh output of the control device is connected connected to the control input of the second switch, the twenty-eighth outputs of the control device are connected to the first inputs of the second switch, the twenty-ninth output of the control device is connected to the recording input of the third memory block, the thirtieth output of the control device is connected to the boot input of the first register-latch, the thirty-first output of the control device connected to the inputs of the downloads of the fifth counter and T-flip-flop, the thirty-second output of the control device is connected to the reset input of the arithmetic device, the oldest (sign (i) the discharge bit of the outputs of the first memory block is the output of the LDPC code decoding device, the arithmetic device comprising a third stack, first and second blocks for calculating the function g, a sixth counter, a second register-latch, the first and second D-flip-flops, seventh-ninth switches, second adder, decoder, first and second elements OR, third to sixth elements AND, sign inversion circuit, the first inputs of the seventh switch being the first data inputs of an arithmetic device, the second inputs of the seventh switch connected to the second inputs of the second adder are the second data inputs of the arithmetic device, the outputs of the seventh switch are connected to the second inputs of the first unit of calculation of the function g and the second inputs of the eighth switch, the outputs of the first unit of the calculation of the function g are connected to the first inputs of the eighth switch, the outputs of the eighth switch are connected to the data inputs the second register-latch, the outputs of the second register-latch are connected to the first inputs of the first unit of calculation of function g, the first inputs of the second unit of calculation functions g, the first inputs of the ninth multiplexer and data inputs of the third stack, the outputs of the second block of calculation of the function g are connected to the second inputs of the ninth switch, the outputs of the ninth switch are connected to the inputs of the sign inversion circuit, the outputs of the sign inversion circuit are connected to the first inputs of the second adder, the outputs of the third stack connected to the second inputs of the second unit of calculation of the function g and the third inputs of the ninth switch, the control input of the sign inversion circuit is the third control input of the arithmetic three, the input of the increment of the sixth counter is connected to the D-input of the second D-trigger, the first input of the second logical element OR, the first input of the third logical element And is the first control input of the arithmetic device, the input of the decrement of the sixth counter is connected to the D-input of the first D-trigger , the second input of the second logical element OR, the first input of the sixth logical element And, the second input of the fourth logical element And, the second input of the fifth logical element And, the control input of the seventh switch, the read input of the third stack and is the second control input of the arithmetic device, the reset input of the second latch register is connected to the reset input of the sixth counter, the reset input of the first D-trigger, the reset input of the second D-trigger and is the reset input of the arithmetic device, the outputs of the sixth counter are connected to the inputs of the decoder, the first output of the decoder is connected to the second input of the third logical element And, the second output of the decoder is connected to the first input of the fourth logical element And, the output of the third The AND gate is connected to the first input of the first OR gate, the output of the first OR gate is connected to the control input of the eighth switch, the output of the second OR gate is connected to the load input of the second latch register, the output of the first D-trigger is connected to the second input of the sixth logical gate And, the output of the second D-trigger is connected to the first input of the fifth logical element And, the output of the fifth logical element And is connected to the recording input of the third stack, the output of the fourth logical element And connected to the first control input of the ninth switch, the output of the sixth logical element AND is connected to the second control input of the ninth switch and the second input of the first logical OR, the outputs of the second adder are the outputs of the arithmetic device.

The interaction of the introduced functional blocks provides a consistent refinement of the word character estimates of the LDPC code while simplifying the verification equations.

The essence of the invention lies in the fact that to reduce the computational complexity of the iterative decoding algorithm used at each iteration, codeword symbols whose reliability is higher than a given threshold are excluded from the LDPC code verification equations. The verification equations in the decoding process are simplified and degenerate. The computational complexity of each subsequent iteration is reduced.

Figure 1 shows the functional diagram of the proposed device for decoding LDPC codes; figure 2 is a functional diagram of an arithmetic device; figure 3 is a functional diagram of the stack.

In the description of the device and in the drawings, the following notation is used:

AU - arithmetic device;

PU - verification equation;

UU - control device;

Cnt - counter;

Mux - switch (multiplexer);

DC - decoder;

LLR - Log likelihood ratio (log-likelihood ratio);

RAM - random access memory;

Rg is the register;

y ₁ -y ₇ - control signals;

n is the number of characters in the codeword of the LDPC code;

r is the number of verification equations in the LDPC code.

A device for decoding LDPC codes (FIG. 1) comprises a control device 1, first to third memory blocks 2-4; arithmetic device 5; first and second stacks 6, 7; first to fifth counters 8-10, 11.1, 12; the first register latch 13; T-trigger 14; first to sixth switches 15-20; code comparison scheme 21; the first and second elements And 22, 23, the first adder 11.2.

The second inputs of the sixth switch 20 are the inputs of the device decoding LDPC codes, which are fed with input data (DIn).

The outputs of the sixth switch 20 are connected to the data inputs of the first memory block 2. The outputs of the first memory block 2 are connected to the data inputs of the first stack 6, with the first data inputs of the arithmetic device 5 and the second inputs of the code comparison circuit 21. The outputs of the first stack 6 are connected with the second data inputs arithmetic device 5. The outputs of the arithmetic device 5 are connected to the first inputs of the sixth switch 20 and the third inputs of the control device 1. The first output of the code comparison circuit 21 is connected to the first input of the first logic and element 22. The second output of the code comparison circuit 21 is connected to the first input of the second logic element And 23. The output of the first logic element And 22 is connected to the decrement input of the fifth counter 12 and the T-input of the T-trigger 14. The output of the second logic element And 23 is connected with recording inputs of the first and second stacks 6 and 7 and the first control input of the arithmetic device 5. The outputs of the fifth counter 12 are connected to the least significant bits of the first inputs of the first switch 15 and the first inputs of the control device 1. The output of the T-trigger 14 is connected to the first bit of the first inputs of the first switch 15, the third control input of the arithmetic device 5 and the second input of the control device 1. The outputs of the first switch 15 are connected to the data inputs of the second memory block 3. The lower bits of the outputs of the second memory block 3 are connected to the data inputs of the fifth counter 12. Senior the outputs of the second memory block 3 are connected to the data input of the T-flip-flop 14. The outputs of the second stack 7 are connected to the second inputs of the second switch 16 and the second inputs of the fifth switch 19. The outputs of the second switch and 16 are connected to the data inputs of the third memory unit 4. The outputs of the third memory unit 4 are connected to the data inputs of the first register-latch 13. The outputs of the first register-latch 13 are connected to the data inputs of the second stack 7 and the third inputs of the fifth switch 19. The outputs of the fifth switch 19 connected to the address inputs of the first memory block 2. The outputs of the first counter 8 are connected to the second inputs of the third switch 17. The outputs of the second counter 9 are connected to the first inputs of the third switch 17. The outputs of the third counter 10 are connected to the second and the inputs of the fourth switch 18. The outputs of the fourth counter 11.1 are connected to the third inputs of the fourth switch 18 and the second inputs of the first adder 11.2. The outputs of the third switch 17 are connected to the address inputs of the second memory block 3. The outputs of the fourth switch 18 are connected to the address inputs of the third memory block 4. The outputs of the first adder 11.2 are connected to the data inputs of the fourth counter 11.1.

The first outputs of the control device 1 are connected to the first inputs of the code comparison circuit 21. The second output of the control device 1 is connected to the reading inputs of the first and second stacks 6 and 7 and the second control input of the arithmetic device 5. The third output of the control device 1 is connected to the second inputs of the logical elements AND 22 and 23. The fourth outputs of the control device 1 are connected to the second inputs of the first switch 15. The fifth output of the control device 1 is connected to the control input of the first switch 15. The sixth output of the control device Phenomenon 1 is connected to the reset input of the fifth counter 12. The seventh outputs of the control device 1 are connected to the third inputs of the third switch 17. The eighth outputs of the control device 1 are connected to the third inputs of the sixth switch 20. The ninth outputs of the control device 1 are connected to the fourth inputs of the sixth switch 20. Tenth the output of the control device 1 is connected to the reset input of the first counter 8. The eleventh outputs of the control device 1 are connected to the control inputs of the sixth switch 20. The twelfth output of the control device Level 1 is connected to the increment input of the first counter 8. The thirteenth outputs of the control device 1 are connected to the control inputs of the third switch 17. The fourteenth output of the control device 1 is connected to the reset input of the second counter 9. The fifteenth output of the control device 1 is connected to the recording input of the second memory unit 3. The sixteenth output of the control device 1 is connected to the input of the increment of the second counter 9. The seventeenth output of the control device 1 is connected to the input of the recording of the first memory block 2. The eighteenth outputs of the device The control device 1 is connected to the first inputs of the first adder 11.2. The nineteenth output of the control device 1 is connected to the boot input of the fourth counter 11.1. The twentieth output of the control device 1 is connected to the reset input of the fourth counter 11.1. The twenty-first output of the control device 1 is connected to the increment input of the third counter 10. The twenty-second output of the control device 1 is connected to the reset input of the third counter 10. The twenty-third outputs of the control device 1 are connected to the first inputs of the fourth switch 18. The twenty-fourth outputs of the control device 1 are connected to the control inputs of the fourth switch 18. The twenty-fifth outputs of the control device 1 are connected to the control inputs of the fifth switch 19. The twenty-sixth outputs of the control device 1 are connected to the first inputs of the fifth switch 19. The twenty-seventh output of the control device 1 is connected to the control input of the second switch 16. The twenty-eighth outputs of the control device 1 are connected to the first inputs of the second switch 16. The twenty-ninth output of the control device 1 is connected to the recording input of the third memory unit 4. The thirtieth output of the control device 1 is connected to the boot input of the first register-latch 13. The thirty-first output of the control device 1 is connected to the boot inputs of the fifth counter 12 and the T-trigger 14. Thirty-second output of the control device 1 is connected to the reset input of the arithmetic unit 5.

The senior (signed) bit of the outputs of the first memory block 2 is the output of the device for decoding LDPC codes (DOut).

All triggers, registers, counters used in the device for decoding LDPC codes change their state at the end of the clock interval, depending on the control signals. The clock signal in the figures of the invention is not shown, but its presence is implied.

The first memory block 2 has a capacity of 2n words, each of which contains an LLR of one character of a codeword (n is the length of the codeword of the LDPC code).

The second memory block 3 has a capacity of r words, each of which contains a description of one parity equation in the LDPC code (r is the number of verification equations in the LDPC code). The most significant category of the description word contains the parity criterion, which determines the type of verification equation. If the sign is zero, a parity check is performed, if one is odd. The remaining bits of the description word contain the number of members of the verification equation.

The third block of memory 4 contains the symbol numbers of the codeword included in the verification equations. The symbol numbers of one verification equation are stored in adjacent words, the number of which is determined by the description of the verification equation. The total number of words of the third memory block 4 is equal to the total number of units in the check matrix H of the LDPC code.

When a logical unit is supplied to the first control input of the ninth switch 33, the contents of its third inputs are transmitted to its outputs. When a logical unit is supplied to the second control input of the ninth switch 33, the contents of its first inputs are transmitted to its outputs. When applying logical zeros to the control inputs of the ninth switch 33, the contents of its second inputs are transmitted to its outputs.

The code comparison circuit 21 compares the LLR value of the symbol supplied to its second inputs with the value of the threshold Thres supplied to its first inputs. And at first the LLR module is located. If this module is greater than the threshold or equal to it, a logical unit is formed at the first output of the circuit, otherwise a logical zero. At the second output of the circuit, an inverse signal is generated to the signal at the first output.

The arithmetic device (figure 2) contains a third stack 24; the first and second blocks of the calculation of the function g 25, 26; sixth counter 27; second latch register 28; the first and second D flip-flops 29. 30; seventh-ninth switches 31-33; second adder 34; decoder 35; the first and second elements OR 36, 37, the third to sixth elements AND 38-41, the sign inversion circuit 42.

The first inputs of the seventh switch 31 are the first data inputs of the arithmetic device 5 (DI1). The second inputs of the seventh switch 31 are connected to the second inputs of the second adder 34 and are the second data inputs of the arithmetic device 5 (DI2). The outputs of the seventh switch 31 are connected to the second inputs of the first block of function calculation g 25 and the second inputs of the eighth switch 32. The outputs of the first block of calculation of function g 25 are connected to the first inputs of the eighth switch 32. The outputs of the eighth switch 32 are connected to the data inputs of the second register-latch 28. The outputs of the second register-latch 28 are connected to the first inputs of the first unit for calculating the function g 25, the first inputs of the second unit for calculating the function g 26, the first inputs of the ninth multiplexer 33 and data inputs of the third ka 24. The outputs of the second block calculating the function g 26 are connected to the second inputs of the ninth switch 33. The outputs of the ninth switch 33 are connected to the inputs of the sign inversion circuit 42. The outputs of the sign inversion circuit 42 are connected to the first inputs of the second adder 34. The outputs of the third stack 24 are connected to the second the inputs of the second block computing function g 26 and the third inputs of the ninth switch 33.

The control input of the sign inversion circuit 42 is the third control input of the arithmetic device 5 (Par).

The increment input of the sixth counter 27 is connected to the D-input of the second D-trigger 30, the first input of the second OR gate 37, the first input of the third AND gate 38, and is the first control input of the arithmetic device 5 (Forward).

The decrement counter input of the sixth counter 27 is connected to the D-input of the first D-flip 29, the second input of the second logical element OR 37, the first input of the sixth logical element AND 41, the second input of the fourth logical element And 39, the second input of the fifth logical element And 40, control input the seventh switch 31, the read input of the third stack 24 and is the second control input of the arithmetic device 5 (Backward).

The reset input of the second register-latch 28 is connected to the reset input of the sixth counter 27, the reset input of the first D-trigger 29, the reset input of the second D-trigger 30 and is the reset input of the arithmetic device 5 (Reset).

The outputs of the sixth counter 27 are connected to the inputs of the decoder 35. The first output of the decoder 35 is connected to the second input of the third logical element And 38. The second output of the decoder 35 is connected to the first input of the fourth logical element And 39. The output of the third logical element And 38 is connected to the first input of the first logical OR element 36. The output of the first OR gate 36 is connected to the control input of the eighth switch 32. The output of the second OR gate 37 is connected to the load input of the second register-latch 28. The output of the first The D-flip-flop 29 is connected to the second input of the sixth logical element AND 41. The output of the second D-flip-flop 30 is connected to the first input of the fifth logical element And 40. The output of the fifth logical element And 40 is connected to the recording input of the third stack 24. The output of the fourth logical element And 39 connected to the first control input of the ninth switch 33. The output of the sixth logical element AND 41 is connected to the second control input of the ninth switch 33 and the second input of the first logical OR 36.

The outputs of the second adder 34 are the outputs of the arithmetic device 5 (DO).

The second inputs of the fifth and sixth gates And 40 and 41 are inverse.

The switches used in the arithmetic device 5, operate as follows.

When a logical unit is supplied to the control input of the seventh switch 31, the contents of its second inputs are transmitted to its outputs. When a logical zero is applied to the control input of the seventh switch 31, the contents of its first inputs are transmitted to its outputs.

When a logical unit is supplied to the control input of the eighth switch 32, the contents of its second inputs are transmitted to its outputs. When a logical zero is applied to the control input of the eighth switch 32, the contents of its first inputs are transmitted to its outputs.

When a logical unit is supplied to the first control input of the ninth switch 33, the contents of its third inputs are transmitted to its outputs. When a logical unit is supplied to the second control input of the ninth switch 33, the contents of its first inputs are transmitted to its outputs. When applying logical zeros to the control inputs of the ninth switch 33, the contents of its second inputs are transmitted to its outputs.

Blocks for calculating the function g 25, 26 (the expression for the function is given below in the form of formula (2)) can be implemented in a known manner using tables (LUT).

The stack (Fig. 3) contains the tenth - (x + 9) th switches 43.1-43.x; the third is (x + 2) -th latch registers 44.1-44.x; the third element is OR 45, here x denotes the depth of the stack (the maximum number of words stored on the stack).

According to the scheme depicted in figure 3, all the stacks used in the device decoding LDPC codes (first stack 6, second stack 7, third stack 24) are implemented. They differ only in depth (parameter x) and the number of digits in the memorized words.

The first inputs of the tenth switch 43.1 are the data inputs of the stack (DI).

The outputs of the tenth switch 43.1 are connected to the data inputs of the third register-latch 44.1. The outputs of the third register-latch 44.1 are connected to the first inputs of the eleventh switch 43.2 and are the outputs of the stack (DO). The outputs of the (x + 9) th switch 43.x are connected to the data inputs of the (x + 2) th register-latch 44.x. The outputs of the (x + 2) th register-latch 44.x are connected to the second inputs of the (x + 8) th switch 43.x-1. The second inputs of the (x + 9) th switch 43.x are supplied with a constant - a zero word.

For the values of i (i = 2, ... x-1): the outputs of the (i + 9) th switch 43.i are connected to the data inputs of the (i + 2) th register-latch 44.i; the outputs of the (i + 2) -th register-latch 44.i are connected to the first inputs of the (i + 10) -th switch 43.i + 1; and with the second inputs of the (i + 8) -th switch 43.i-1.

The first input of the OR gate 45 is the stack read input (R). The second input of the OR gate 45 is connected to the control inputs of the tenth - (x + 9) -th switch 43.1-43.x and is the input to the stack record (W). The output of the OR gate 45 is connected to the inputs of the downloads of the third - (x + 2) th register-latches 44.1-44.x.

The stack works as follows.

When a logical unit of the stack entry (W) is fed to the input of the outputs of all switches 43.1-43.x, the words from their first inputs are transmitted, while the data inputs of each next latch register are logically connected to the outputs of the previous latch registers (forming a shift register by x words that implements a shift down), the data written to the stack (DO) are fed to the input of the register-latch 44.1. At the same time, using the third logical element OR 45, a logical unit is fed to the download inputs of all register-latches 44.1-44.x. At the end of the clock interval, all latch registers 44.1-44.x load the words that are fed to their inputs. Thus, the stack register is shifted in depth with writing to the top of the stack (register-latch 44.1) the words supplied to the inputs of the stack.

When a logical unit is fed to the read (stack) input input to the outputs of all switches 43.1-43.x, the words from their second inputs are transmitted, while the data inputs of each previous latch register are logically connected to the outputs of the following latch registers (forming a shift register by x words that implements an upward shift), the word zeros is fed to the input of the register-latch 44.x). At the same time, using the third logical element OR 45, a logical unit is fed to the download inputs of all register-latches 44.1-44.x. At the end of the clock interval, all latch registers 44.1-44.x load the words that are fed to their input. Thus, the stack register is shifted upwards and written to the top of the stack (register-latch 44.1) of the word previously written onto the stack.

Most often, for decoding LDPC codes, an iterative belief-propagation (IBP) decoding algorithm is used, also known as the sum-product algorithm and the message-passing algorithm (see Morelos-Zaragoza. The art of noise-resistant coding. Methods, algorithms , application. - M .: Technosphere, 2005. - 320 p.).

In the present invention, a modification of this algorithm is used, which provides for updating the LLR values (Log likelihood ratio) of the received word characters of the LDPC code after processing each verification code equation.

This algorithm is iterative, it involves the following steps.

1) The iteration counter is reset.

2) The first verification equation (PU) is selected from the set of valid PUs. If the set of valid PUs is empty, go to step 10.

3) Validation of the LLR values of the characters included in the verification equation. If the value module is greater than or equal to the specified threshold, the symbol score is considered reliable, and it does not change anymore (“freezes”). The corresponding symbol is removed from the verification equation, while the verification equation is modified. If the value of the frozen symbol corresponds to binary 1, then the parity of the equation changes.

4) If, as a result of a modification, no members remain in the PU, it is considered degenerate. If there is only one member left, the threshold value (taking into account the sign) is taken as an estimate of the LLR of the character addressed by this member and the symbol “freezes.” The only term in the equation is removed (the equation also becomes degenerate).

5) If the equation degenerates, it is removed from the set of valid PUs and the transition to step 8 is performed.

6) The LLR values of the symbols included in the verification equation are updated.

7) The modified PU replaces the previous PU in the set of valid PUs.

8) The following verification equation is selected from the set of valid PUs. If all PUs have been processed, go to the next step, otherwise go to step 3.

9) The iteration counter is incremented. If its value is less than the specified limit number of iterations, the transition to step 2.

10) Hard decisions are made, which are used as the sign bits LLR characters of the code word. The LLR values of the symbols included in the verification equation are updated in step 6 as follows:

- значение LLR символа i_j кодового слова; g() - функция, используемая для оценки LLR символа на основе проверочного уравнения; p - число членов проверочного уравнения.Where

- LLR value of the symbol i _j codeword; g () is the function used to estimate the LLR of a symbol based on a test equation; p is the number of members of the verification equation.

The function g () of the two arguments can be defined as follows (see patent 1379001 EP. IPC ⁷ H03M 13/13. Methods and system for decoding low density parity check (LDPC) codes / Mustafa Eroz, Feng-Wen Sun, Lin- Nan Lee - stated 02.07.2003 No. 03254214.4; publ. 07.01.2004):

where LUT _g ( a , b) = ln (1 + e ^{- | a + b |} ) -ln (1 + e ^{- | ab |} ).

The g () function of more than two arguments can be calculated recursively.

In the present invention, the arithmetic device 5 implements an update of the LLR values of the characters sequentially in two passes.

,

, …,

,

- значения LLR символов, входящих в проверочное уравнение. При этом вычисляется последовательность вспомогательных переменных f_j:In a direct passage to the first inputs of the arithmetic device 5 sequentially arrive

,

, ...,

,

- LLR values of the symbols included in the verification equation. In this case, the sequence of auxiliary variables f _j is calculated:

...

,

, …,

,

. При этом вычисляется последовательность вспомогательных переменных b_j:When performing a reverse pass to the second inputs of the arithmetic device 5, the same LLR values of the characters that were fed to the arithmetic device 5 during the first pass sequentially arrive in the reverse order from the first stack 6,

,

, ...,

,

. In this case, the sequence of auxiliary variables b _j is calculated:

...

Also, during the return pass, new LLR symbol values are sequentially calculated and output from the arithmetic device 5:

In the process of processing the device decoding LDPC codes of the received codeword, three phases can be distinguished.

In the first phase, LLR symbols are sequentially loaded into the first memory unit 2 (Fig. 1) through the sixth switch 20, the second inputs of which are the data inputs of the device. The addresses of the cells of the first memory block in this case are formed by the control device 1, from the twenty-sixth outputs of which they go to the first inputs of the fifth switch 19 and are then sent to the address inputs of the first memory block 2. A write gate to the memory is also formed by УУ 1.

Also, in the first phase, the control unit 1 initializes the second and third memory blocks 3 and 4. For this, they store the initial values of the parameters of the verification equations determined by the verification matrix H of the used LDPC code. For initialization, the first and fourth switches 15-18 are used: through the first and second switches 15, 16, parameters are written into memory blocks 3, 4, and the addresses of the corresponding memory cells are transmitted through the third and fourth 17, 18.

In the second phase, iterative decoding of the codeword is performed. The second phase is the main, it will be discussed in detail below.

In the third phase, the corrected code word is unloaded from the first memory block 2, its characters are sent to the output of the device. Tough decisions are taken as symbols of the code word, which are LLR signed digits. The addresses of the cells of the first memory block in this case are formed by the control device 1, from the twenty-sixth outputs of which they go to the first inputs of the fifth switch 19 and are then fed to the address inputs of the first memory block 2.

Let us consider in more detail the operation of the apparatus for decoding LDPC codes in the second phase of processing the received codeword.

In this phase, the decoding device performs a given number of iterations.

The number of decoding iterations is calculated by the control device 1. Decoding is completed when the decoder performs a specified number of iterations. Also, decoding is completed in the absence of valid verification equations, which should be contained in the second and third memory blocks 3 and 4. The absence of valid PUs is determined by the zero value of the field of the number of PU members in the cell of the second memory block 3 located at the zero address.

In each iteration, the decoding device processes all valid verification equations whose parameters are stored in the second and third memory blocks 3 and 4.

Processing one valid verification equation begins by reading the description of the gas turbine from the second memory block 3. The number of PU members from the PU description is entered in the fifth counter 5, the parity flag is placed in the T-trigger 14.

Then from the third memory block 4 into the first register-latch 13 sequentially reads the position numbers of the symbols of the codeword included in the processed equation. These numbers are used as the addresses of the first memory block 2 to read the sequence of LLR values of the characters included in the verification equation. To do this, the contents of the first register-latch 13 is fed to the third inputs of the fifth switch 19 and then to the address inputs of the first memory block 2. The sequence of position numbers of the codeword symbols included in the equation is also stored in the second stack 7.

The sequence of LLR values of the symbols included in the verification equation is simultaneously fed to the second inputs of the code comparison circuit 21, the first data inputs of the arithmetic device 5 and to the data inputs of the first stack 6. Only non-frozen LLR values are pushed onto the stack and processed by AC 5, whose the module does not exceed the Thres threshold. This corresponds to a direct pass of the LLR modification of the symbols included in the verification equation.

To determine and process the "frozen" values of LLR characters, a code comparison scheme 21 and the first and second logic elements And 22 and 23 are used. The comparison circuit compares the codes received at its inputs. The first inputs are supplied with a threshold value issued by UU 1, the second inputs are fed with a sequence of LLR values of characters read from the first memory block 2. If the LLR value is greater than or equal to the threshold value at the first output of the code comparison circuit 21, logical 1 is generated (sign “ icing ”), at the second output of the comparison circuit, an inverse value is formed to the first output. A single value of the signal at the output of the first logical element And 22 reduces by one the number of PU members stored in the fifth counter 12, and changes the parity of the PU, the sign of which is stored in the T-trigger. A single value of the signal at the output of the second logical element AND 23 allows the LLR values to be written to the first stack of AC 5 and the corresponding LLR values of symbol numbers to the second stack 7.

If, after a direct pass, the contents of the fifth counter 12 are reset or equal to 1, the reverse pass is not performed, the parameters of the degenerate verification equation in the second and third memory blocks are not saved. If the contents of the fifth counter 12 has become equal to 1, the threshold value with the corresponding sign at the address equal to the number of the only remaining character is written into the first memory block 2 as the LLR value.

If the verification equation does not degenerate (the contents of the fifth counter 12 are greater than 1), after the direct pass is completed, the reverse pass of the modification of LLR symbols included in the verification equation begins. During the passage to the second data inputs of the arithmetic device 5 from the first stack 6, a sequence of LLR values of symbols included in the verification equation is fed in the reverse order. During the return pass, the modified values of LLR characters appear on the outputs of AU 5, which are written to the first memory block 2 at the addresses read from the second stack 7. At the same time, the addresses read from the second stack 7, which are the numbers of characters included in the PU, are entered in the third memory block 4. A modified description of the PU is recorded from the T-flip-flop 14 and the fifth counter 12 to the second memory block 3 at the address stored in the second counter 9, which is then incremented. Thus, the modified PU is saved.

The first counter 8, which stores the address of the current PU description, is incremented, and the described process is repeated for the next and then for all valid verification equations, the description of which is stored in the second and third memory blocks 3 and 4.

The computational complexity of the device decoding LDPC codes is reduced compared with the prototype due to the sequential decrease in the computational complexity of iterations of the decoding algorithm with increasing iteration number. This is determined by a decrease in the number of members of the verification equations (due to the "freezing" of the codeword characters) and a decrease in the number of PUs (due to their degeneration).

Arithmetic device 5 (figure 2) during a direct pass works as follows.

The LLR values of the symbols supplied to the first data inputs of the arithmetic device 5 (DI1) are transmitted to the outputs of the seventh switch 31, since the second control signal of the arithmetic device 5 (Backward), which is input to the control input of the switch 31, is inactive.

через восьмой коммутатор 32, выходы которого на это время подключаются к его вторым входам, загружается во второй регистр-защелку 28, формируя значение f₁ в соответствии с формулой (3). Для управления коммутатором 32 в это время активизируется (принимает значение, равное логической единице) сигнал на выходе логического элемента И 38, поступающий далее через логический элемент ИЛИ 36 на вход управления восьмого коммутатора. Соответствующий временной интервал определяется нулевым состоянием шестого счетчик 27, во время которого на первом выходе дешифратора 35 появляется логическая 1.First LLR value

through the eighth switch 32, the outputs of which are connected to its second inputs at this time, is loaded into the second latch register 28, forming the value f ₁ in accordance with formula (3). To control the switch 32 at this time, the signal at the output of the AND gate 38 is activated (takes a value equal to a logical unit), which then goes through the OR gate 36 to the control input of the eighth switch. The corresponding time interval is determined by the zero state of the sixth counter 27, during which logical 1 appears at the first output of the decoder 35.

The following LLR values go to the second inputs of the first unit of calculation of the function g 25, the first inputs of which receive the values f _j-1 from the outputs of the second register-latch 28. The results of the calculation of the function g through the eighth switch 32, the outputs of which are connected to its first inputs are recorded in the second register-latch 28, thereby forming the values of f _j in accordance with formulas (4-6). From the outputs of the second register-latch 28, the values of f _{j are} written to the third stack 24. The second D-trigger 30 is needed to synchronize the write signal to the stack with the appearance of the values f _j at the outputs of the second register-latch 28.

During the return pass, the arithmetic device 5 operates as follows.

The LLR values of the symbols supplied to the second data inputs of the arithmetic device 5 (DI2) in the reverse order are transmitted to the outputs of the seventh switch 31, since the second control signal of the arithmetic device 5 (Backward), which is input to the control input of the switch 31, is active.

через восьмой коммутатор 32, выходы которого на это время подключаются к его вторым входам, загружается во второй регистр-защелку 28, формируя значение b_p в соответствии с формулой (7). Для управления коммутатором 32 в это время активизируется (принимает значение, равное логической единице) сигнал на выходе логического элемента И 41, поступающий далее через логический элемент ИЛИ 36 на вход управления восьмого коммутатора. Соответствующий временной интервал определяется с помощью первого D-триггера 29, на D-вход которого подается сигнал управления "Backward".First in reverse order of LLR

through the eighth switch 32, the outputs of which are connected to its second inputs at this time, is loaded into the second latch register 28, forming the value of b _p in accordance with formula (7). To control the switch 32 at this time, a signal is activated (takes a value equal to a logical unit) at the output of the AND gate 41, which then passes through the OR gate 36 to the control input of the eighth switch. The corresponding time interval is determined using the first D-flip-flop 29, to the D-input of which a control signal "Backward" is applied.

The following LLR values go to the second inputs of the first unit of calculation of the function g 25, the first inputs of which receive the values of b _{j + 1} from the outputs of the second register-latch 28. The results of the calculation of the function g through the eighth switch 32, the outputs of which are connected to its first inputs are recorded in the second register-latch 28, thereby forming the values of b _j in accordance with formulas (8-10).

During the backward pass, modified LLR symbol values appear at the output of the arithmetic device 5.

(см. формулу 11), для этого используется второй сумматор 34, на вторые входы которого постоянно подаются значения LLR, поступающие на вторые входы данных арифметического устройства 5, на первые входы сумматора в 34 это время через девятый коммутатор 33 (третьи входы) и схему инверсии знака 42 из стека подается значение f_p-1.New value comes first

(see formula 11), for this, a second adder 34 is used, on the second inputs of which LLR values are constantly supplied to the second inputs of the arithmetic device 5, at the first inputs of the adder at 34 this time through the ninth switch 33 (third inputs) and the circuit sign inversion 42 from the stack, the value f _p-1 is supplied.

Then LLR values calculated by formula (12) appear, for this, the value g (f _j , b _j is supplied to the first inputs of the second adder 34 through the ninth switch 33 (second inputs) and the sign inversion circuit 42 from the outputs of the second unit of calculation of the function g 26 _+2, ). At the same time, the values of b _{j + 2} from the outputs of the second register of the latch 28 are supplied to the first inputs of the second block of calculation of the function g 26, and the quantities f _j from the outputs of the third stack 24 are received at the second inputs of the second block of the calculation of function g.

(см. формулу 13), для этого на первые входы второго сумматора 34 через девятый коммутатор 33 (первые входы) и схему инверсии знака 42 с выходов второго регистра-защелки 28 подается значение b₂. Соответствующий этому временной интервал определяется нахождением шестого счетчика 27 в состоянии «1», при этом на втором выходе дешифратора 35 появляется логическая 1, которая пропускается во время обратного прохода четвертым логическим элементом И 39 на первый вход управления девятого коммутатора 33.Last at the outputs of arithmetic device 5 appears a new value

(see formula 13), for this, the value b ₂ is supplied to the first inputs of the second adder 34 through the ninth switch 33 (first inputs) and the sign inversion circuit 42 from the outputs of the second register-latch 28. The corresponding time interval is determined by the sixth counter 27 in the state “1”, while at the second output of the decoder 35 appears logical 1, which is skipped during the return pass by the fourth logical element And 39 to the first control input of the ninth switch 33.

If logic 1 is present at the third control input of the arithmetic device 5 (Par), the sign inversion circuit changes the sign of the magnitude of the LLR change, this must be done for test equations, the sum of characters of which must be odd.

The proposed device consists of simple in its functional purpose elements and therefore can easily be implemented on FPGA or specialized LSI.

The proposed device decoding LDPC codes in comparison with the prototype has the advantage of less computational complexity. This in turn determines less hardware complexity or / and higher device throughput.

Claims (2)

1. A device for decoding LDPC codes, containing the first and second memory blocks, characterized in that the third memory block, the arithmetic device, the first and second stacks, the first to fifth counters, the first register-latch, T-trigger, the first- sixth switches, code comparison circuit, first and second elements AND, first adder, the second inputs of the sixth switch being inputs of the LDPC code decoding device, the outputs of the sixth switch are connected to the data inputs of the first memory block, the outputs of the first memory block are connected inens with data inputs of the first stack, with the first data inputs of the arithmetic device and second inputs of the code comparison circuit, the outputs of the first stack are connected to the second data inputs of the arithmetic device, the outputs of the arithmetic device are connected to the first inputs of the sixth switch and the third inputs of the control device, the first output of the comparison circuit codes connected to the first input of the first logical element And, the second output of the circuit comparing codes connected to the first input of the second logical element And, the output of the first the logical element And is connected to the decrement input of the fifth counter and the T-input of the T-trigger, the output of the second logical element And is connected to the recording inputs of the first and second stacks and the first control input of the arithmetic device, the outputs of the fifth counter are connected to the least significant bits of the first inputs of the first switch and the first the inputs of the control device, the output of the T-trigger is connected to the senior bit of the first inputs of the first switch, the third control input of the arithmetic device and the second input of the control device, the outputs of the first switch are connected to the data inputs of the second memory block, the least significant bits of the outputs of the second memory block are connected to the data inputs of the fifth counter, the highest bit of the outputs of the second memory block is connected to the data input of the T-trigger, the outputs of the second stack are connected to the second inputs of the second switch and second inputs of the fifth switch, the outputs of the second switch are connected to the data inputs of the third memory block, the outputs of the third memory block are connected to the data inputs of the first register-latch, the outputs of the first register-protect The tabs are connected to the data inputs of the second stack and the third inputs of the fifth switch, the outputs of the fifth switch are connected to the address inputs of the first memory block, the outputs of the first counter are connected to the second inputs of the third switch, the outputs of the second counter are connected to the first inputs of the third switch, the outputs of the third counter are connected to the second the inputs of the fourth switch, the outputs of the fourth counter are connected to the third inputs of the fourth switch and the second inputs of the first adder, the outputs of the third switch with are connected to the address inputs of the second memory block, the outputs of the fourth switch are connected to the address inputs of the third memory block, the outputs of the first adder are connected to the data inputs of the fourth counter, the first outputs of the control device are connected to the first inputs of the code comparison circuit, the second output of the control device is connected to the read inputs of the first and the second stacks and the second control input of the arithmetic device, the third output of the control device is connected to the second inputs of the first and second logic elements And, the fourth outputs of the control device are connected to the second inputs of the first switch, the fifth output of the control device is connected to the control input of the first switch, the sixth output of the control device is connected to the reset input of the fifth counter, the seventh outputs of the control device are connected to the third inputs of the third switch, the eighth outputs of the control device connected to the third inputs of the sixth switch, the ninth outputs of the control device are connected to the fourth inputs of the sixth switch, the tenth output of the device The control is connected to the reset input of the first counter, the eleventh outputs of the control device are connected to the control inputs of the sixth switch, the twelfth output of the control device is connected to the increment input of the first counter, the thirteenth outputs of the control device are connected to the control inputs of the third switch, the fourteenth output of the control device is connected to the reset input the second counter, the fifteenth output of the control device is connected to the recording input of the second memory unit, the sixteenth output of the device the two controls are connected to the increment input of the second counter, the seventeenth output of the control device is connected to the recording input of the first memory block, the eighteenth outputs of the control device are connected to the first inputs of the first adder, the nineteenth output of the control device is connected to the boot input of the fourth counter, the twentieth output of the control device is connected to the input resetting the fourth counter, the twenty-first output of the control device is connected to the input of the increment of the third counter, the twenty-second output of the device the two controls are connected to the reset input of the third counter, the twenty-third outputs of the control device are connected to the first inputs of the fourth switch, the twenty-fourth outputs of the control device are connected to the control inputs of the fourth switch, the twenty-fifth outputs of the control device are connected to the control inputs of the fifth switch, the twenty-sixth outputs of the control device connected to the first inputs of the fifth switch, the twenty-seventh output of the control device is connected to the control input of the second comm tator, twenty-eighth outputs of the control device are connected to the first inputs of the second switch, twenty-ninth output of the control device is connected to the recording input of the third memory block, the thirtieth output of the control device is connected to the boot input of the first register-latch, the thirty-first output of the control device is connected to the inputs of the fifth downloads counter and T-flip-flop, the thirty-second output of the control device is connected to the reset input of the arithmetic device, the senior (signed) bit of the outputs of the first memory block This is the output of the LDPC decoding device. 2. The device according to claim 1, characterized in that the arithmetic device comprises a third stack, first and second blocks for calculating the function g, a sixth counter, a second latch register, a first and second D-trigger, seventh-ninth switches, a second adder, a decoder , the first and second elements OR, the third to sixth elements AND, a sign inversion circuit, the first inputs of the seventh switch being the first data inputs of an arithmetic device, the second inputs of the seventh switch connected to the second inputs of the second adder and being the second input arithmetic data, the outputs of the seventh switch are connected to the second inputs of the first unit of calculation of function g and the second inputs of the eighth switch, the outputs of the first unit of calculation of function g are connected to the first inputs of the eighth switch, the outputs of the eighth switch are connected to the data inputs of the second register-latch, the outputs of the second register-latch connected to the first inputs of the first unit of calculation of the function g, the first inputs of the second unit of calculation of the function g, the first inputs of the ninth multiplexer and input and data of the third stack, the outputs of the second block of function calculation g are connected to the second inputs of the ninth switch, the outputs of the ninth switch are connected to the inputs of the sign inversion circuit, the outputs of the sign inversion circuit are connected to the first inputs of the second adder, the outputs of the third stack are connected to the second inputs of the second block of the function calculation g and the third inputs of the ninth switch, the control input of the sign inversion circuit is the third control input of the arithmetic device, the increment input of the sixth counter is connected to the D-input the house of the second D-trigger, the first input of the second logical element OR, the first input of the third logical element AND is the first control input of the arithmetic device, the decrement input of the sixth counter is connected to the D-input of the first D-trigger, the second input of the second logical element OR, the first input the sixth logical element And, the second input of the fourth logical element And, the second input of the fifth logical element And, the control input of the seventh switch, the read input of the third stack and is the second input of the control arithmetic device, the reset input of the second register-latch is connected to the reset input of the sixth counter, the reset input of the first D-trigger, the reset input of the second D-trigger and is the reset input of the arithmetic device, the outputs of the sixth counter are connected to the inputs of the decoder, the first output of the decoder is connected to the second input of the third logical element And, the second output of the decoder is connected to the first input of the fourth logical element And, the output of the third logical element And is connected to the first input of the first logical of the OR gate, the output of the first OR gate is connected to the control input of the eighth switch, the output of the second OR gate is connected to the boot input of the second register-latch, the output of the first D-trigger is connected to the second input of the sixth logical gate And, the output of the second D-trigger is connected with the first input of the fifth logical element AND, the output of the fifth logical element And is connected to the recording input of the third stack, the output of the fourth logical element And is connected to the first control input of the ninth switch , the output of the sixth logical element AND is connected to the second control input of the ninth switch and the second input of the first logical element OR, the outputs of the second adder are the outputs of the arithmetic device.

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