RU2522299C1 - Method and apparatus for noise-immune decoding of signals obtained using low-density parity check code - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: method for noise-immune decoding of signals obtained using a low-density parity check (LDPC) code, where after decoding a LDPC code, the method includes a procedure for detecting and eliminating short unresolved cycles in a Tanner graph, and specifically determining a set of invalid bit indices; based on the obtained set, constructing a frequency of occurrence vector G; determining indices having maximum frequency of occurrence in the vector G; changing the sign therein to an opposite sign in a codeword arriving at the decoder and re-decoding the obtained word; the method being characterised by that during iterative decoding, after every ten iterations, the method includes forming an additional evidential vector of demodulator relaxed solutions, from which demodulator relaxed solutions are corrected when decoding the code and determining a set of invalid bits, from which the frequency of occurrence vector of bit indices is then constructed when detecting and eliminating short cycles in a Tanner graph.

EFFECT: low error probability in signal decoding.

2 cl, 4 dwg, 1 tbl

Description

The inventions are united by a single inventive concept, relate to the field of radio engineering, and in particular to systems for detecting errors in signals obtained using a low-density parity check code, and are intended for use in the field of digital information transmission.

Interference-resistant coding refers to the coding of the symbols of a digital data signal, characterized by the use of code combinations that can detect and (or) correct errors in this signal (GOST 17657-79. Data transmission. Terms and definitions. - p. 9).

Interference-free decoding is understood as the reverse operation of encoding the symbols of a digital data signal (GOST 17657-79. Data transmission. Terms and definitions. - p. 9).

A low-density parity check code is understood to mean a code whose check matrix has the majority of elements equal to zero and the minority equal to unity (R. G. Gallager. Low-Density Parity-Check Codec. - 1963, p.7).

A parallel cascade code is understood as a coding scheme consisting of two codes connected in parallel through an interleaver (R. Morelos-Zaragoza. The art of noise-resistant coding. Methods, algorithms, applications. - Moscow: Technosfera, 2005, p.238).

A known method of decoding a low-density code is the trust propagation algorithm (R. Morelos-Zaragoza. The art of noise-resistant coding. Methods, algorithms, application. - Moscow: Technosphere, 2005, pp. 262-263). The principle of the algorithm is that each node iteratively exchanges data with neighboring nodes through the edges connecting them. The initial data for the algorithm are the soft solutions of the demodulator, namely the logarithmic likelihood ratio (LLR) for each bit of the codeword:

, $$L^{\left(0\right)}\left(c_i\right)=\log \frac{P\left(c_i=0|\; |\; |y_i\right)}{P\left(c_i=\mathrm{one}|\; |\; |y_i\right)}$$

,

Where:

L ⁽⁰⁾ (c _i ) is the logarithmic likelihood ratio of the i-th element of the codeword, zero iteration;

P (c _i = 0 | y _i ) is the conditional probability that 0 was transmitted, provided that y _i was received;

P (c _i = 1 | y _i ) is the conditional probability that 1 was transmitted, provided that y _i was received.

At the end of each iteration, the LLR vector is formed:

, $${\overline{L}}^{(l+\mathrm{one})}={\overline{L}}^{(0)}+\alpha {\overline{L}}_{ext}^{(l)}$$

,

Where

- вектор логарифмического отношения правдоподобия на (l+1)-й итерации; $${\overline{L}}^{(l+\mathrm{one})}$$

- the logarithmic likelihood ratio vector at the (l + 1) th iteration;

- мягкие решения демодулятора; $${\overline{L}}^{(0)}$$

- soft demodulator solutions;

- сторонняя информация на l-й итерации. $${\overline{L}}_{ext}^{(l)}$$

- third-party information at the l-th iteration.

In the classical confidence spreading algorithm, third-party information is calculated as the sum of the products, and in a simplified version of this algorithm, as the sum of the minimum elements. The simplified noise immunity algorithm is inferior to the classical one by about 0.5-1 decibels, but has been widely used in view of a simple implementation in practice.

At the output of the algorithm, after performing l iterations, the LLR vector is formed:

. $${\overline{L}}^{(l)}=\left[L^{(l)}(c_{\mathrm{one}}),L^{(l)}(c_2),...,L^{(l)}(c_n)\right]$$

.

Based on this vector, a tough decision is made - vector V.

Syndrome S of the code word V is calculated by the formula:

S = V · H ^T ,

where the vector S consists of (nk) components (n is the total length of the codeword, k is the informational length of the codeword) and is calculated by (nk) verification equations, H ^T is the transposed verification matrix of the code. If the vector V is a codeword, all (nk) components are 0, i.e. all (nk) test equations are 0.

The disadvantage of this method is the lack of mechanisms to deal with unresolved short cycles in the Tanner graph of the low-density code that are generated as a result of iterative decoding of the code by the confidence propagation algorithm, and, as a result, there is a high probability of decoding error at low signal to noise ratios.

Unresolved short cycle - a cycle with a length of six edges, the bit nodes of which are decoded ambiguously.

Also known is a method and apparatus for decoding a channel in a communication system using a low-density parity check code (RF Patent No. 2446585, IPC Н04Н 60/88).

The disadvantage of this method and device is the lack of mechanisms to deal with unresolved short cycles in the Tanner graph of the low-density code that are generated as a result of iterative decoding of the code by the confidence propagation algorithm, and, as a result, there is a high probability of decoding error at low signal to noise ratios.

The closest in technical essence to the claimed invention (prototype) is a channel decoding method using a parallel cascading low density density parity check code (RF Patent No. 2461964, IPC Н03М 13/11), which consists in the fact that after decoding the parity check code with a low density, the procedure for identifying and eliminating short unresolved cycles in the Tanner graph is carried out, namely, by the threshold value, a plurality of indices of invalid bits are determined, a vector is constructed from the obtained set p frequency of occurrence G, determine the indices having the maximum frequency of occurrence in the vector G, change their sign in the opposite in the code word that was received by the decoder, and again decode the resulting word.

The closest in technical essence to the claimed invention (prototype) is an LDPC decoding device (RF Patent No. 2392737, IPC Н03М 13/00) containing an input buffer, a log likelihood ratio generator, an iterative LDPC decoder, an output buffer and a control device, an output the input buffer is connected to the input of the generator of the logarithmic likelihood ratio of the bits, the output of which is connected to the iterative decoder LDPC, and the output of the latter is connected to the input of the output buffer.

The disadvantage of this method and device is the relatively low percentage of elimination of unresolved short cycles in the Tanner graph of the low-density code, which are generated as a result of iterative decoding of the code by the trust propagation algorithm, and, as a result, the high probability of decoding errors at low signal-to-noise ratios, and the disadvantage of the device is lack of a mechanism to combat short cycles.

The objective of the invention is a method and apparatus for noise-free decoding of signals obtained using a low-density parity check code, which reduces the likelihood of signal decoding errors.

The objective of the invention is solved in that a method for noise-free decoding of signals obtained using a low-density parity check code, which consists in the fact that after decoding a low-density parity check code, a procedure for identifying and eliminating short unresolved cycles in the Tanner graph is performed, namely the threshold value determines the set of indices of invalid bits, from the resulting set, construct the frequency vector of occurrence G, determine the indices having the maximum frequency occurrences in the vector G, they change the sign in the opposite in the code word that was sent to the decoder, and again decode the resulting word, according to the invention is supplemented by the fact that iterative decoding every ten iterations forms an additional vector of reliability of the soft solutions of the demodulator, according to which carry out the correction of the soft decisions of the demodulator in the process of decoding the code and determine the set of unreliable bits, which, in the future, build the vector of frequencies of occurrence of indices bit when performing the procedure for identifying and eliminating short cycles in the Tanner graph.

The objective of the invention is solved in that in an LDPC decoding device containing an input buffer, a bit likelihood logarithmic shaper, an iterative LDPC decoder, an output buffer and a control device, an input buffer output is connected to an input of a bit likelihood logarithm shaper, the output of which is connected to an iterative decoder and the output of the latter with the input of the output buffer, according to the invention, a module for correction of the logarithmic likelihood ratio of bits and an intermediate counter are additionally introduced For accurate decoding iterations, the input of the intermediate iteration counter is connected to the second output of the iterative LDPC decoder, and the output of the intermediate iteration counter is connected to the correction unit, the output of which is connected to the second input of the bit likelihood ratio generator.

принимает значение меньше нуля, то i-е значение индекса вектора оценок увеличивается на единицу. Таким образом, после каждой десятой итерации элементы вектора оценок принимают значения от 0 до 9. Если i-й элемент равен 0, то данный элемент десять раз декодировался как положительное значение (т.е. в жестком виде 0), а если элемент равен 9, то данный элемент десять раз декодировался как отрицательное значение (т.е. в жестком виде 1). Коррекция мягких решений демодулятора L⁽⁰⁾(c_i) осуществляется следующим образом. Если W[i]=0 и L⁽⁰⁾[i]<0, то L⁽⁰⁾[i]=0, а если W[i]=9 и L⁽⁰⁾[i]>0, то L⁽⁰⁾[i]=-1. После чего элементы вектора W(w₀, w₁,…) обнуляются и за следующие десять итераций формируются заново. Также вектор дополнительных оценок участвует в процедуре определения и разрешения коротких циклов в графе Таннера, а именно с его помощью определяют индексы недостоверных бит. Недостоверные биты - это биты, которые можно с одинаковой вероятностью декодировать как «0», так и «1». В прототипе (Патент РФ №2461964, МПК Н03М 13/11) недостоверные биты определяются по абсолютному пороговому значению. При наиболее оптимальном пороге, установленном экспериментально, вероятность, рассчитанная по формуле P=n/N, где N - число индексов, биты которых имеют абсолютное значение меньше порогового, a n - число индексов из N, которые декодировались неверно, составляет «0.25», т.е. из ста отобранных индексов только 25 декодировалось неверно. В случае использования вектора достоверности мягких решений демодулятора W(w₀, w₁,…, w_n) для определения недостоверных бит, где недостоверными решениями являются те, которые имеют в векторе W значение, равное «4» или «5», вероятность, рассчитанная по выше написанной формуле, равна «0.491». Таким образом, при использовании вектора достоверности мягких решений демодулятора формируется наиболее полное множество недостоверных бит. На фигуре 4 показана зависимость вероятности ложного декодирования бит от значений вектора достоверности мягких решений демодулятора.An additional vector of estimates W (w ₀ , w ₁ , ..., w _n ) has a dimension equal to the length of the code word and shows the degree of inaccuracy of the soft bit solution. The vector of estimates is formed as follows. In case the ith bit after the jth iteration $$\left(j=\overline{\mathrm{0..9}}\right)$$

takes a value less than zero, then the ith value of the index of the vector of estimates increases by one. Thus, after every tenth iteration, the elements of the estimation vector take values from 0 to 9. If the ith element is 0, then this element was decoded ten times as a positive value (i.e., in hard form 0), and if the element is 9 , then this element was decoded ten times as a negative value (i.e., in hard form 1). Correction of soft solutions of the demodulator L ⁽⁰⁾ (c _i ) is as follows. If W [i] = 0 and L ⁽⁰⁾ [i] <0, then L ⁽⁰⁾ [i] = 0, and if W [i] = 9 and L ⁽⁰⁾ [i]> 0, then L ⁽⁰⁾ [i] = - 1. After that, the elements of the vector W (w ₀ , w ₁ , ...) are zeroed and over the next ten iterations are formed anew. Also, the vector of additional estimates participates in the procedure for determining and resolving short cycles in the Tanner graph, namely, with its help, indices of invalid bits are determined. Invalid bits are bits that can be decoded with the same probability as “0” or “1”. In the prototype (RF Patent No. 2461964, IPC Н03М 13/11), invalid bits are determined by the absolute threshold value. At the most optimal threshold established experimentally, the probability calculated by the formula P = n / N, where N is the number of indices whose bits have an absolute value less than the threshold, an is the number of indices from N that were decoded incorrectly, is “0.25”, t .e. out of a hundred selected indices, only 25 were decoded incorrectly. In the case of using the reliability vector of soft solutions of the demodulator W (w ₀ , w ₁ , ..., w _n ) to determine invalid bits, where invalid solutions are those that have a value in the vector W equal to "4" or "5", the probability calculated according to the above written formula, is equal to "0.491". Thus, when using the reliability vector of soft solutions of the demodulator, the most complete set of invalid bits is formed. The figure 4 shows the dependence of the probability of false decoding of bits on the values of the reliability vector of soft decisions of the demodulator.

The listed new set of essential features allows to reduce the likelihood of decoding errors at low signal-to-noise ratios by taking into account the statistical features of constructing a low-density parity check code.

The analysis of the prior art made it possible to establish that there are no analogues that are characterized by a combination of features that are identical to all the features of the claimed method and device for noise-free decoding of signals received using the low-density parity check code, which indicates that the invention meets the patentability condition of “novelty”.

Search results for known solutions in this and related fields of technology in order to identify features that match the distinctive features of the claimed object from the prototype showed that they do not follow explicitly from the prior art. The prior art also did not reveal the popularity of the impact provided for by the essential features of the claimed invention transformations on the solution of this problem.

Therefore, the claimed invention meets the condition of patentability "inventive step".

The "industrial applicability" of the method is due to the presence of an element base, on the basis of which devices can be made that implement this method with the achievement of the destination specified in the invention.

The claimed method is illustrated by drawings, which show:

figure 1 - sequence of operations of the error-correcting decoding of signals obtained using the low-density parity check code:

1 - decoding operation of ten iterations (0-9);

2 - correction procedure for soft solutions of the demodulator after the tenth iteration;

3 - decoding operation of ten iterations (10-19);

4 - correction procedure for soft solutions of the demodulator after the twentieth iteration;

5 - decoding operation of ten iterations (20-29);

6 - procedure for correcting soft decisions of the demodulator after the thirtieth iteration;

7 - decoding operation of ten iterations (from 10 · (k-1) to 10 · k);

8 is a procedure for correcting soft decisions of a demodulator after 10 · k iterations;

9 is a procedure for calculating a codeword syndrome;

10 is a procedure for detecting and eliminating short cycles in the Tanner column;

L is a codeword received from a communication channel;

L _n is the codeword after the nth decoding operation;

- скорректированное кодовое слово после n-й операции декодирования; $$L_n^{correct}$$

- the corrected codeword after the nth decoding operation;

L _cycle - code word with unresolved short cycles in the Tanner graph;

L _{with out cycle} - code word with allowed short cycles in the Tanner graph;

L ^correct - decoded codeword;

figure 2 is a General algorithm for a noiseless decoding of signals received using a low density parity check code:

A1 - initialization of the decoding algorithm;

A2 - condition check: the current iteration number is equal to the maximum number of iterations or not;

A3 - initialization (zeroing) of the reliability vector of soft decisions of the demodulator;

A4 - increase the number of the current iteration;

A5 - condition check: the current iteration number modulo 10 is equal to zero or not;

A6 - execution of one iteration of decoding a confidence-propagation algorithm;

A7, A8, A9 - formation of the vector of reliability of soft decisions of the demodulator;

A10, A11, A12, A13, A14, A15 - correction of soft solutions of the demodulator;

A16 - calculation of the codeword syndrome;

A17 - condition check: the codeword syndrome is equal to zero or not;

figure 3 is a diagram of a device that implements the decoding algorithm of the parity check code with low density:

B1 - module accumulation and storage of input values until the next code word;

B2 - module for storing the logarithmic likelihood relations of each bit, with the ability to change values during decoding;

B3 - correction device for input values of the logarithmic likelihood ratios of each bit;

B4 - module storage and storage of decoded bits;

B5 - low-density code decoder;

B6 - counter of iterations of low-density coding;

B7 - device for monitoring and generating control signals;

figure 4 - dependence of the probability of false decoding of bits on the values of the reliability vector of soft decisions of the demodulator.

The figure 1 presents the sequence of operations of the method of decoding signals obtained using the parity check code with low density.

, вектор достоверности W обнуляется и в блоках 3, 4, 5, 6, 7, 8 процесс повторяется. В блоке 9 после 10·k итераций выполняется расчет синдрома кодового слова. В случае если синдром равен 0, кодовое слово поступает на выход (L^correct), в противном случае - на процедуру обнаружения и устранения коротких циклов в графе Таннера (L_cycle). Данная процедура выполняется, как и в прототипе, за исключением того, что множество недостоверных бит определяется не по пороговому значению, а по значениям вектора достоверности мягких решений демодулятора, а именно недостоверные биты - биты, имеющие значения вектора W, равные «4» или «5». После устранения коротких циклов кодовое слово L_{with out cycle} вновь поступает на блок 1 и заново повторяется весь цикл обработки.The first ten decoding iterations of the decoding algorithm adopted by the trust propagation algorithm are performed over the code word L received from the communication channel and the confidence vector of soft decisions of the demodulator W (w ₀ , w ₁ , ..., w _n ) is formed, the elements of which take values from "0" to 9". If W [i] = 9, then ie the soft solution was decoded 9 times as a negative value, if W [i] = 0, then the ith soft solution was decoded 9 times as a positive value. In block 2, based on the values of the vector W, the soft solutions of the demodulator are corrected $$L_n^{correct}$$

, the confidence vector W is zeroed and in blocks 3, 4, 5, 6, 7, 8 the process is repeated. In block 9, after 10 · k iterations, the codeword syndrome is calculated. If the syndrome is 0, the code word is output (L ^correct ), otherwise, the procedure for detecting and eliminating short cycles in the Tanner graph (L _cycle ). This procedure is performed, as in the prototype, except that the set of invalid bits is determined not by the threshold value, but by the values of the reliability vector of the soft decisions of the demodulator, namely, invalid bits - bits having the values of the vector W equal to "4" or "5". After eliminating short cycles, the code word L _{with out cycle} reappears to block 1 and the entire processing cycle is repeated.

(блок А1). Далее проверяется условие: не превышает ли номер текущей итерации предельное число итераций декодирования (блок А2). В случае превышения кодовое слово поступает на выход, в противном случае - снова происходит инициализация вектора достоверности мягких решений демодулятора (блок A3) и текущий номер итерации декодирования увеличивается на один (блок А4). Затем проверяется условие: равен ли нулю по модулю десять номер текущей итерации (блок А5). Если не равен, то продолжается формирование вектора недостоверности мягких решений демодулятора (блок А7, А8, А9). В противном случае - вектор достоверности мягких решений демодулятора сформирован и выполняется коррекция мягких решений демодулятора - от начала до конца кодового слова в цикле (блок А10) перебираются значения вектора достоверности. Если элемент вектора принимает крайние значения - «0» или «9» (блок A11), то проверяется условие: если для конкретного мягкого решения бита значение вектора достоверности равно «0» (данный бит десять раз декодировался как положительное значение), а мягкое решение демодулятора -отрицательное значение (блок А 12), то мягкому решению демодулятора присваивается значение «0» (блок А13). Если для конкретного мягкого решения бита значение вектора достоверности равно «9» (данный бит десять раз декодировался как отрицательное значение), а мягкое решение демодулятора - положительное значение (блок А14), то мягкому решению демодулятора присваивается значение «-1» (блок А15). После коррекции мягких решений демодулятора рассчитываем синдром декодированного кодового слова (блок 17), если он равен «0», то кодовое слово поступает на выход. В противном случае данное кодовое слово снова поступает на вход блока 1, и весь цикл обработки повторяется заново.The general algorithm of a signal decoding method using a low-density parity check code is shown in Figure 2. At the initial stage of signal decoding, the current number of iterations is set to zero and the reliability vector of soft solutions of the demodulator is initialized: $$\text{n}=\text{0}\text{, W [m]}=\text{0}\text{, m}=\overline{\text{0}\text{,}...\text{, N-1}}$$

(block A1). Next, the condition is checked: does the current iteration number not exceed the limit number of decoding iterations (block A2). In case of exceeding, the code word is output, otherwise, the vector of the reliability vector of soft decisions of the demodulator (block A3) is initialized again and the current decoding iteration number is increased by one (block A4). Then, the condition is checked: does the modulus of the current iteration equal ten modulo zero (block A5). If not equal, then the formation of the vector of unreliability of soft decisions of the demodulator continues (block A7, A8, A9). Otherwise, the reliability vector of soft decisions of the demodulator is generated and correction of soft decisions of the demodulator is performed - from the beginning to the end of the code word in the loop (block A10), the values of the reliability vector are selected. If the vector element takes extreme values - “0” or “9” (block A11), then the condition is checked: if for a particular soft decision of a bit, the value of the reliability vector is “0” (this bit was decoded as a positive value ten times), and the soft decision If the demodulator is a negative value (block A 12), then the soft decision of the demodulator is assigned the value "0" (block A13). If for a specific soft bit decision the value of the confidence vector is “9” (this bit was decoded ten times as a negative value), and the soft solution of the demodulator is a positive value (block A14), then the soft decision of the demodulator is set to “-1” (block A15) . After correction of the soft decisions of the demodulator, we calculate the syndrome of the decoded codeword (block 17), if it is “0”, then the codeword is output. Otherwise, this code word is fed back to the input of block 1, and the entire processing cycle is repeated again.

The figure 3 presents a diagram of a device that implements the decoding algorithm of the parity check code with low density.

The decoded codeword enters the input buffer B1, designed to accumulate input data during decoding and prevent loss of input data. A decoded codeword is read from the input buffer, and a soft demodulator solution is generated in block B2, which during decoding can be changed after ten iterations using the correction module for the logarithmic likelihood ratio of the OT bits. Error correction in the received codeword is achieved through the iterative decoder LDPC B5. The decoding process is controlled by an intermediate iteration counter B6, which generates an overflow signal when the value "10" is reached. At this moment, the logarithmic likelihood ratios of the input bits (soft demodulator solution) B3 are corrected. The decoding result is recorded in the output buffer B4, designed to match the read speed of the decoded bits and the clock frequency of the decoder. All of the above blocks generate operation indication signals to control device B7, which, depending on the operating mode, generates various control actions.

To implement the circuit described above, a programmable logic integrated circuit (FPGA) XC6VSX240T-FF1156-1 from the Xilinx family of the Virtex-6 family was used. The table shows the FPGA resources needed to implement the proposed method of noise-free decoding.

Table 1 The resource consumption of the proposed method error-correcting decoding Resource Intensity Slice Logic is used Total interest Number of Slice Registers 36391 58880 61% Number of Slice LUTs 45765 58880 77% The number used as logic 45600 58880 77% The amount used as memory 165 24320 0% Resource intensity of specialized blocks Number of Block RAM / FIFO 153 244 62% Number of BUFG / BUFGCTRLs 6 32 eighteen% Number of DSP48Es 180 640 28% Number of PLL ADVs one 6 16%

To evaluate the effectiveness of the proposed method of noise-free decoding in comparison with the existing method described in the prototype, a software model of the decoder was developed in the Microsoft Visual Studio 2008 environment, which implements the algorithm of the proposed method of noise-free decoding for DVB-S2 standard signals, where the parity check code is low density is part of the cascade design, as well as for a parallel turbo coding scheme, where the low density parity check code is a component code . The experiment showed that when using QPSK modulation for the DVB-S2 standard for all coding rates, the energy gain was 0.2-0.3 dB. When using a parallel turbo coding scheme - 0.5 dB.

Claims (2)

1. The method of error-correcting decoding of signals obtained using a low density parity check code, which consists in the fact that after decoding a low density parity check code, a procedure for identifying and eliminating short unresolved cycles in the Tanner graph is performed, namely, the threshold value is determined a plurality of indices of invalid bits, based on the obtained set, construct a vector of occurrence frequencies G, determine indices having a maximum frequency of occurrence in the vector G, change to x the opposite sign in the code word that was sent to the decoder, and again decode the resulting word, characterized in that iterative decoding every ten iterations forms an additional vector of reliability of the soft decisions of the demodulator, which corrects the soft decisions of the demodulator in the process of decoding the code and determine the set of unreliable bits, by which, in the future, build the vector of frequencies of occurrence of the bit indices during the identification and elimination procedure short cycles in the Tanner graph. 2. An error-correcting device for decoding signals received using a low-density parity check code containing an input buffer, a bit likelihood log-shaper generator, an LDPC iterative decoder, an output buffer and a control device, and an input buffer output connected to the input of the bit-likelihood ratio generator, the output of which is connected to an iterative LDPC decoder, and the output of the latter is connected to the output buffer input, characterized in that the of the log of the likelihood ratio of bits and the counter of intermediate iterations of decoding, the counter input is connected to the second output of the iterative decoder LDPC, and the output of the counter of intermediate iterations is connected to the input of the module of the correction of the log likelihood of bits, the output of which is connected to the second input of the generator of the log likelihood of the bits.

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