RU2520538C1 - NANOSIZE STRUCTURE WITH QUASI-ONE-DIMENSIONAL CONDUCTING TIN FIBRES IN GaAs LATTICE - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to nanosize semiconductor structures comprising a system of quasi-one-dimensional conducting channels used to make nanoelectronic and nanophotonic devices. The technical result is increase in electron concentration in the active region of the nanostructure. The nanostructure obtained from molecular beam epitaxy contains a monocrystalline semi-insulating vicinal substrate of GaAs (100) with misorientation angle of 0.3°-0.4° in the <011> direction, a buffer undoped layer of GaAs, a tin delta-doped layer which covers the undoped GaAs layer and a silicon-doped contact layer of GaAs. During epitaxy, a system of atomically smooth terraces separated by steps with monoatomic thickness is formed on the surface of the buffer layer. During doping, tin atoms accumulate near the steps as a result of surface diffusion to form conducting nanofibres of tin atoms lying in one plane parallel to each other.

EFFECT: use of tin in GaAs instead of silicon increases electron concentration in the delta layer since tin has a higher solubility limit and does not exhibit amphoteric properties.

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Description

Technical field

The present invention relates to nanoscale semiconductor structures containing a system of quasi-one-dimensional conductive channels used for the manufacture of nanoelectronics and nanophotonics devices.

State of the art

In recent years, the development and creation of devices based on quasi-one-dimensional and quasi-zero-dimensional systems along with the tendency to miniaturization is one of the main areas of nanoelectronics. Dimensional quantization effects in objects with linear dimensions of less than tens of nanometers make it possible to improve the performance of semiconductor electronics products (increase speed, reduce energy consumption) and optoelectronics, as well as create fundamentally new devices based on the use of these effects.

There are a large number of methods for the formation of semiconductor structures with quantum filaments. A wide group is formed by methods based on the use of two-dimensional semiconductor systems (for example, metal-insulator-semiconductor structures, heterojunctions, and δ-doped layers) as initial structures. To limit electrons in one more direction, using electron, ultraviolet, or X-ray lithography and subsequent chemical etching (liquid or plasmachemical) from a two-dimensional structure, nanobands of controlled sizes and shapes are formed. One-dimensional charge carriers in a quantum well can also be created using metal-shaped contacts of a special shape grown on the surface of a sample parallel to the plane of two-dimensional carriers. The application of various voltages to the contacts, which creates an electrostatic potential for restricting the motion of two-dimensional electrons, makes it possible to control the width of the nanowire and the concentration of charge carriers.

Another method for creating nanowires is a method based on etching V grooves in a substrate. During the epitaxial growth of a thin GaAs layer on a substrate in which V grooves are preliminarily etched and then an AlGaAs layer, the GaAs thickness in the groove will be larger than in the rest, and the charge carriers will tend to localize at the quantum levels of the groove, since the size of the groove inside the groove quantum levels are lower than in the rest of GaAs.

The considered methods possess, along with simplicity and clarity, all the disadvantages inherent in lithography and etching methods. These disadvantages include: heterogeneity of thickness and shape, always accompanying the etching process; defects introduced to the interface during etching; the minimum size of nanowires, determined by the resolution of the used lithography method and amounting to approximately 0.15 μm, 30 nm, 3 ÷ 20 nm for ultraviolet, X-ray and electron beam lithography, respectively.

More successful and acceptable were the methods of forming nanowires on vicinal surfaces. A vicinal surface (FIGS. 1, 2) is a surface deflected by a small misorientation angle α with respect to the crystal face with small Miller indices; the vicinal surface is atomically smooth and, under equilibrium conditions, consists of terraces (2) formed by surfaces with small Miller indices and separated by equidistant monoatomic steps (3). Epitaxial growth on vicinal substrates with different orientations, directions, and misorientation angles with respect to the singular face allows one to obtain periodic nanowire structures with controlled sizes, orientations, and periods. Due to planar geometry, nanowire systems grown on a vicinal substrate are convenient for the production of semiconductor devices with a channel of one-dimensional conductive threads (field effect transistors).

In the patent [1], it is proposed to grow a vertical superlattice of nanobands consisting of single-crystal layers of a narrow-gap semiconductor A (for example, InAs) and a wide-gap semiconductor B (for example, GaAs), on a GaAs substrate deviated from the plane (100) by an angle of 2 ° or less. The formation of an array of nanobands occurs during epitaxy by alternate deposition of materials A and B under conditions of increased surface diffusion of the deposited adatoms, in the layer-by-layer growth of the “step flow growth”. The amount of material A planted on the surface of terraces in one cycle is less than 1/2 of the monolayer. Accordingly, the amount of wide-gap material B is more than 1/2 of the monolayer so that exactly one monolayer is deposited in a single cycle. After repeating several cycles, the structure will be a periodic system of alternating nanobands of semiconductors A and B. The need for precise control (up to a fraction of a monolayer) of the amount of deposited material during cyclic layered growth makes this structure difficult to implement.

In the invention [2], adopted as an analogue, a method of epitaxial growth on a vicinal substrate of an array of conductive nanowires consisting of impurity atoms was proposed. The method includes the following steps: the formation of a vicinal surface of step atomic terraces, the deposition of a dopant monolayer fraction in the form of nanosized strips less than the width of atomic terraces, the closure of nanosized strips with a layer of undoped semiconductor, annealing of the semiconductor structure. Doped impurity nanobands can be obtained as follows: a) due to the collimated impurity beam falling at a sliding angle to the substrate surface in the direction of the steps descending, in which part of the terrace surface is obscured by the edge of the previous terrace and is not covered by impurity atoms; b) due to the deposition of impurity atoms at a normal angle of incidence, when impurity atoms fill the entire surface of the substrate, and subsequent exposure to the sample of an ionic or chemical etchant. The flow of ions or etchant molecules is directed at a sliding angle to the surface of the sample. Due to the small angle of incidence of the etchant, some areas of the terrace surface are not exposed to the etchant, and other areas are etched to form nanosized doped semiconductors. The disadvantage of the described method for producing doped impurity nanowires is the use of technically complex small-angle growth, as well as the use of annealing, which leads to diffusion smearing of the nanowire distribution.

In [3], a method for producing a nanoscale filament system adopted as a prototype of the present invention was described. When silicon is doped with vicinal (001) GaAs (1) faces with silicon with a misorientation angle of 2 °, one can obtain ordered superstructures in the form of nanowires (7) containing silicon atoms (Fig. 3). The main difference from the invention [2] is the use of the phenomenon of self-organization - the ordered introduction of silicon atoms at the edges of the steps of the vicinal face. A stepped surface is characterized by a burst of potential energy at the edges of steps (3) for adatoms of an epitaxially growing substance, for example, silicon atoms. If the average diffusion length of the adatom on the surface exceeds the size of the terraces of the vicinal face L, then the epitaxial film growth occurs due to the attachment of adatoms to the edges of steps without the formation of germinal islands on the terraces. By setting the desired size of the terraces of the vicinal substrate, choosing growth conditions, accurately dosing the number of adatoms of the substance falling onto the surface, it is possible to form on the surface, including threads, which are chains of atoms "attached" to the edges of steps. The authors of [3] demonstrated the formation of silicon nanowires, the distance between which, determined by a misorientation angle of 2 °, is 8 nm. Such structures are primarily two-dimensional, despite the quasi-one-dimensional character of the distribution of impurity atoms, since the distance between the nanowires is less than the Bohr radius of a shallow donor impurity in GaAs (of the order of 10 nm).

Disclosure of invention

The problem solved by the present invention is to increase the conductivity of the channel of a field effect transistor made on the basis of structures with quasi-one-dimensional conductive nanowires. The technical result that allows you to complete the task are:

a) an increase in the electron concentration in the active region of the nanostructure;

b) the formation of an array of parallel quasi-one-dimensional conductive nanowires. The nanowires are grown at such a distance from each other that the main quantum states of neighboring nanowires do not overlap.

The structure proposed as an active region for a GaAs field-effect transistor has the following structure (Fig. 4):

a) the vicinal GaAs (100) substrate with a misorientation angle of 0.3 ° ÷ 0.4 ° in the direction of the type <011> (1);

b) undoped GaAs buffer layer (4);

c) 5 — doped with tin layer with an impurity concentration (5);

d) closing and contact layers of GaAs (6);

The technical result is achieved, firstly, by using a vicinal GaAs substrate with an extremely low misorientation angle of 0.3 ° ÷ 0.4 ° and, secondly, by using tin as a dopant.

Brief Description of the Drawings

In the drawings, the width of the terraces and the height of the steps of the vicinal surface are shown schematically, without respecting the proportions. In the present invention, for a GaAs (100) vicinal substrate with a misorientation angle of 0.3 ° to 0.4 °, the width of the terraces is more than 100 times the height of the steps.

Figure 1 presents a schematic view of the vicinal surface of a GaAs (100) substrate.

2 is a schematic cross-sectional side view of the vicinal surface of a GaAs (100) substrate.

Figure 3 schematically illustrates the phenomenon of segregation of impurity atoms of Si or Sn near the steps of the vicinal GaAs surface and the formation of nanowires of impurity atoms. Some impurities do not participate in the formation of nanowires and remain on the terraces.

Figure 4 presents a layered diagram of a nanoscale structure with quasi-one-dimensional conductive tin filaments in a GaAs lattice, proposed as an invention.

Figure 5 presents a diagram of a nanoscale structure with quasi-one-dimensional conductive tin filaments in a GaAs lattice grown according to the claimed invention.

The implementation of the invention

A diagram of a GaAs nanostructure proposed as an active region for a field effect transistor is shown in FIG. 4. Each nanostructure layer performs the following functions:

GaAs (100) vicinal substrate (1) with a misorientation angle of 0.3 ° ÷ 0.4 ° in the <011> type direction sets the average distance between tin nanowires during subsequent delta doping equal to the average distance between steps (terrace width); the undoped GaAs buffer layer (4) is designed to produce as perfect atomically smooth terraces on its surface as possible;

A δ-doped tin layer with an impurity concentration greater than 2 × 10 ^-2 cm ^-2 (5) serves to obtain an ordered periodic superstructure containing nanowires of tin atoms. Layer concentration provides overlapping impurity wave functions inside nanowires and the formation of one-dimensional electronic states; the closing and contact layers of GaAs (6) serve to “close” the atoms deposited during δ doping and to form ohmic contacts with a low resistivity, which is necessary to create semiconductor devices.

Features of the choice of a certain angle of misorientation of the vicinal substrate are as follows. For GaAs (100) substrates with misorientation in the <011> type direction, the surface consists of steps one monolayer high (in this case, one monolayer is 1/2 of the lattice constant of gallium arsenide approximately 0.283 nm), separated by terraces with an exact crystallographic orientation of the type ( one hundred). The width of the terraces, or the distance between the steps L = 0.283 / tg (α) nm, where α is the disorientation angle. To form a system of impurity nanowires on the vicinal surface by attaching adatoms to the edges of steps, the average diffusion length of the adatom on the surface should exceed the size of the terraces of the vicinal face. Otherwise, the epitaxial growth of the film will be due to the formation of germinal islands on the terraces, the dopant will be uniformly distributed on the surface. On the other hand, a strong decrease in the width L is also impractical, since the neighboring tin filaments (as a result of fluctuations in the width of the terraces) may turn out to be too close to each other with the inevitable significant overlap of the wave functions of the conduction electrons with the formation of a two-dimensional system (the Bohr radius of an electron with a small impurity in GaAs is approximately 10 nm). The proposed misorientation angle α = 0.3 ° ÷ 0.4 ° corresponds to the period of the structure L ~ 40 ÷ 50 nm and ensures the formation of an array of nanowires with the highest possible density, at which the existence of quasi-one-dimensional conducting threads is still possible.

The choice of tin as a dopant for GaAs is associated with its following features compared to silicon:

a) the tendency of tin to segregate on a growth surface with unsaturated bonds. Compared to silicon, this property of tin leads to an increase in the concentration of impurity atoms near the steps, to a decrease in the blurring of the impurity distribution profile over the nanowire cross section;

b) a greater solubility limit of tin;

c) tin does not exhibit amphotericity inherent in silicon, which reduces the utilization of electrically active impurities.

Due to these differences, the use of tin to create conductive quantum filaments in gallium arsenide seems preferable from the point of view of expected characteristics in comparison with silicon: the electron concentration in nanowires increases, and the conductivity of the field-effect transistor channel increases.

The proposed nanostructure is grown in a molecular beam epitaxy unit. The sample manufacturing process can be divided into the following stages:

1. Pregrowth preparation of the vicinal substrate (1) with a given angle and direction of disorientation. After removal of the oxide, the surface of the substrate is not smooth enough. In addition, traces of certain impurities, in particular carbon, may remain on the surface of the substrate, leading under certain conditions to faceting the surface, that is, the formation of microregions with a different orientation from the original.

2. Growing a buffer layer (4) of gallium arsenide, which provides the creation of the most perfect stepped surface with smooth terraces, preparing its surface for the deposition of impurities.

3. Alloying the surface. It is advisable to plant tin at a moderate speed in order to avoid the interaction of tin atoms with each other with the formation of a metal phase. In addition, it is advisable to withstand a certain pause after doping to provide additional time for tin adatoms migrating over the surface of the substrate to “meet” with the edges of the steps of the vicinal face.

4. The growth of planted chains of tin atoms in the modes that ensure the activation of dopant atoms, on the one hand, and prevent the diffusion and segregation of tin atoms during overgrowing, on the other. Gallium arsenide planted on the edges of the steps of tin should be grown at a maximum speed, minimum substrate temperature, and a sufficiently high ratio of arsenic to gallium fluxes. These measures are necessary to prevent tin diffusion and segregation during overgrowing. On the other hand, tin atoms must be in the crystal lattice, replacing gallium atoms in order to remain an electrically active shallow donor impurity. At an excessively low epitaxial growth temperature, too many growth defects such as gallium vacancies can form. This in turn can lead to a large concentration of deep levels and degrade the electrical properties of the grown structures.

According to the invention, the following nanostructure sample was grown (FIG. 5). An unalloyed GaAs (4) buffer layer with a thickness of 0.8 μm and a delta-doped tin layer (5) with a layer concentration of 5 × 10 ¹² cm were grown on a GaAs vicinal substrate (1) with a misorientation angle of 0.3 ° ÷ 0.4 ° in the <011> type direction ^-2 , undoped GaAs closing layer 40 nm thick (6), silicon-doped with a concentration of 4 × 10 ¹⁸ cm ^-3 GaAs contact layer 15 nm thick (8). The mobility values µ = 1700 cm ² / V · s and the electron concentration n = 2.7 × 10 ¹² at room temperature were obtained; the relative error is 10%. The resistance anisotropy coefficient for weak fields (in the region of a linear dependence of the electron drift velocity on the applied field) is approximately 2 at room temperature and increases to 2.5 at a temperature of 77 K. The anisotropy of resistance also remains in strong electric fields, which clearly demonstrate the presence of a quasi-one-dimensional potential relief.

Information sources

1. Hiroyuki Sakaki. "Grid-Inserted quantum structure". EP 0427905 (05.22.1991).

2. S. Fernandez-Ceballos, G. Manai, I.V.Shvets. "Method of forming conducting nanowires." US 7569470 (August 4, 2009).

3. Z. M. Wang, L. Daweritz, K. N. Ploog. "Controllable step bunching induced by Si deposition on the vicinal GaAs (001) surface." Surface Science, v. 459, p. L482-L486 (2000).

Claims (1)

Nanoscale structure with quasi-one-dimensional conducting tin filaments in a GaAs lattice, including a single-crystal semi-insulating vicinal GaAs (100) substrate with a misorientation angle of 0.3 ° ÷ 0.4 ° in the <011> direction, an unalloyed buffer GaAs layer, a delta-doped layer that covers an unalloyed GaAs layer and contact silicon-doped GaAs layer, characterized in that tin is used as an impurity for the delta-doped layer.

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