RU2519446C2 - Selective amplifier - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: selective amplifier comprises a first (1) input transistor, the base of which is connected to the input (2) of the device, and the collector is connected to the output (3) of the device and is connected through a first (4) frequency-setting resistor to a first (5) power supply bus, a first (6) balancing capacitor connected via alternating current in parallel to the first (4) ) frequency-setting resistor, a second (7) input transistor, the collector of which is connected to a second (8) power supply bus, and the emitter is connected to the emitter of the first (1) input transistor, a second (9) frequency-setting resistor, the first lead of which is connected to the base of the second (7) input transistor, a second (10) balancing capacitor, the first lead of which is connected to the base of the second (7) input transistor. The second lead of the second (10) balancing capacitor is connected to the output (3) of the device, and the second lead of the second (9) frequency-setting resistor is connected to a first (11) auxiliary voltage source.

EFFECT: reduced overall power consumption.

7 cl, 11 dwg

Description

The present invention relates to the field of radio engineering and communications and can be used in devices for filtering radio signals, television, radar, etc.

Integrated operational amplifiers with special RC correction elements that form the amplitude-frequency characteristic of the resonant type are widely used today in the tasks of extracting high-frequency signals [1, 2]. However, the classical construction of such selective amplifiers (DUTs) is accompanied by significant energy losses, which are mainly used to ensure the static mode of a sufficiently large number of secondary transistors forming an operational amplifier [1, 2]. In this regard, it is very urgent to build selective amplifiers that provide the selection of a narrow spectrum of signals with a sufficiently high quality factor (Q) of the resonance characteristic (Q = 2 ÷ 10) at low power consumption.

Known circuits of DUTs based on bipolar transistors, which provide the formation of the amplitude-frequency characteristics of the voltage gain in a given frequency range Δf = f _B -f _n [3-17]. Moreover, their upper cutoff frequency f _{in is} sometimes formed by the inertia of the transistors of the circuit (capacitance per substrate), and the lower f _n is determined by a corrective isolation capacitor.

The closest prototype of the claimed device is a selective amplifier, presented in the structure of the circuit according to patent application US No. 2008/0211580, fig.7A. It contains the first 1 input transistor, the base of which is connected to the input 2 of the device, and the collector is connected to the output of 3 devices and through the first 4 frequency-setting resistor connected to the first 5 bus of the power source, the first 6 correction capacitor connected by alternating current parallel to the first 4 frequency-setting resistor , the second 7 input transistor, the collector of which is connected to the second 8 bus of the power source, and the emitter is connected to the emitter of the first 1 input transistor, the second 9 frequency-setting resistor, the first output of which connected to the base of the second 7 input transistor, the second 10 correction capacitor, the first output of which is connected to the base of the second 7 input transistor.

амплитудно-частотной характеристики (АЧХ) и большой коэффициент усиления по напряжению К₀>1 на частоте квазирезонанса (f₀).A significant drawback of the known YiU prototype is that it does not provide high quality factor $$Q\approx \frac{f_0}{f_{\mathrm{at}}-f_n}$$

amplitude-frequency characteristics (AFC) and a large voltage gain coefficient K ₀ > 1 at the quasi-resonance frequency (f ₀ ).

The main objective of the invention is to increase the quality factor of the frequency response of the DUT and its gain in voltage (K ₀ ) at a frequency of quasi-resonance f ₀ . This allows in some cases to reduce the overall energy consumption and implement a high-quality selective device.

The problem is solved in that in the selective amplifier of figure 1, containing the first 1 input transistor, the base of which is connected to the input 2 of the device, and the collector is connected to the output 3 of the device and through the first 4 frequency-setting resistor connected to the first 5 bus power source, the first 6 a correction capacitor connected by alternating current parallel to the first 4 frequency-setting resistor, the second 7 input transistor, the collector of which is connected to the second 8 bus of the power source, and the emitter is connected to the emitter of the first 1 input transistor, the second 9 frequency-setting resistor, the first output of which is connected to the base of the second 7 input transistor, the second 10 correction capacitor, the first output of which is connected to the base of the second 7 input transistor, new elements and connections are provided - the second output of the second 10 correction capacitor is connected to output 3 device, and the second output of the second 9 frequency-setting resistor is connected to the first 11 source of auxiliary voltage.

The amplifier circuit of the prototype is shown in the drawing of figure 1. The drawing of figure 2 presents a diagram of the inventive device in accordance with claim 1 of the claims.

In the drawing of figure 3 presents a diagram of the claimed IU in accordance with paragraph 2 of the claims, and in the drawing of figure 4 in accordance with paragraph 3 of the claims.

In the drawing of FIG. 5, a diagram of the claimed IU is presented in accordance with claim 4, and in the drawing of FIG. 6 in accordance with claim 5.

In the drawing of Fig.7 shows a diagram of the claimed IU in accordance with paragraph 6 of the claims, and in the drawing of Fig.8 in accordance with paragraph 7 of the claims.

The drawing of Fig.9 shows a diagram of the control system of Fig.6 in the elemental basis of the technological process ABMK_1_3 (Minsk) in the environment of computer simulation PSpice.

The drawing of Fig. 10 shows the logarithmic amplitude-frequency (LFC) and phase-frequency (PFC) characteristics of the DUT of Fig. 9 in the frequency range from 10 kHz to 10 GHz at Rvar = 22 kOhm, Cvar = 1 fF, Rvar2 = 610 Ohm, Cvar3 = 20 pF, Cvar2 = 9 pF.

In the drawing of FIG. 11 shows the LACH of the DUT of FIG. 9 with values of resistance Rvar2 varying in the range from 540 Ohms to 600 Ohms.

The selective amplifier of Fig. 2 contains a first 1 input transistor, the base of which is connected to the input 2 of the device, and the collector is connected to the output 3 of the device and through the first 4 frequency-setting resistor connected to the first 5 bus of the power source, the first 6 correction capacitor connected in alternating current in parallel the first 4 frequency setting resistor, the second 7 input transistor, the collector of which is connected to the second 8 bus of the power source, and the emitter is connected to the emitter of the first 1 input transistor, the second 9 frequency setting side, the first output of which is connected to the base of the second 7 input transistor, the second 10 correction capacitor, the first output of which is connected to the base of the second 7 input transistor. The second output of the second 10 correction capacitor is connected to the output 3 of the device, and the second output of the second 9 frequency-setting resistor is connected to the first 11 source of auxiliary voltage.

In the drawing of FIG. 3, in accordance with claim 2, as the first 1 input transistor, a field-effect transistor is used with a pn junction, the gate of which is equivalent to the base of transistor 1, its source is emitter, and the drain is the collector, and as the first 11 of the auxiliary voltage source, the potential of the second 8 bus of the power source is used, and the input voltage source 12 is connected between the input 2 of the device and the second 8 bus of the power source.

In the drawing of FIG. 4, in accordance with claim 3, the input 2 of the device is connected to the second 8 bus of the power source through the third 13 frequency-setting resistor, the input voltage source 14 is connected to the input 2 of the device through the third 15 correction capacitor, and as the first 1 input transistor, a field-effect transistor is used with a pn junction, the gate of which is equivalent to the base of transistor 1, the source is to its emitter, the drain is to the collector, and the potential is used as the first 11 source of auxiliary voltage al 8 second power supply bus.

In the drawing of FIG. 5, in accordance with claim 4, the potential of the common bus of power supplies 16 is used as the auxiliary voltage source 11, the input voltage source 17 is connected between the input 2 of the device and the common bus of power supplies 16, and as a second 7 the input transistor uses a field effect transistor with a pn junction, the gate of which is equivalent to the base of transistor 7, the source to the emitter, and the drain to the collector of this transistor 7.

In the drawing of FIG. 6, in accordance with claim 5, the potential of the common bus 16 of the power sources is used as the auxiliary voltage source 11, the input 2 of the device is connected to the common bus of the power sources 16 through the fourth 18 frequency-setting resistor, the input voltage source 19 is connected for alternating current with input 2 of the device through the fourth 20 frequency-setting capacitor and connected to a common bus of power sources 16, and as a second 7 input transistor, a field-effect transistor with a control p -n junction, the gate of which is equivalent to the base of transistor 7, the source to the emitter, and the collector to the drain of this transistor 7.

In the drawing of Fig. 7, in accordance with claim 6, the input voltage source 21 is connected to the input 2 of the device through the fifth isolation capacitor 22, the potential of the second 8 bus power supply is used as the source of additional voltage 11, and the input 2 of the device is connected to base and collector of the first 23 additional transistor through the first 24 additional resistor, the emitter of the first 23 additional transistor is connected to the emitter of the second 25 additional transistor, the collector of the second 25 additional The second transistor is connected to the second 8 bus of the power supply, between the base of this transistor 25 and the second 8 bus of the power supply, a second 26 additional resistor is connected, and the collector of the first 23 additional transistor is connected to the first 5 bus of the power supply through the third 27 additional resistor.

In the drawing of Fig. 8, in accordance with claim 7 of the claims, an auxiliary bipolar switch 28, for example, a pn junction, is included in the source of the field effect transistor with the control pn junction, which is used as the second 7 input transistor.

Consider the operation of the circuit of figure 3.

The input voltage source u _I (12) changes the drain current of the first 1 input transistor. The nature of the drain load of this transistor, formed by resistors 4 and 9, as well as capacitors 6 and 10, converts this current into the output signal of the DUT. Moreover, the presence of a capacitive divider formed by capacitors 6 and 10, provides a functional dependence of this signal, corresponding to the frequency characteristics of the selective amplifier.

The complex transfer coefficient of the DUT of Fig. 3 as the ratio of the output voltage (output of the device 3) to the input voltage u _in (1) is determined by the formula, which can be obtained using methods of analysis of electronic circuits:

$$K\left(jf\right)=\frac{u_3}{u_{\mathrm{at}x}}=K_0\frac{jf\frac{f_0}{\mathrm{<figure-callout\; id="0"\; label="Q\; f"\; filenames="00000026.png,00000027.png"\; state="\{\{state\}\}">Q\; </figure-callout>}}}{f_{}^{}},\left(\mathrm{one}\right)$$

where f is the frequency of the input signal;

f ₀ is the frequency of the quasi-resonance of the selective amplifier;

Q is the quality factor of the frequency response of the selective amplifier;

To ₀ is the gain of the DUT at the frequency of quasi-resonance f ₀ .

Moreover:

$${\mathrm{<figure-callout\; id="0"\; label="f"\; filenames="00000026.png,00000027.png"\; state="\{\{state\}\}">f</figure-callout>}}_0=\frac{\mathrm{one}}{2\pi \sqrt{C_6{C}_{10}{R}_{\mathrm{four}}{R}_9}},\left(2\right)$$

where C ₆ , C ₁₀ , R ₄ , R ₉ are the parameters of the corresponding elements of the circuit 6, 10, 4 and 9;

The quality factor of the DUT is determined by the formula

$$Q^{-\mathrm{one}}={\mathrm{<figure-callout\; id="0"\; label="D"\; filenames="00000026.png,00000027.png"\; state="\{\{state\}\}">D</figure-callout>}}_0+\sqrt{\frac{C_{10}}{C_6}}\sqrt{\frac{R_9}{R_{\mathrm{four}}}}\left[\mathrm{one}-\frac{R_{\mathrm{four}}}{h_{11.7}+S_{\mathrm{one}}^{-\mathrm{one}}}\right],\left(3\right)$$

where h _11.7 is the input resistance of the transistor 7 in a circuit with a common base;

- эквивалентное затухание пассивной частото-зависимой цепи; $${\mathrm{<figure-callout\; id="0"\; label="D"\; filenames="00000026.png,00000027.png"\; state="\{\{state\}\}">D</figure-callout>}}_0=\left(\sqrt{\frac{C_6}{{\mathrm{<figure-callout\; id="10"\; label="C"\; filenames="00000020.png,00000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{10}}}+\sqrt{\frac{C_{10}}{C_6}}\right)\sqrt{\frac{R_{\mathrm{four}}}{R_9}}$$

- equivalent attenuation of a passive frequency-dependent circuit;

S ₁ - the steepness of the transistor 1;

By choosing the parameters of the elements included in the formula (3), it is possible to provide Q >> 1.

The formula for the gain K ₀ in the complex transfer coefficient (1) has the form

$${\mathrm{<figure-callout\; id="0"\; label="K"\; filenames="00000026.png,00000027.png"\; state="\{\{state\}\}">K</figure-callout>}}_0=-QS\sqrt{R_{\mathrm{four}}{R}_9}\sqrt{\frac{C_{10}}{{\mathrm{<figure-callout\; id="6"\; label="C"\; filenames="00000020.png,00000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_6}},\left(\mathrm{four}\right)$$

.Where $$S\approx \frac{\mathrm{one}}{\left(h_{11.7}+S_{\mathrm{one}}^{-\mathrm{one}}\right)}$$

.

From relation (3) it follows the possibility of parametric optimization of the DUT scheme when implementing the required Q factor. Really,

$$Q^{-\mathrm{one}}=\frac{m\left({\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="00000020.png,00000021.png"\; state="\{\{state\}\}">k</figure-callout>}}^2+\mathrm{one}\right)}{k}+\frac{\mathrm{one}-R_{\mathrm{four}}S}{mk},\left(5\right)$$

; $$m=\sqrt{\frac{R_4}{R_9}}$$

.Where $$k=\sqrt{\frac{C_6}{{\mathrm{<figure-callout\; id="10"\; label="C"\; filenames="00000020.png,00000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{10}}}$$

; $$m=\sqrt{\frac{R_{\mathrm{four}}}{{\mathrm{<figure-callout\; id="9"\; label="R"\; filenames="00000020.png,00000021.png"\; state="\{\{state\}\}">R</figure-callout>}}_9}}$$

.

In this case, parametric sensitivities

$$S_{C_6}^Q=-S_{C_{10}}^Q=\frac{\mathrm{one}}{2}\left[\frac{m\left(k^2-\mathrm{one}\right)}{k{D}_p}-\frac{S{R}_{\mathrm{four}}}{mk}\right],\left(6\right)$$

$$S_{R_{\mathrm{four}}}^Q=-S_{R_9}^Q=\frac{\mathrm{one}}{2}\left[\frac{m\left(k^2-\mathrm{one}\right)}{km}-\frac{\mathrm{one}+S{R}_{\mathrm{four}}}{mk}\right],\left(7\right)$$

$$S_S^Q=-\frac{QS{R}_{\mathrm{four}}}{mk}\left(8\right)$$

can be optimized according to one of the criteria - total sensitivity, rms sensitivity, etc. So, while minimizing the rms sensitivity

$$k_{opt}=\mathrm{1,6}{\left(S{R}_{\mathrm{four}}\right)}_{opt}=\mathrm{2.5,}\left(9\right)$$

the ratio between resistive elements is determined from condition (5) of the practical implementation of Q.

параметрические чувствительности основных параметров ИУ имеют следующий вид:Under conditions of C ₁₀ = C ₆ = C and $$h_{11.7}+S_{\mathrm{one}}^{-\mathrm{one}}=R_{\mathrm{four}}$$

The parametric sensitivities of the main parameters of the DUT are as follows:

$$S_{C_{10}}^{{\mathrm{<figure-callout\; id="0"\; label="f"\; filenames="00000026.png,00000027.png"\; state="\{\{state\}\}">f</figure-callout>}}_0}=S_{C_6}^{{\mathrm{<figure-callout\; id="0"\; label="f"\; filenames="00000026.png,00000027.png"\; state="\{\{state\}\}">f</figure-callout>}}_0}=S_{R_{\mathrm{four}}}^{{\mathrm{<figure-callout\; id="0"\; label="f"\; filenames="00000026.png,00000027.png"\; state="\{\{state\}\}">f</figure-callout>}}_0}=S_{R_9}^{{\mathrm{<figure-callout\; id="0"\; label="f"\; filenames="00000026.png,00000027.png"\; state="\{\{state\}\}">f</figure-callout>}}_0}=-\frac{\mathrm{one}}{2},\left(10\right)$$

$$S_{C_{10}}^Q=S_{C_6}^Q=0S_{C_{10}}^{{\mathrm{<figure-callout\; id="0"\; label="K"\; filenames="00000026.png,00000027.png"\; state="\{\{state\}\}">K</figure-callout>}}_0}=-S_{C_6}^{{\mathrm{<figure-callout\; id="0"\; label="K"\; filenames="00000026.png,00000027.png"\; state="\{\{state\}\}">K</figure-callout>}}_0}=\frac{\mathrm{one}}{2},\left(\mathrm{eleven}\right)$$

$$S_{R_9}^Q=-S_{R_{\mathrm{four}}}^Q=\frac{\mathrm{<figure-callout\; id="2"\; label="one"\; filenames="00000020.png,00000021.png"\; state="\{\{state\}\}">one</figure-callout>}}{2},S_{R_9}^{{\mathrm{<figure-callout\; id="0"\; label="K"\; filenames="00000026.png,00000027.png"\; state="\{\{state\}\}">K</figure-callout>}}_0}=S_{R_{\mathrm{four}}}^{{\mathrm{<figure-callout\; id="0"\; label="K"\; filenames="00000026.png,00000027.png"\; state="\{\{state\}\}">K</figure-callout>}}_0}=\frac{\mathrm{one}}{2}.\left(12\right)$$

This characterizes the scheme of the claimed IU in the class of low-sensitivity links of the second order. In this case, K ₀ = Q.

Presented on the drawings, Fig.10 - Fig.11 simulation results of the proposed IU confirm the indicated properties of the claimed circuit.

A feature of the circuit of Fig. 3 (P2 of the claims) is the minimum possible current consumption from the power source, as well as working with unipolar power.

The circuit of FIG. 4 (PZ of the claims) has additional quality with unipolar power supply — high signal attenuation in the low frequency range.

The scheme of figure 5 (P4 of the claims) has bipolar power with a minimum current consumption in the elemental basis ABMK_1_3 (NPO Integral, Minsk).

In the circuit of FIG. 6 (A5 of the claims), RC circuits are provided that provide a deeper attenuation of the input signal in the low frequency range.

The peculiarity of the circuit of Fig. 7 (P6 of the claims) is unipolar power and the possibility of realizing on p-np and n-p-n transistors the analog base matrix crystal ABMK_1_3 (NPO Integral, Minsk).

In the circuit of FIG. 8 (P7 of the claims), a further reduction in current consumption is provided by transferring the field effect transistor (ABMK_1_3 technology) to micro mode.

Thus, the proposed circuitry solutions of the DUT are characterized by higher values of the gain coefficient K ₀ at the frequency of quasi-resonance f ₀ , as well as increased values of the quality factor Q, characterizing its selective properties at low power consumption.

BIBLIOGRAPHIC LIST

1. Design of Bipolar Differential OpAmps with Unity Gain Bandwidth up to 23 GHz \ N.Prokopenko, A. Budyakov, K.Schmalz, C.Scheytt, P. Ostrovskyy \\ Proceeding of the 4-th European Conference on Circuits and Systems for Communications - ECCSC′08 / Politehnica University, Bucharest, Romania: July 10-11, 2008. - pp.50-53

2. Microwave SF blocks of communication systems based on fully differential operational amplifiers \ Prokopenko NN, Budyakov AS, K.Schmalz, S.Scheytt \\ Problems of developing promising micro- and nanoelectronic systems - 2010. Proceedings / under the general. ed. Academician of the Russian Academy of Sciences A.L. Stempkovsky. - M .: IPPM RAS, 2010. - P.583-586

3. Patent application US 2008/0012640, fig.4

4. Patent US 7.705.677, fig.2

5. Patent US 6.396.346

6. Patent US 5.767.542, fig.2, fig.3

7. Patent US 6.690.231, fig.6

8. Patent US 6.624.699

9. Patent US 6.198.348, fig.2

10. Patent EP 1.480.333, fig. 1, fig. 17

11. JP patent 2010-28311

12. Patent WO 03094344, fig. 3

13. Patent application US 2003/0206062, fig. 3, fig. 4

14. Patent application US 2006/0125561, fig. 1

15. Patent WO 2009/029284

16. Patent application US 2007/0146070, fig. 1

17. Patent application US 2010/0013557.

Claims (7)

1. A selective amplifier containing the first (1) input transistor, the base of which is connected to the input (2) of the device, and the collector is connected to the output (3) of the device and through the first (4) frequency-setting resistor is connected to the first (5) bus of the power source, the first (6) correction capacitor connected by alternating current parallel to the first (4) frequency-setting resistor, the second (7) input transistor, the collector of which is connected to the second (8) bus of the power source, and the emitter is connected to the emitter of the first (1) input transistor, second (9) frequency a supply resistor, the first terminal of which is connected to the base of the second (7) input transistor, the second (10) correction capacitor, the first terminal of which is connected to the base of the second (7) input transistor, characterized in that the second output of the second (10) correction capacitor is connected to the output (3) of the device, and the second output of the second (9) frequency-setting resistor is connected to the first (11) auxiliary voltage source. 2. The selective amplifier according to claim 1, characterized in that the first transistor (1) uses a field effect transistor with a pn junction, the gate of which is equivalent to the base of the transistor (1), the source is its emitter, and the drain is the collector, and as the first (11) auxiliary voltage source, the potential of the second (8) bus of the power source is used, and the input voltage (12) is connected between the input (2) of the device and the second (8) bus of the power source. 3. The selective amplifier according to claim 1, characterized in that the input (2) of the device is connected to the second (8) bus of the power source through the third (13) frequency-setting resistor, the input voltage source (14) is connected to the input (2) of the device through the third (15) a correction capacitor, and a field-effect transistor with a pn junction, the gate of which is equivalent to the base of transistor (1), the source is its emitter, the drain is the collector, and the first (11) is used as the first (1) input transistor auxiliary voltage source used potential of the second (8) power supply bus. 4. The selective amplifier according to claim 1, characterized in that the potential of the common bus of the power sources (16) is used as the auxiliary voltage source (11), the input voltage source (17) is connected between the input (2) of the device and the common bus of the power sources ( 16), and as the second (7) input transistor, a field-effect transistor with a pn junction control is used, the gate of which is equivalent to the base of transistor (7), the source is emitter, and the drain is the collector of this transistor (7). 5. The selective amplifier according to claim 1, characterized in that the potential of the common bus (16) of the power sources is used as the auxiliary voltage source (11), the input (2) of the device is connected to the common bus of the power sources (16) through the fourth (18) a frequency-setting resistor, the input voltage source (19) is connected via alternating current to the input (2) of the device through the fourth (20) frequency-setting capacitor and is connected to a common bus of power sources (16), and a field-effect transistor is used as the second (7) input transistor management The pn junction, whose gate is equivalent to the base of the transistor (7), the source to the emitter, and the collector to the drain of this transistor (7). 6. The selective amplifier according to claim 1, characterized in that the input voltage source (21) is connected to the input (2) of the device through a fifth (22) isolation capacitor, the potential of the second (8) source bus is used as an additional voltage source (11) power, and the input (2) of the device is connected to the base and collector of the first (23) additional transistor through the first (24) additional resistor, the emitter of the first (23) additional transistor is connected to the emitter of the second (25) additional transistor, the collector of the second (25) additional The auxiliary transistor is connected to the second (8) bus of the power supply, between the base of this transistor (25) and the second (8) bus of the power supply, a second (26) additional resistor is connected, and the collector of the first (23) additional transistor is connected to the first (5) bus power supply through the third (27) additional resistor. 7. The selective amplifier according to claim 5, characterized in that at the source of the field-effect transistor with a control pn junction, which is used as the second (7) input transistor, an auxiliary two-terminal device (28), for example, a pn junction, is included.

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