RU2516528C2 - Device for stepped motor control - Google Patents

Abstract

FIELD: engines and pumps.

SUBSTANCE: invention relates to ACS and can be used in systems with discrete drives built around three-phase, four-phase and six-phase steeped motors. Claimed device implements Hamming coding algorithm by hardware means to reveal and indicate the address of single fault. For this, proposed device incorporates 1^st, 2^nd and 3^rd convolves, reference check discharge buses, indicator, power amplifier unit with current and voltages tranducers for every phase.

EFFECT: expanded operating performances, variable timing mode controlled by switching selection buses.

3 tbl, 1 dwg

Description

The invention relates to the field of automation and can be used in systems with a discrete electric drive with automatic detection of single failures based on three-phase, four-phase and six-phase stepper motors.

It is known [1] a device for detecting failures in a step-by-step drive, comprising a synchronization unit, a reversible ring shift register, an element for comparing codes, threshold current and voltage sensors included in the circuit of each phase, while the outputs of the current sensors are connected to the first inputs of logic elements 2I, the outputs of the voltage sensors to the second inputs, and the outputs of the elements 2I are connected to the discharge inputs of the ring reverse shift register and the first inputs of the comparison element, the second inputs of which are connected to the bit and outputs of the shift register. The device detects an open or short circuit in the windings of a four-phase stepper motor with symmetrical pair switching.

The disadvantages of the device are the lack of a pointer to the fault address, as well as the inability to ensure the operation of the stepper motor in a variable cycle mode, controlled by the selection mode switching buses.

Closest to the claimed device is a device for controlling a stepper motor [2], comprising a first, second, third bus for selecting a switching mode, a control bus, a clock bus, a reverse bus, a reversible 2/12 counter, the first, second and third inputs of which are connected to control buses, clock, reverse, respectively, read-only memory, read authorization bus, while the first or fourth outputs of the reverse counter are connected to the inputs of the same-name read-only memory, fifth, sixth, with the eighth, the eighth inputs of which are connected to the third, second, first, seventh buses for selecting the switching mode and reading permission, respectively, and the outputs of the first to sixth read-only memory are the outputs of the same name for the stepper motor control device.

This device implements the well-known switching and parking modes for motors with a different number of phase windings and ensures the operation of the stepper motor in a variable cycle mode controlled by the switching mode selection buses.

However, this device does not detect a malfunction and does not indicate their address.

The invention is aimed at expanding the functionality of the device. This is achieved by the fact that the first, second, third convolution schemes, outputs 10, 11, 12 of a permanent storage device representing the reference control bits of the Hamming code, an indicator, a block of power amplifiers with current and voltage sensors, the inputs 1, 2, 4 of the first convolution circuit, inputs 1, 3, 4 of the second convolution circuit, inputs 2, 3, 4 of the third convolution circuit are connected to the same (logical) outputs 1, 2, 3, 4 of the power amplifier block, power outputs a, b, c, d of which are connected to the phase windings A, B, C, D of the step d of the drive, the outputs of the permanent storage device 10, 11, 12 are connected to the inputs of the same name convolution schemes, the outputs of which the first, second, third are connected to the same inputs of the indicator.

The drawing shows a block diagram of a device.

The device contains buses for selecting a switching mode 1-3, a control bus 4, a clock bus 5, a reverse bus 6, a read permission bus 7, a reverse 2/12 counter 8, read-only memory 9, convolution schemes 14, 15, 16, indicator 18, power amplifier unit 13.

The selection mode switching buses 3, 2, 1 are connected to the inputs 5, 6, 7 of the read-only memory, respectively, the control bus 4 is connected to the first input of the reverse counter 8, the clock bus 5 and the reverse bus 6 are connected to the second and third inputs of the reverse counter, respectively read permission bus 7 is connected to the eighth input of the read-only memory 9, the outputs 1, 2, 3, 4 of the reverse counter are connected to the same inputs of the read-only memory 9, the outputs of which 1-6 are connected to the same the strokes of the block of power amplifiers 13, the second (power) outputs of which a, b, c, d are connected to the phase windings A, B, C, D of the motor, respectively, and the first (logical) outputs of the block of power amplifiers 1, 2, 3, 4 are connected respectively, with the inputs 1, 2, 4 of the first convolution circuit 14, with the inputs 1, 3, 4 of the second convolution circuit 15, as well as the inputs 2, 3, 4 of the third convolution circuit 16, the outputs 1, 2, 3 of which are connected to the inputs of the same name indicator 18, the tenth input of the first convolution scheme 14, the eleventh input of the second convolution scheme 15, the twelfth input of the third convolution scheme 16 are respectively with outputs 10, 11, 12 of read-only memory.

The power amplifiers of block 13 contain two channels with a common input in the logical levels of the read-only memory 9, the first channel (logical) generates a logical variable α _i = DT _i ∧ DH _i , with DT _i = DH _i = 1, if the current and voltage in the i phase correspond to the nominal value, otherwise zero, the second channel (power) converts the input phase control signal (tables 1-3) to a level that meets the specifications of the stepper motor.

The device operates as follows.

During the initial installation of the device, the phase windings of the stepper motor are connected to the power outputs of the power amplifiers. For example, the outputs a, b, from power amplifiers are connected respectively to the windings of the first (A), second (B), third (C) phases of a three-phase motor (table 1), which provides three-cycle alternating switching modes (table 1, mode code 111) , six-cycle alternating (table 2, mode code 011). When a four-phase motor is connected, its first (A) - fourth (D) windings are connected to the corresponding outputs a, b, c, d of the power amplifiers, providing four-cycle alternating modes (code 101) or four-cycle pair (table 3, code 001) switching.

The mode codes are set by the upper digits of the address a ₅ a ₆ a _{7 of the} read-only memory (drawing), the value of the lower address digits of which are ₁ , ₂ , a ₃ , and ₄ is represented by the status code of the reverse counter at its outputs 1-4, the highest digits modes are determined by the value of logical variables on the first or third buses for selecting the switching mode.

The value of the logical variable V = 1 of the control bus 4 allows the count of pulses arriving on the clock bus 5 to increase or decrease the status code of the reverse counter, depending on the level on the reverse bus 6.

задает режим стоянки под током, при Е=1 код содержимого постоянного запоминающего устройства по адресу а₁а₂а₃а₄а₅а₆а₇ выводится на его выходные разряды b₁-b₆ (код управления коммутацией фаз двигателя) и c₁-c₃ (эталонный код контрольных разрядов по Хэммингу).The value E = 0 sets the output of the permanent storage device to zeros, providing a de-energized parking mode, the value

sets the stand-by mode under current, at E = 1 the content code of the permanent storage device at the address a ₁ a ₂ a ₃ a ₄ a ₅ a ₆ a ₇ is output to its output bits b ₁ -b ₆ (control code for switching the motor phase switching) and c ₁ -c ₃ (Hamming reference bit code).

Tables 1-3 show examples of the operation of the inventive device in three-cycle alternating modes (mode code 111), six-cycle alternating (mode code 011), four-cycle pair (mode code 001) switching. In table 1, line 1 corresponds to the counter code 1000, and the word read from the permanent storage device at the address 1000111 is 010101 (the inclusion of phase B, phases A, C are de-energized, reference control bits c ₁ = c ₃ = 1, c ₂ = 0 )

If the device has no malfunctions, then the code x ₃ = x ₆ = 0, x ₅ = 1 appears on the logic outputs of the power amplifiers, and the first or third convolution schemes generate the code of the failure address (syndrome) S ₁ = x ₁ ⊕x ₃ ⊕x ₅ ⊕x ₇ = 1⊕0⊕1⊕0 = 0, S ₂ = x ₂ ⊕x ₃ ⊕x ₆ ⊕x ₇ = 0⊕0⊕0⊕0 = 0, S ₄ = x ₄ ⊕x ₅ ⊕x ₆ ⊕x ₇ = 1⊕1⊕0⊕0 = 0, according to which the indicator will display the number 0, indicating the absence of failures.

Suppose that in phase B there is an open (DT ₂ = 0) or a short circuit in the motor winding (DH ₂ = 0) or a short to ground on the ground circuit b _{2 of a} permanent storage device, i.e. x ₅ = 0, then, in accordance with line 4 of table 1, the counter code is 0010, and the word read from the permanent storage device at 0010111 is 010101, while in the fifth digit (x ₅ ), 0 was replaced due to failure 1.

In this case, the fault address code is defined as S ₁ = x ₁ ⊕x ₃ ⊕x ₅ ⊕x ₇ = 1⊕0⊕0⊕0 = 1, S ₂ = x ₂ ⊕x ₃ ⊕x ₆ ⊕x ₇ = 0⊕ 0⊕0⊕0 = 0, S ₄ = x ₄ ⊕x ₅ ⊕x ₆ ⊕x ₇ = 1⊕0⊕0⊕0 = 1, in accordance with which the indicator will highlight the number 5, indicating the address of the failure. The device responds similarly in case of failures x ₃ ≡1 (rows 7, 8 of table 1), x ₃ ≡0 (rows 7, 8, 12 of table 2), x ₆ ≡1 (rows 13, 14, 15 of table 2), x ₇ ≡0 (rows 6, 7 of table 3), x ₅ ≡1 (rows 10, 11 of table 3).

Information sources

1. Copyright certificate SU 1415401, H02P 7/62, published from 07.08.88. Bull. No. 29.

2. Patent RU 2417512, H02P 8/00, published 04/27/2011. Bull. No. 12.

THREE-START ALTERNATE MODE. MODE CODE a ₅ a ₆ a ₇ = 111

Table 1 Line number Counter Code 1246 Phase Control Code ABCD x ₃ x ₅ x ₆ x ₇ Reference control bits c ₁ c ₂ c ₃
x ₁ x ₂ c ₄ Supervisory and control digits x ₁ x ₂ x ₃ x ₄ x ₅ x ₆ Failure Address Code S ₁ S ₂ S ₄ Note 0 0000 one hundred 110 111,000 000 one 1000 010 101 100110 000 no failures 2 0100 001 011 010101 000 3 1100 one hundred 110 111,000 000 four 0010 010 101 100100 101 failure x ₅ ≡0 5 1010 001 011 010101 000 6 0001 one hundred 110 111,000 000 7 1001 010 101 101110 110 failure x ₃ ≡1 8 0101 001 011 011101 110

Six-step alternate mode. MODE CODE a ₅ a ₆ a ₇ = 011

table 2 Line number Counter Code 1246 Phase Control Code ABCD x ₃ x ₅ x ₆ x ₇ Reference control bits c ₁ c ₂ c ₃
x ₁ x ₂ x ₄ Supervisory and control digits x ₁ x ₂ x ₃ x ₄ x ₅ x ₆ Failure Address Code S ₁ S ₂ S ₄ Note one 0000 one hundred 110 111,000 000 2 1000 110 011 011110 000 3 0100 010 101 100110 000 no failures four 1100 011 110 110011 000 5 0010 001 011 010101 000 6 1010 101 101 101101 000 7 0001 one hundred 110 110000 110 8 1001 110 011 010110 110 9 0101 010 101 100110 000 failure x3≡0 10 1101 011 110 110011 000 eleven 0011 001 011 010101 000 12 1011 101 111 100101 110 13 0000 one hundred 110 111001 011 fourteen 1000 110 011 011111 011 fifteen 0100 010 101 100111 011 failure x6≡1 16 1100 011 110 110011 000 17 0010 001 011 010101 000 eighteen 1010 101 101 101101 000

FOUR STROKE MODE PAIR. MODE CODE a ₅ a ₆ a ₇ = 001

Table 3 Line number Counter Code 1246 Phase Control Code ABCD x ₃ x ₅ x ₆ x ₇ Reference control bits c ₁ c ₂ c ₃
x ₁ x ₂ x ₄ Supervisory and control digits x ₁ x ₂ x ₃ x ₄ x ₅ x ₆ Failure Address Code Note 0 0000 1100 011 0111100 000 one 1000 0110 110 1100110 000 2 0100 0011 one hundred 1000011 000 no failures 3 1100 1001 001 0011001 000 four 0000 1100 011 0111100 000 5 1000 0110 110 1100110 000 failure x ₇ ≡0 6 0100 0011 one hundred 1000010 111 7 1100 1001 001 0011000 111 8 0010 1100 011 0111100 000 9 1010 0110 110 1100110 000 failure x ₅ ≡1 10 0001 0011 one hundred 1000111 101 eleven 1001 1001 001 0011101 101

Claims (1)

A device for controlling a stepper motor comprising a first, second, third bus for selecting a switching mode, a control bus, a clock bus, a reverse bus, a read permission bus, a read-only memory, a reversible counter, the first, second, third inputs of which are connected to the control buses, a clock reverse, respectively, and the outputs the first, second, third, fourth are connected to the inputs of the same name with the same memory, the inputs of which the fifth, sixth, seventh, eighth are connected to the third, second, first, seventh the first, second, third, fourth, fifth, fifth, sixth outputs of the read-only memory device, respectively, characterized in that the first, second, third convolution schemes, an indicator, reference control bit buses, a block are additionally introduced into the device power amplifiers with current and voltage sensors in each phase, while the first, second, third, fourth, fifth, sixth outputs of the permanent storage device are connected to the inputs of the same block of power amplifiers, WTO The first group output of the power amplifier is connected to the phase windings of the stepper motor, and the first group output of the power amplifier is connected to the inputs of convolution circuits, the outputs of which are connected to the indicator inputs.