RU2490696C1 - Error detecting and correcting device with memory self-testing function - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: error detecting and correcting device with a memory self-testing function, which includes second layer cache memory, having four tag memory and data sections, a logic unit for noiseless coding and decoding, is provided with a self-testing unit with a status register, a port for accessing test logic, a unit for generating a test sequence, address and data generators, an operating mode selecting unit, an additional coding unit, having independent encoders, a decoding unit, having independent decoders, a check bit control unit connected to tags of each section for independent and parallel checking of each section of cache memory through the self-testing function, wherein the status register of the self-testing unit is connected to the decoding unit and the port for accessing test logic, and the data generator and address generator are connected to the operating mode selecting unit.

EFFECT: faster operating mode of the memory data transfer channel owing to simultaneous determination of multiple one-fold errors in tags of different sections.

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Description

The invention relates to the field of computer technology, namely to microprocessor systems with cache memory, error detection and correction units, and a built-in self-test unit.

A known memory block self-test scheme containing memory blocks (to be tested), a comparator, a signature register, statistics collection registers, a self-test block control circuit, test sequence generation blocks (Application for invention US No. 2002/0194558 A1, class G06F 17/50 , published on December 19, 2002).

The disadvantage of this scheme is the low speed due to the transfer of test data directly to the inputs of the tested memory unit by multiplexing.

A memory block self-test scheme is also known, where data from the memory block is processed and then written into the signature register, which also reduces the speed of the data transmission channel between the memory and the working logic (Application for invention US 2011/0055646 A1, class G06F 17/50, 03.03.2011).

The disadvantage of this circuit is the low speed and excessive load of the memory outputs due to the use of data for comparison and determination of comparator errors directly at the outputs of the memory blocks. Another disadvantage of the presented scheme is the formation of an error sign by the self-testing unit that is not used in the operating mode.

The closest in technical essence and the achieved result is a device for detecting and correcting errors with the function of self-testing memory including a second level cache containing four sections of tag and data memory, a block of error-correcting encoding and decoding logic (US Patent No. 6,038,693, G06F 11/10, publ. March 14, 2000).

A disadvantage of the described device is the inability to simultaneously detect several single errors in the tags of various sections, leading to low speed of the operating mode of the memory data channel.

The technical result from the use of this invention is to reduce the occupied by the self-testing unit on the chip, the area, the time required for testing, reducing the operating speed of the operating mode of the memory data channel.

The specified technical result is achieved by the fact that the error detection and correction device with a memory self-testing function including a second-level cache memory containing four sections of tag and data memory, a noise-resistant coding and decoding logic block, according to the invention, is equipped with a self-testing block with a status register, an access port to test logic, test sequence generation unit, address and data generators, operation mode selection unit, additional coding unit a unit containing independent encoders, a decoding unit containing independent decoders, a control bit control unit associated with tags of each section, for independently and simultaneously checking each cache section with a self-test function, while the status register of the self-testing unit is connected to the decoding unit and the port access to the test logic, and the data generator and address generator are connected to the mode selection block.

The invention is illustrated in the drawing, which shows a diagram of the sharing of self-testing logic and error-correcting coding modules (ECC).

The device diagram consists of a self-test unit 1, a second-level cache 2, an access port for test logic 3, a unit for generating a test sequence 4, address generators 5, data generator 6, status register 7, an operating mode selection unit 8, tag RAM 9, The RAM of the ECC 10 bits, the coding block 11, the encoders 12, the decoding block 13, the decoders 14, the control bit control block 15.

The operation mode of the circuit is controlled by the unit for generating a test sequence by means of signals: controlling the operating mode 16, controlling the operating mode of the status register 17.

The circuit also contains control buses 18, addresses 19 and tags 20 of the test mode, control buses 21, addresses 22 and tags 23 of the operating mode, input control buses 24, addresses 25, tags 26, input buses of control bits 27, output buses of tags 28, output control bit buses 29, ECC status bus 30.

The device operates as follows. The control logic access port 3 receives control signals, for example, via the JTAG interface. The unit for generating the test sequence 4 goes into test mode, issuing a control signal 16, which turns on the address 5 generators and data 6. At the same time, the control signal 16 extends to the mode selection block 8, switching the cache memory into test mode, disconnecting the tag buses 23 address 22 and control 21 of the operating mode.

The unit for generating the test sequence 4 according to predefined testing algorithms (marching tests, running zero / unit) generates control signals for the memory blocks. Distribution of control signals to the memory blocks is carried out on the control buses 18 and 24. At the same time, one tag memory 9 in each section and the corresponding ECC 10 RAM are turned on.

The address generator 5, controlled by the test sequence generation unit 4, creates a physical address transmitted via the address bus of the test mode 17 to the operation mode selection unit, from where the address extends to all memory blocks of tags 9 of each section and memory blocks of ECC 10 at the input address bus 25.

Received from the data generator 6, the tags through the tag bus of the test mode 20 and the input tag bus 26 are distributed to all RAM blocks of the tags 9 of each section, and to the ECC encoding block 11, which contains encoders 12. The number of encoders corresponds to the number of cache sections in the second level. The control bits calculated by the encoders 12 in the coding unit 11 are transmitted via the input buses of the control bits 27 to the control unit of the control bits 15, in which a line is formed from the control bits of each section. The resulting string is recorded in the corresponding RAM ECC 10, the selection of which is made by the control bus 24.

In test mode, the unit for generating a test sequence 4 for reading and writing to tags memory blocks generates a set of control signals and transmits them via the control bus of the test mode 18 and the input control bus 24. In this case, only one tag memory 9 in each section can be turned on and the corresponding one ECC RAM 10. The tags received from each section on the output buses of the tags 28 are transmitted to the decoding unit 13. The control bits read from the corresponding ECC 10 RAM through the control unit control These 15 are also transmitted to the decoding unit 12. The decoding unit 15 consists of several decoders 14 (one for each section). The statuses of tags obtained as a result of decoding on the ECC 30 status buses are transferred to the status register 7 of the self-testing scheme, where data on the presence of errors in the RAM blocks of tags 9 and the corresponding ECC RAM 10 during the passage of the selected testing algorithms are accumulated. Upon completion of testing, the status of completion is issued from the status register 7 to the port of test logic 3, which determines the operability of each memory block of tags and bits of the ECC cache of the second level.

Claims (1)

An error detection and correction device with a memory self-testing function, including a second-level cache containing four sections of tag and data memory, an error-correcting encoding and decoding logic unit, characterized in that the device is equipped with a self-testing unit with a status register, an access port to test logic, a test sequence generating unit, address and data generators, an operating mode selection unit, an additional coding unit containing independent encoders, a unit decoding, containing independent decoders, control block control bits associated with the tags of each section, for independent and parallel verification of each section of the cache by the self-test function, while the status register of the self-test unit is connected to the decoding unit and the access port to the test logic, and the generator data and the address generator are associated with the block selection mode of operation.