RU2477920C1 - Frequency synthesiser - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: frequency synthesiser includes reference generator (RG) 1, the first and the second phase detectors (PD) 3, 17, divider with variable-division ratio of RG frequency (DVDRR) 2, generator controlled by voltage (GCV) 5, low frequency filter (LFF) 6, divider with variable-division ratio (DVDR) 4, control unit (CU) 7, memory device (MD) 14, controllable constant voltage source (CCVS) 16, the second summing unit 12, starting pulse former (SPF) 18, delay line 15, switching device 11, phase-shifter 13, constant voltage control unit (CVCU) 19.

EFFECT: reduction of transition process duration at frequency setting.

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Description

The proposed device relates to radio communications and can be used in radio receivers and radio transmitting devices for frequency conversion, modulation and generation of radio signals.

To receive, transmit and process signals, frequency synthesizers are used, the main requirements for which are the tuning range, frequency step and speed, as well as the purity of the output oscillation spectrum. A large amount of literature is devoted to the construction and operation of synthesizers, for example [1], [2], [3], [4], [5], [6], [7].

As an analogue of the proposed device can be taken a synthesizer from the literature [3], discussed in Chapter 4 S. 250-254. Radio transmitting devices: Textbook for high schools / V.V. Shahgildyan, V. B. Kozyrev, A. A. Lyakhovkin and others; Ed. V.V.Shahgildyan. - 3rd ed., Revised. and add. - M .: Radio and communications, 2003 .-- 560 p.: Ill.

The authors identified the following modes of synthesizer operation:

1. The hold (capture) mode, in which the synthesizer frequency changes so slowly that the FAP ring manages to track these changes.

2. The synthesizer in the frequency tuning mode. In which at the first stage of tuning in the phase locked loop (PLL) beats occur. A characteristic feature of the beat phase is the continuous increase in the average phase difference between the adjustable and reference generators. The beat stage in the frequency tuning mode is always observed in those cases when the initial detuning of the VCO relative to the reference generator (EG) is larger than the band in the hold mode.

The operation of the synthesizer in the frequency tuning mode is determined by the end of the first stage, i.e. the transition from the beat mode over time to the second stage of the frequency tuning mode - to the hold or quasi-phase matching mode. This happens if the initial detuning does not go beyond the capture band, then the constant component reduces the beat frequency to zero and a retention step occurs. If the initial detuning exceeds the capture band, then the constant component of the voltage is insufficient for its full compensation and the beat phase does not stop in the system.

Thus, the mode of switching the synthesizer to a new frequency occurs through the beat stage and, therefore, takes a long time. The following is an estimate of this time from [4].

The closest in technical essence to the proposed one is the synthesizer presented in [4] on p.271-273, Fig.4.7, adopted as a prototype.

In the prototype synthesizer in the mode of switching to a new frequency, two stages are distinguished: the beat stage and the frequency hold (capture) stage.

The functional diagram of the prototype device, shown in Fig.4.7 of [4], with some refinements is shown in figure 1, where it is indicated:

1 - reference generator (OG);

2 - a divider with a variable frequency division coefficient of the exhaust gas (DPCDO);

3 - phase detector (PD);

4 - divider with a variable division ratio (DPKD);

5 - voltage controlled oscillator (VCO);

6 - low-pass filter (low-pass filter);

7 - control unit;

8 - integrator (I);

9 - large-scale amplifier (MU);

10 - adder (C).

The refinements are as follows: the control of the dividers is carried out by the control unit, the functions of which in [4] are shown in the form of arrows N and M (which means commands for dividing by frequency by the number N or M), the presence of such a block is noted in [2] p.33. In addition, in the functional diagram (figure 1) the low-pass filter 6 is specified, which is presented in the form of an integrating filter consisting of an integrator 8, a scale amplifier 9 and an adder 10, the possibility of such a presentation is described, for example, in [7] p.15, [ 4] p. 277, [8] and others.

The prototype device contains serially connected exhaust gas 1, a DPKDO 2 divider and PD 3, the output of which is connected to the input of the low-pass filter 6, the output of which is connected to the input of the VCO 5, the output of which is the output of the synthesizer, and also through the DPKD 4 divider is connected to the second input of the PD 3. In addition, the first output of the control unit 7 is connected to the control input of the DPKDO 2, and the second output of the control unit 7 is connected to the control input of the DPKDO 4.

When describing the work, in some cases, for simplicity, we will consider the low-pass filter 6 without revealing its structure, however, we assume that the low-pass filter 6 is implemented only in the form of a block consisting of an integrator 8 and a scale amplifier 9, the inputs of which are connected and the outputs are connected to the input of the adder 10, the output of which is the output of the low-pass filter 6.

The prototype synthesizer works as follows.

The output voltage of the exhaust gas 1 is fed to the input of the DPKDO 2 divider, the division coefficient of which is set in accordance with the command from the first output of the control unit 7, which is fed to the control input of the DPKDO 2, the output voltage of which is supplied to the first input of the phase detector 3, to the second input of which the output the voltage of the DPKD 4, to the input of which the harmonic voltage of the VCO is supplied 5. The division coefficient of the DPKD 4 is set in accordance with the command supplied to its control input from the second output of the control unit 7, and you odnoe voltage phase detector 3 via the PD 6 is fed to the control input of the VCO 5. The synthesizer operation two modes can be distinguished: the first one - frequency locking and a second mode - adjustment mode to the new frequency.

In the first mode, i.e. when the frequency and phase coincide of the voltage of DPKDO 2 and voltage of DPKD 4 at the first and second inputs of the phase detector 3, its output voltage is zero, and the voltage that controls the frequency of the VCO 5 at the output of the low-pass filter 6 maintains the frequency of the VCO 5, which ensures equality to zero the output voltage of the phase detector 3. If the voltage phase at the output of DPCDO 2 changes slowly, the signal that appears at the output of the phase detector 3, and therefore the output of the low-pass filter 6, connected to the control input of the VCO 5 changes its frequency and phase in such a way, h then the difference in frequency and phase of the voltage DPKDO 2 and voltage DPKD 4 at the first and second inputs of the phase detector 3 becomes equal to zero, and its output voltage also takes a zero value.

In the second mode - synthesizer frequency tuning - the operation of the FAP ring is different. According to [4], the synthesizer frequency tuning takes place in two stages: the first beat stage and the second - phase adjustment within the linearity of the phase detector characteristics.

In accordance with [4] p.277, to switch to another operating frequency, the DPKD division coefficient 4 is switched by a command from the second output of the control circuit 7 and the DPKDO division coefficient 2 by a command from the first output of the control circuit 7. In this case, the voltage at the phase inputs detector 3 do not coincide in frequency and phase, and at its output the signal is different from zero.

As a result, in the PLL auto-control ring: PD 3, LPF 6, VCO 5, DPKD 4 blocks, a transition process occurs. The transition process, as noted above, has two stages. On the first of them (with a duration of τ _lane ), the frequency of the adjustable oscillator approaches the frequency of the reference oscillator, and the phase difference varies by several periods. Beating Stage.

At the second stage of the transition process, the phase difference varies within the "section of the PD characteristic with a positive slope, and then its constant phase value is set" [4]. In accordance with [4] "The value of τ _per is usually 30 ... 50 periods of the frequency of comparison" [4].

The time of the second stage is much shorter and is not taken into account by the author.

So, the prototype synthesizer has a long transition period, i.e. It does not work effectively in the mode of tuning the synthesizer to a different frequency.

The objective is to reduce the duration of the transient process when establishing the frequency of the synthesizer.

To solve the problem, a frequency synthesizer containing a series-connected reference oscillator (OG), a divider with a variable frequency division coefficient of an exhaust gas (DPKDO) and a first phase detector (PD), a series-connected voltage-controlled oscillator (VCO) and a divider with a variable division ratio (DPKD), and the VCO output is the output of the device, as well as a low-pass filter (LPF) and a control unit (BU), the first and second outputs of which are connected to the second inputs of the DPKDO and DPKD, respectively, according to the image eniyu, administered serially connected second PD, a storage device (memory) and the phase shifter, the output of which is connected to a second input of the first PD; connected in series with a constant voltage control unit (DCLF) and a controlled constant voltage source (DCLI), the output of which is connected to the second input of the second adder, the output of which is connected to the VCO input, in addition, a start pulse shaper (FSI) and a delay line (LZ) ), the output of which is connected to the second inputs of the memory and the switch, the third input of which is connected to the output of the FSI, while the second output of the control unit is connected to the inputs of the BUPN and the FSI, the low-pass filter is connected between the output of the switch ora and the first input of the second adder besides DPKD output connected to second inputs of the phase shifter and the second PD.

Functional diagram of the proposed device is presented in figure 2, where it is indicated:

1 - reference generator (OG);

2 - a divider with a variable frequency division coefficient of the exhaust gas (DPCDO);

3, 17 - the first and second phase detectors (PD);

4 - divider with a variable division ratio (DPKD);

5 - voltage controlled oscillator (VCO);

6 - low-pass filter (low-pass filter);

7 - control unit (BU);

8 - integrator (I);

9 - large-scale amplifier (MU);

10, 12 - the first and second adders;

11 - switch;

13 - phase shifter (FVR);

14 - storage device (memory);

15 - delay line (LZ);

16 - controlled constant voltage source (IUPN);

18 - shaper start pulse (FSI);

19 - constant voltage control unit (BEL).

The proposed frequency synthesizer contains a series-connected exhaust gas 1, DPKDO 2, the first PD 3, switch 11, low-pass filter 6, the second adder 12 and VCO 5, the output of which is the output of the device. In addition, connected in series to the second PD 17, memory 14 and FVR 13, the output of which is connected to the second input of the first PD 3; serially connected BUPN 19 and IUPN 16, the output of which is connected to the second input of the second adder 12; sequentially connected FSI 18 and a delay line 15, the output of which is connected to the second inputs of the switch 11, and the memory 14, and the output of the FSI 18 is connected to the third input of the switch 11. The first output of the control unit 7 is connected to the control input DPKDO 2, the second output of the control unit 7 connected to the inputs of the FSI 18, BUPN 19 and the second (control) input of the DPKD 4, the output of which is connected to the second input of the phase shifter 13 and to the second input of the second PD 17, the first input of which is connected to the output of the DPKDO 2. The output of the VCO 5 is connected to the input DPKD 4. LPF 6 performed n similar to that given in the description of the prototype.

In the proposed synthesizer, as well as the prototype synthesizer, the work in the first mode - hold (capture) is not fundamentally different. Work in the second mode - transients in the FAP ring occur differently.

To clarify the physics of transients in the FAP ring, we use the results of [8]. In [8], the time dependences of the phase establishment (transients) in the frequency synthesizer were determined. Note that in [8], the solutions were obtained by idealizing the characteristics of a phase detector, i.e. in the absence of linearity limitations of the phase detector by any segment, for example (-π, π). It will be shown below that the issue of this idealization of the PD characteristics is methodological in nature and does not affect the operation of the proposed device.

Since the purpose of [8] is to determine the transient process of the FAP ring, the synthesizer functional diagram is simplified (there are no DPKD and DPKDO blocks, we can consider DPKD included in the VCO, and the exhaust gas and DPKDO form the source of the reference signal (OS), respectively, and the solution was found in the form of voltage changes at the input of the phase detector.

The functional diagram of the synthesizer according to [8] is shown in figure 3, where it is indicated:

1 - reference signal source (OS);

5 - voltage controlled oscillator (VCO);

3 - phase detector (PD);

6 - integrating filter; ??

9 - large-scale amplifier (MU);

8 - integrator (I);

10 - adder.

According to [8], the transition process is determined, firstly, by the parameters of the FAP ring, and, secondly, by the initial conditions.

FAP ring parameters include:

1. The frequency of natural oscillations ω ₀ = (k _VCO k _AND k _PD ) ^1/2 ,

where k _VCO , k _И , k _ФД are the transmission coefficients of the VCO, integrator, and phase detector, respectively.

2. The ring attenuation time constant τ ₀ = l / (k _VCO k ₁ k _PD ), where k ₁ is the transfer coefficient of the scale amplifier.

3. The attenuation decrement d = k ₁ (k _VCO k _PD / k _I ) ^1/2 .

The initial conditions include the phases and frequencies of the signals acting on the PLL ring of voltages, namely:

1. The initial phase difference φ (0) between the harmonic signals at the inputs of the PD.

2. Normalized initial frequency difference of the same signals (specifically normalized frequency difference b).

For convenience, the results were normalized in [8] and the following notation was introduced.

Normalized time τ = ω ₀ t; normalized frequency difference (phase angle) between the harmonic signals at the PD inputs b = g / ω ₀ , g is the initial deviation of the frequency of the harmonic voltage at the output of the VCO from the frequency of the harmonic voltage of the OS.

First, we give an example from [8] - a transition process in which at the initial moment only the constant component of the phase of the reference oscillation φ of the _{exhaust gas} changes (0). (More precisely, we mean the change in the phase difference at the inputs of PD 3, but for brevity, we retain the previous formulation).

Three curves for the establishment of the phase φ (τ) at the output of the VCO are shown in Fig. 4 with a jump in the phase φ of the _{exhaust gas} (0) of the reference oscillation by 1, 0.2, and 1.5 radians, respectively.

It is easy to see from Fig. 4 that the dependence of the phase difference at the PD 3 inputs on τ consists of two terms - the forced component (constant value), in this case 1, 0.2, and 1.5, and the second term - free oscillation: damped cosine waves. The maximum amplitude of the phase oscillation is equal in magnitude and opposite in sign to the constant value φ _ОГ (0).

The maximum phase deviation, as can be seen from figure 4, is a value close to 2 φ _OG (0). In the cases considered in FIG. 4, the change in the phase φ of the _{exhaust gas} (τ) does not go beyond the linearity of the PD of the prototype device [4], i.e. does not exceed ± π, however, at φ _ОГ (0) greater than 2, the amplitude of the phase change should exceed the region ± π. This fact will lead to a transition to the beat mode. Importantly, when _{the exhaust gas} φ (0) ≤π _exhaust phase φ (τ) is within the linear portion of the PD equal to ± π. It should be noted that the time of the transition process does not depend on the value of φ _ОГ (0). However, the absolute magnitude of the phase changes is linearly associated with φ _ОГ (0). Thus, with φ _ОГ (0) = 0.5, the magnitude of the phase deviations does not exceed 1 (see Fig. 4). At other values of φ _ОГ (0), this property is preserved, for example, with φ _ОГ (0) = 0.1, the magnitude of the phase deviations does not exceed 0.2. In practice, a phase deviation of 0.2 (11 °) can be neglected. However, it should be borne in mind that this is the phase deviation at the input of the phase detector of the FAP ring, and the phase deviation at the output of the VCO in the synthesizers corresponding to the functional diagram of Fig. 2 will be larger in the division coefficient of the DPKD, which must be taken into account.

Consider the second case - at the initial moment, only the frequency b at the output of the exhaust gas 1 changes. As in the previous case, the solution consists of forced and free components. So, the phase change at the output of the VCO can be represented as the sum φ (τ) = η (τ) + bτ, where bτ characterizes the increase in the frequency of the VCO by b, and the phase η (τ) is a transition process, i.e. difference between φ (τ) and bτ.

According to [8], the dependences η (τ), η1 (τ), η2 (τ), for b = 1, b = -1 and b = 0.2, respectively, have the form shown in Fig. 5. The curves η (τ), η1 (τ), η2 (τ) have the form of a damped sinusoid with a frequency ω ₀ , and the maximum amplitude of the phase oscillation does not exceed b.

Note that in the cases considered in FIG. 5, the phase change η (τ) does not go beyond the linearity of the PD of the prototype device [4], i.e. beyond ± π. However, for b greater than π, the amplitude of the phase change should leave the region ± π. This fact will lead to a transition to the beat mode.

With a simultaneous change in φ of the _{exhaust gas} (0) and b according to [8], the phase change is equal to the sum of the damped harmonic oscillations φ (τ) and η (τ) from φ the _{exhaust gas} (0) and b, respectively. Therefore, the maximum amplitude of the phase deviation will be | 2φ _OG (0) + b |. Thus, at | 2φ _OG (0) + b | ≤π, transients will be in the zone of linearity of the PD, in this case the beat stage is excluded. Note that the limits of linearity are chosen ± π, according to the data of [4], changing them to another value is unprincipled.

Thus, to reduce the time of establishing the frequency, it is required to work in a mode with small values of φ _ОГ (0) and b, this is what the proposed device provides.

Consider the operation of the proposed device.

Work in the first mode - capture, fundamentally no different from the work of the prototype.

The exhaust gas exhaust voltage 1 is supplied to the first input of DPKDO 2, in which its frequency is divided by the number of times specified by the command from the control unit 7, the output voltage of exhaust gas 2 is fed to the first inputs of phase detectors 3 and 17, the second of which is connected to the output voltage from DPKD 4, formed from the voltage of the VCO 5 by dividing this voltage by frequency in the number of times specified by the command from the control unit 7, and the voltage of the DPKD 4 is supplied directly to the second input of the PD 17, and the voltage of the DPKD 4 is supplied to the second input of the PD 3 through the phase shifter 13, The phase value is set in accordance with the memory command 14. The output voltage of the PD 3 through the switched on switch 11 is supplied to the input of the low-pass filter 6 and is integrated (filtered) in it, and then summed in the adder 12 with a constant voltage of the source 16 and connected to the input of the VCO 5. Block control 7, the command to change the division coefficient of the block DPKD 4 does not issue, and therefore there is no command to the shaper 18, which in turn does not generate commands to start the search, for this reason LZ 15 does not generate a command to change the status of the memory 14 and comm Tator 11. The switch 11 connects the output of the PD 3 to the input of the low-pass filter 6. Blocks 19, 16 and 12 do not change their state.

Thus, the FAP ring is closed and keeps at the input of PD 3 the phase difference between the output voltages of DPKDO 2 and DPKD 4 equal to zero, while the voltage at the output of PD 3 is also zero, and the frequency of the output voltage of VCO 5 is equal to the frequency of the output voltage at the output of VCO 5 multiplied by the division coefficient of the DPKD 4.

In the second mode, the synthesizer frequency tuning mode, the control unit 7 issues a command to change the division coefficient of DPKDO 2 and issues a command to generate a start pulse by block 18 to change the division coefficient of the DPKD 4, to generate a command to change the output voltage of IUPN 16 in BUPN 19. The start pulse from block 18 starts the delay line 15, disconnects the switch 11 from the output of the PD 3 and connects the input of the low-pass filter 6 to the "ground".

Under these conditions, work in the second mode (tuning the synthesizer frequency) occurs as follows.

The exhaust gas exhaust voltage 1 is supplied to the input of DPKDO 2, in which its frequency is divided by the number of times specified by the command from the control unit 7, the output voltage of DPKDO 2 is supplied to the first inputs of the phase detectors PD 3 and PD 17, to the second inputs of which the output voltage from DPKD is connected 4, formed from the voltage of the VCO 5, by dividing this voltage by frequency in the number of times specified by the command from the control unit 7, and the input voltage of the DPD 4 is supplied directly to the second input of the PD 17, and to the second input of the PD 3 through the phase shifter 13. The command with fo tors, the start pulse 18, the switch 11 disconnects from the PD 3 and the LPF 6 connects the LPF input 6 at "earth". The output voltage of the PD 17 changes in accordance with the phase difference between the voltages at the first and second inputs, this voltage is recorded in the memory 14 when a time equal to the delay passes, the delay line 15 generates a pulse that captures the voltage at the output of the memory 14, in accordance with this voltage phase shifter 13 changes the phase of the output signal DPKD 4, so that the phase difference of the voltage DPKDO 2 and phase shifter 13 will be close to zero. By the same command from the memory 14, the switch 11 disconnects the input of the low-pass filter 6 from the ground and connects it to the output of the PD 3, thus, the phase-locked loop closes and the transition process begins, as a result of which the proposed device switches to synchronization mode. Since the initial conditions for the transition process: the phase is close to zero, and the difference in frequency, normalized frequency b, is less than 1, then with a linear phase characteristic of the PD ± π, the beat mode is impossible and a short time to transition to a stable state is ensured. Thus, the proposed device works efficiently.

Information sources

1. Radio transmitting devices. Shakhgildyan V.V., Kozyrev V.B., Lyakhovkin A.A. et al. Ed. V.V.Shahgildyan. - 2nd ed., Revised. and add. - M .: Radio and communications, 1990. - 432 p.: Ill.

2. Manassevich V. Frequency synthesizers (Theory and design): Per. from English / Ed. Galina. M .: Communication, 1979.- 384 p. silt.

3. Radio transmitting devices: Textbook for high schools / VV Shahgildyan, VB Kozyrev, A. A. Lyakhovkin and others; Ed. V.V.Shahgildyan. - 3rd ed., Revised. and add. - M .: Radio and communications, 2003 .-- 560 p.: Ill.

4. Generation of oscillations and the formation of radio signals. Ed. V.N. Kuleshov and N.N. Udaltsova. - M .: Publishing house MPEI. 2008 .-- 416 pp., Ill.

5. Tikhomirov N.M., Romanov S.K., Lenshin A.V. Generation of FM signals in synthesizers with automatic tuning. - M .: Radio and communications, 2004 .-- 210 p .: ill.

6. Phase synchronization systems / Akimov VN, Belyustina LN, Belykh VN and etc.; Ed. V.V. Shahgildyan, L.N. Belyustina - M .: Radio and communications, 1982 - 288 p., Ill.

7. Kapranov M.V. Elements of the theory of phase synchronization systems. - M.: Publishing House MPEI, 2006. - 208 p.

8. Bokk O.F. Properties of an idealized phase-locked loop. Theory and technique of radio communication: scientific. - tech. Journal / Concern Constellation OJSC. - Voronezh, 2011. - No. 1. - S. 109-116.

Claims (1)

A frequency synthesizer comprising a series-connected reference oscillator (OG), a divider with a variable frequency division coefficient of the exhaust gas (DPKDO) and the first phase detector (PD), a voltage-controlled oscillator (VCO) and a variable frequency division divider (DPKD) in series, and the VCO output is the output of the device, as well as a low-pass filter (LPF) and a control unit (BU), the first and second outputs of which are connected to the second inputs of DPKDO and DPKD, respectively, characterized in that they are connected in series with Inonii second PD, a storage device (memory) and the phase shifter, the output of which is connected to a second input of the first PD; connected in series with a constant voltage control unit (DCVN) and a controlled constant voltage source (IITN), the output of which is connected to the second input of the second adder, the output of which is connected to the VCO input, in addition, the start pulse shaper (FSI) and the delay line (LZ) are connected in series ), the output of which is connected to the second inputs of the memory and the switch, the third input of which is connected to the output of the FSI, while the second output of the control unit is connected to the inputs of the BUPN and the FSI, the low-pass filter is connected between the output of the switch ora and the first input of the second adder besides DPKD output connected to second inputs of the phase shifter FD and the second, the output voltage DPKDO supplied to the first input of the second phase detector.

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