RU2474838C1 - Electronic device for rapid recovery of pseudorange measurements - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: device consists of first and second registers with a reset function, first, second, third, fourth, fifth and sixth registers, an inverter, first, second, third and fourth adders, a multiplier, a prediction module, a correction module and a memory update module. The prediction module consists of one register, first, second and third inverters, first, second, third and fourth multipliers, first, second, third and fourth adders and a module for calculating -1 degree. The correction module consists of first, second and third adders, an inverter, an adder, a module for dividing by 4, a module for calculating the remainder of division, first and second comparators, first, second, third and fourth conjunction elements, a disjunction element and a negation element. The memory update unit consists of a register, an inverter, first and second adders, first, second, third and fourth comparators, first, second and third conjunction elements, a disjunction element and a negation element.

EFFECT: designing navigation receivers with a function for rapid recovery of pseudorange measurements, thus achieving low power consumption and increasing speed of navigation receivers of GLONASS systems.

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Description

The invention relates to the field of creating portable navigation receivers, as well as means for autonomous monitoring of navigation signals of GLONASS / GPS satellite systems.

It is known that measurements made by a navigation receiver are a phase shift (measured pseudorange) of a pseudo-random bit sequence (PSP), we denote it by Δφ, and to solve a navigation problem, it is necessary to obtain a value characterizing the true distance from the receiver to the navigation device accurate to the shift value time scales of the receiver relative to the time scale of the apparatus. This value is called pseudorange and is determined by the formula:

Where:

- R - range of measurement unambiguity;

- K is a natural number such that 0≤L-L '<R, where

- L 'is the true range from the navigation satellite to the receiver at the time of measurement.

The measurement uniqueness range is determined by the length of the SRP period. The problem of determining L 'is called the problem of restoring pseudorange measurements. There are two possible ways to solve this problem:

- determination of K each time a new measurement is received;

- a single determination of K (at the beginning of reception) and further continuous monitoring of Δφ measurements in order to clarify K.

The first method today is a standard approach and is implemented in many GPS / GLONASS navigation receivers, for example, in navigation receivers produced by the Navis Design Bureau. This method is characterized by a simpler implementation, however, when processing a measurement stream at a high rate, it requires significant computational resources and, accordingly, high energy costs.

The second method can significantly reduce the need for computing resources of the navigation receiver, however, for reliable operation of this method it is necessary that there are relatively few losses in the measurement stream.

In the claimed electronic device for the operational recovery of pseudorange measurements, a second approach is implemented.

The method and system that has many Global Navigational Satellite System GNSS satellites and a slew system are known (see US patent for invention US 7,911,378, publ. 19.12.2008), the method includes the steps of acquiring the source code for measuring the pseudorange and the initial measurement of the passable phase from a signal transmitted from a GNSS satellite to the GNSS system, obtaining a correction code from a rise system, using a correction code to edit the source code for measuring the pseudorange and the initial measurement of the passable phase to reduce errors in the signal e, to result in a corrected pseudorange measurement code and an adjusted measurement of the passable phase and the use of the dominant measurement code in the filter, which produces an apposition and uncertainty estimate.

The disadvantage of the invention is that the restoration of pseudorange measurements is carried out programmatically, and this requires large energy costs and large computing power.

The technical result of the claimed invention is:

- restoration of pseudorange measurements with signal losses up to several tens of minutes, sequentially generated by the measuring channel of the navigation receiver, in real time;

- reducing the dimensions (area, size) of the device due to the reduction in the number of functional elements, which makes it possible to use it as part of modern navigation receivers of GLONASS / GPS systems;

- reduction of energy consumption;

- increase the pace of processing the measurement stream;

- improving the performance of navigation receivers due to the effective hardware solution of the problem of restoring pseudorange measurements.

The technical result is achieved by the fact that the electronic device for the operational recovery of pseudorange measurements consists of a first and second register with a reset function, first, second, third, fourth, fifth and sixth registers, one inverter, first, second, third and fourth adder, one multiplier, a forecast module, a correction module, and a memory update module, wherein the output of the first register from the reset functions is connected to the second input of the forecast module and to the first input of the second register with the reset function, output One of the second register with the reset function is connected to the fourth input of the forecast module, the output of the fourth register is connected to the seventh input of the forecast module, the output of the first register is the input of the second register, the output of which is connected to the inverter, the output of the inverter is connected to the second input of the first adder, the output of the first register is connected with the first input of the first adder and the third input of the forecast module, the output of the first adder is connected to the fifth input of the forecast module, the output of the third register is connected to the sixth input of the forecast module, p the first output of the forecast module is connected to the first input of the second adder, and the second and third output of the forecast module are connected to the second and third inputs of the correction module, respectively, the first input of the correction module is connected to the second input of the electronic device, the output of the third register is connected to the fourth input of the correction module, output the correction module is connected to the second input of the second adder, the outputs of the first and second registers with the reset function are connected to the first and second inputs of the memory update module, respectively, the output is tre the fifth adder is connected to the third input of the memory upgrade module, the output of the fifth register is connected to the fourth input of the memory upgrade module, the first output of the memory upgrade module is connected to the second inputs of the first and second registers with a reset function, and the second output of the memory upgrade module is connected to the first input of the first register with a reset function and is the output of an electronic device, the output of the second adder is connected to the input of the fourth register and with the first input of the fourth adder, the output of the sixth register is second the input of the fourth adder, the output of which, in turn, is connected to the second input of the multiplier, the first input of which is the output of the third register, the output of the multiplier is connected to the second input of the third adder, the first input of which is the second input of the electronic device, the first input of the electronic device is connected to the first input of the forecast module and the inputs of the first register, while the forecast module is designed to calculate the pseudorange measurement predicted for the next measure, the correction module is intended to the correction value K during long signal losses, where K - a positive number which is determined once at the beginning of the reception, memory refresh module is intended to control the reliability of received pseudorange measurements. The forecast module consists of one register, the first, second and third inverters, the first, second, third and fourth multipliers, the first, second, third and fourth adders, the -1 degree calculation module, with the first input of the forecast module connected to the first input of the second adder , the second input of which is the output of the second inverter, the second input of the forecast module is connected to the second input of the third adder and the first input of the first adder, the second input of which is the output of the first inverter, the third input of the prog connected to the input of the second inverter, the fourth input of the forecast module is connected to the input of the first inverter, the fifth input of the forecast module is connected to the -1 degree calculation module, the sixth input of the forecast module is connected to the second input of the third multiplier, the first input of which is the seventh input of the forecast module, output the first adder is connected to the first input of the first multiplier, the second input of which is the output of the -1 degree calculation module, the output of the first multiplier is the second output of the forecast module and the first input of the second a knife, the second input of which is the output of the second adder, the output of the second multiplier is connected to the first input of the third adder, the output of the third multiplier is connected to the input of the third inverter, the output of which is connected to the second input of the fourth adder, the first input of which is the output of the third adder, the output of the fourth adder is the third output of the forecast module and the first input of the fourth multiplier, the second input of which is the output of the register, the output of the fourth multiplier is the first output of the module Projections. The correction module consists of the first, second and third register, one inverter, one adder, one dividing by 4 module, one module for calculating the remainder of the division, the first and second comparator, the first, second, third and fourth elements of the conjunction, one disjunction element and one element of negation, while the first input of the correction module is connected to the inverter, the second input of the correction module is connected to the second input of the second comparator, the third input of the correction module is connected to the first input of the residue calculation module from division, the fourth input of the correction module is connected to the second input of the module for calculating the remainder of the division and with the input of the module for dividing by 4, the output of the first inverter and the output of the module for calculating the remainder of division are connected to the first and second inputs of the adder, respectively, the output of the division module by 4 is connected to the second the input of the first comparator, the first input of which is the output of the adder, the output of the first register is connected to the first input of the second comparator, the output of the first comparator is the first inputs for the first and second elements conjunction, the second input of the first conjunction element is the output of the second comparator, and the second input of the second conjunction element is the output of the negation element, the input of which is the output of the second comparator, the output of the first conjunction element is connected to the second input of the third conjunction element, the first input of which is the output of the second register, the output of the second conjunction element is connected to the second input of the fourth conjunction element, the first input of which is the output of the third register, the outputs of the third and even of the conjunction elements are the first and second inputs of the disjunction element, respectively, the output of which is the output of the correction module. The memory update module consists of one register, one inverter, the first and second adder, the first, second, third and fourth comparator, the first, second and third conjunction elements, one disjunction element and one negation element, while the first input of the memory update module is connected to the first input of the first comparator, the second input of the memory update module is connected to the first input of the second comparator, the third input of the memory update module is the first inputs for the second and third elements of the conjunction, the third and fourth comparators, the fourth input of the memory update module is connected to the inverter input and the second input of the first adder, the second inputs for the first and second comparators are the register output, the outputs of the first and second comparators are connected to the first and second inputs of the first conjunction element, respectively, the output of which is connected with the second input of the second conjunction element, in turn, the output of which is the first inputs for the first and second adder, the inverter output is connected to the second input of the second about the adder, the output of the first adder is connected to the second input of the third comparator, and the output of the second adder is connected to the second input of the fourth comparator, the outputs of the third and fourth comparator are connected to the first and second inputs of the disjunction element, respectively, the output of the disjunction element is the first output of the memory update module and the input the negation element, the output of which is the second input of the third conjunct element, the output of the third conjunct element is the second output of the memory update module.

The essence and features of the claimed invention are further illustrated by the drawings, which show the following:

Figure 1 - presents a structural diagram of an electronic device for the operational recovery of pseudorange measurements, where:

1 - first register with reset function;

2 - second register with reset function;

3 - first register;

4 - second register;

5 - the first adder;

6 - inverter;

7 - third register;

8 - the fourth register;

9 - the second adder;

10 - the third adder;

11 - multiplier;

12 - fourth adder;

13 - fifth register;

14 - sixth register.

Figure 2 - presents a structural diagram of a forecast module of an electronic device for the operational recovery of pseudorange measurements, where:

15 - the first adder;

16 - the first inverter;

17 - module calculating -1 degree;

18 - the first multiplier;

19 - the second multiplier;

20 - second adder;

21 - second inverter;

22 - the third adder;

23 - fourth adder;

24 - the third inverter;

25 - the third multiplier;

26 - the fourth multiplier;

27 is a register.

Figure 3 - presents a structural diagram of a correction module of an electronic device for the operational recovery of pseudorange measurements, where:

28 - inverter;

29 - adder;

30 - the first register;

31 - the first comparator;

32 - the second comparator;

33 - module for calculating the remainder of the division;

34 - an element of negation;

35 - the first element of the conjunction;

36 - the second element of the conjunction;

37 - module dividing by 4;

38 - the second register;

39 - third register;

40 - the third element of the conjunction;

41 - the fourth element of the conjunction;

42 is an element of disjunction.

Figure 4 - presents a structural diagram of a memory update module of an electronic device for the operational recovery of pseudorange measurements, where:

43 - register;

44 - the first comparator;

45 - the second comparator;

46 - the first element of the conjunction;

47 - the second element of the conjunction;

48 - the first adder;

49 - second adder;

50 - inverter;

51 - third comparator;

52 - the fourth comparator;

53 - element of disjunction;

54 - an element of negation;

55 is the third element of the conjunction.

The principle of operation of the claimed invention is as follows.

Let Δφ _i-1 , Δφ _i , Δφ _{i + 1} denote the phase shift measurements of the SRP corresponding to the time t _i-1 , t _i , t _{i + 1} . We also assume that at times t _i-1 , t _i , t _{i + 1} , the quantities K _i-1 and K _{i are} known. It is assumed that t _i -t _i-1 = 1, K _i = K _i-1 , t _{i + 1} = t _i +1. A unit is a time interval between consecutive pseudorange measurements. In this case, for the quantity K _{i + 1, the} following relations hold:

The operation of the device is based on tracking changes in Δφ _i in order to determine the change in K _i . In other words, remembering Δφ _i-1 , Δφ _i and the corresponding time points, the device determines the predicted phase shift Δφ at time t _{i + 1} and, comparing it with the range of measurement unambiguity, determines the value of K _{i + 1} .

The electronic device for the operational recovery of pseudorange measurements (see Fig. 1) consists of a first (pos. 1) and a second (pos. 2) register with a reset function, the first (pos. 3), the second (pos. 4), and the third (pos. .7), the fourth (pos. 8), fifth (pos. 13) and sixth (pos. 14) registers, one inverter (pos. 6), the first (pos. 5), the second (pos. 9), and the third ( pos. 10) and the fourth (pos. 12) adder, one multiplier (pos. 11), a prediction module, a correction module, and a memory update module. At the first input, the measurement of pseudorange from the receiver at time t _i is applied, and the time t _i itself is fed to the second input. At the output of the circuit, a reconstructed measurement of the pseudorange at the same time moment, i.e. the circuit works almost without delay.

The inverter (pos. 6) multiplies the input signal by -1.

The registers (pos. 1, 2) have a reset function: if a signal arrives at the second input, then the value 0 is placed in the register. These registers store the current values of the measurement and receiver time.

The registers (items 3, 4) store the previous measurement and time values.

The value R is stored in the register (pos. 7) - the value of the range of measurement uniqueness.

The register (pos. 8) stores the total value of K.

The register (pos. 13) stores the value of the measurement confidence range.

The register (pos. 14) stores the initial value K.

Adders (pos. 5, 9, 10 and 12) output the value of the sum of all their inputs.

The multiplier (pos. 11) calculates the value of the product of all its inputs and issues it to the output.

The forecast module calculates the pseudo-range measurement predicted for the next measure. The first input time fed prediction module t _i, a second input supplied pseudorange measurement at a time t _i-1, the third input is a time t _i-1, the fourth input receives pseudorange measurement at time t _i-2, the fifth the input is supplied with the value Δt = t _i -t _i-2 , calculated directly in the electronic circuit of the operational recovery of pseudorange measurements, the sixth input is fed with the value of the measurement unambiguity range and the seventh input is fed with the total value K. The forecast module (see Fig. 2) consists of from one regis RA (pos. 27), the first (pos. 16), the second (pos. 21) and the third (pos. 24) inverter, the first (pos. 18), the second (pos. 19), the third (pos. 25) and the fourth (pos. 26) multiplier, the first (pos. 15), the second (pos. 20), the third (pos. 22) and the fourth (pos. 23) adder and the -1-degree calculation module (pos. 17).

The calculation module -1 degree (pos.17) raises the input signal -1 degree.

Inverters (pos. 16, 21 and 24) multiply the input signal by -1.

Adders (pos. 15, 20, 22 and 23) calculate the sum value of all their inputs and give it to the output.

Multipliers (pos. 18, 19, 25 and 26) calculate the value of the product of all their inputs and give it to the output.

The register (pos. 27) stores the value of 1 / R, where R is the range of measurement uniqueness.

At the first output of the forecast module, the value K is output for the current clock cycle, the second derivative is given the value of the first derivative of the pseudorange measurement function with respect to time at the current moment, and the predicted pseudorange value at the current moment is output to the third output.

The correction module corrects the value of K with prolonged signal loss. The pseudorange value from the receiver at the current moment is fed to the first input of the correction module, the value of the first derivative of the pseudorange measurement function in time at the current moment is fed to the second input, the predicted pseudorange value at the current moment is fed to the third input, and the value of the unambiguity range of the pseudorange measurements . The correction module (see Fig. 3) consists of the first (pos. 30), second (pos. 38) and third (pos. 39) registers, one inverter (pos. 28), one adder (pos. 29), one dividing by 4 (pos. 37), one module for calculating the remainder of dividing (pos. 33), the first (pos. 31) and second (pos. 32) comparator, the first (pos. 35), and the second (pos. 36) , the third (pos. 40) and the fourth (pos. 41) element of conjunction, one element of disjunction (pos. 42) and one element of negation (pos. 34).

Registers (pos. 30, 38 and 39) store values of 0.1 and -1, respectively.

The dividing by 4 module (pos. 37) divides the input signal by 4.

The module for calculating the remainder of the division (key 33) calculates and outputs the remainder of the division of the signal supplied to the first input to the signal supplied to the second input.

Comparators (pos. 31 and 32) compare two values that came to their inputs and give 0 or 1 depending on the truth of the inequality.

At the output, the correction module issues a correction value K to a receiving value of 1, -1, or 0.

The memory update module monitors the accuracy of pseudorange measurements received at the input and, in case of false pseudorange measurements, resets the shift registers. The first and second inputs of the memory update module provide measured pseudorange values at time t _i-1 and t _i-2, respectively, the restored pseudorange value at the current moment is fed to the third input, the value of the validity range of the pseudorange measurements is fed to the fourth input. The memory update module (see Fig. 4) consists of one register (pos. 43), one inverter (pos. 50), the first (pos. 48) and the second (pos. 49) adder, the first (pos. 4), the second (pos. 45), the third (pos. 51) and the fourth (pos. 52) comparator, the first (pos. 46), the second (pos. 47) and the third (pos. 55) element of the conjunction, one disjunction element (pos. .53) and one element of negation (key 54).

The register (pos. 43) stores the value 0.

A reset signal that takes the values 1 or 0 is issued to the first output of the memory update module, and the adjusted pseudo-range value restored to is returned to the second output.

Thus, the claimed electronic device allows in real time to restore pseudorange measurements sequentially generated by the measuring channel of the navigation receiver. Moreover, the developed scheme has a small area, which makes it possible to use it as part of modern navigation receivers of GLONASS / GPS systems.

Claims (4)

1. An electronic device for the operational recovery of pseudorange measurements, consisting of first and second registers with a reset function, first, second, third, fourth, fifth and sixth registers, one inverter, first, second, third and fourth adders, one multiplier, prediction module, a correction module and a memory update module, wherein the output of the first register from the reset functions is connected to the second input of the forecast module and to the first input of the second register with the reset function, the output of the second register with the reset function and connected to the fourth input of the forecast module, the output of the fourth register is connected to the seventh input of the forecast module, the output of the first register is the input of the second register, the output of which is connected to the inverter, the output of the inverter is connected to the second input of the first adder, the output of the first register is connected to the first input of the first adder and the third input of the forecast module, the output of the first adder is connected to the fifth input of the forecast module, the output of the third register is connected to the sixth input of the forecast module, the first output of the forecast module is connected with the first input of the second adder, and the second and third output of the forecast module are connected to the second and third inputs of the correction module, respectively, the first input of the correction module is connected to the second input of the electronic device, the output of the third register is connected to the fourth input of the correction module, the output of the correction module is connected to the second the input of the second adder, the outputs of the first and second registers with a reset function are connected to the first and second inputs of the memory update module, respectively, the output of the third adder is connected to the third the memory update module, the fifth register output is connected to the fourth input of the memory update module, the first output of the memory update module is connected to the second inputs of the first and second registers with a reset function, and the second output of the memory update module is connected to the first input of the first register with a reset function and is the output of the electronic device, the output of the second adder is connected to the input of the fourth register and to the first input of the fourth adder, the output of the sixth register is the second input of the fourth adder, output for which, in turn, is connected to the second input of the multiplier, the first input of which is the output of the third register, the output of the multiplier is connected to the second input of the third adder, the first input of which is the second input of the electronic device, the first input of the electronic device is connected to the first input of the forecast module and the input of the first register, while the forecast module is designed to calculate the pseudorange measurement predicted for the next clock cycle, the correction module is designed to correct the value of K with length nyh signal losses, where K - a positive number which is determined once at the beginning of the reception, memory refresh module is intended to control the reliability of received pseudorange measurements. 2. The electronic device according to claim 1, in which the forecast module consists of one register, the first, second and third inverters, the first, second, third and fourth multipliers, the first, second, third and fourth adders, the calculation module -1 degree, with this, the first input of the forecast module is connected to the first input of the second adder, the second input of which is the output of the second inverter, the second input of the forecast module is connected to the second input of the third adder and the first input of the first adder, the second input of which is the output the first inverter, the third input of the forecast module is connected to the input of the second inverter, the fourth input of the forecast module is connected to the input of the first inverter, the fifth input of the forecast module is connected to the -1 degree calculation module, the sixth input of the forecast module is connected to the second input of the third multiplier, the first input of which is the seventh input of the forecast module, the output of the first adder is connected to the first input of the first multiplier, the second input of which is the output of the -1 degree calculation module, the output of the first multiplier is the second output ohm of the forecast module and the first input of the second multiplier, the second input of which is the output of the second adder, the output of the second multiplier is connected to the first input of the third adder, the output of the third multiplier is connected to the input of the third inverter, the output of which is connected to the second input of the fourth adder, the first input of which is the output the third adder, the output of the fourth adder is the third output of the forecast module and the first input of the fourth multiplier, the second input of which is the output of the register, the output of the fourth the multiplier is a first output of prediction module. 3. The electronic device according to claim 1, in which the correction module consists of the first, second and third registers, one inverter, one adder, one dividing by 4 module, one module for calculating the remainder of the division, the first and second comparators, the first, second, the third and fourth conjunction elements, one disjunction element and one negation element, wherein the first input of the correction module is connected to the inverter, the second input of the correction module is connected to the second input of the second comparator, the third input of the correction module is connected to the first input of the module for calculating the remainder of the division, the fourth input of the module for calculating the remainder of the division and with the input of the module for dividing by 4, the output of the first inverter and the output of the module for calculating the remainder of the division are connected to the first and second inputs of the adder, respectively, the output of the module dividing by 4 is connected to the second input of the first comparator, the first input of which is the output of the adder, the output of the first register is connected to the first input of the second comparator, the output of the first comparator is the first inputs for the first and second conjunction elements, the second input of the first conjunction element is the output of the second comparator, and the second input of the second conjunction element is the output of the negation element, the input of which is the output of the second comparator, the output of the first conjunction element is connected to the second input of the third conjunction element, the first the input of which is the output of the second register, the output of the second conjunction element is connected to the second input of the fourth conjunction element, whose first input is od the third register, the outputs of the third and fourth members are conjunctions of the first and second inputs respectively disjunction element, the output of which is the output correction unit. 4. The electronic device according to claim 1, in which the memory update module consists of one register, one inverter, first and second adders, first, second, third and fourth comparators, first, second and third conjunction elements, one disjunction element and one element denial, while the first input of the memory update module is connected to the first input of the first comparator, the second input of the memory update module is connected to the first input of the second comparator, the third input of the memory update module is the first inputs I have the second and third elements of the conjunctions, the third and fourth comparators, the fourth input of the memory update module is connected to the inverter input and the second input of the first adder, the second inputs for the first and second comparator are the register output, the outputs of the first and second comparators are connected to the first and second inputs of the first conjunction element, respectively, whose output is connected to the second input of the second conjunction element, in turn the output of which is the first inputs for the first and second adders, the output the inverter is connected to the second input of the second adder, the output of the first adder is connected to the second input of the third comparator, and the output of the second adder is connected to the second input of the fourth comparator, the outputs of the third and fourth comparators are connected to the first and second inputs of the disjunction element, respectively, the output of the disjunction element is the first output the memory update module and the input of the negation element, the output of which is the second input of the third conjunction element, the output of the third conjunction element is second Flash output of the memory update module.

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