RU2468498C1 - Selective amplifier - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: selective amplifier has a signal source (1), a first input transistor (2), a first current stabilising two-terminal device (3), a first power supply bus (4), a second power supply bus (5), a second input transistor (6), a first load resistor (7), a second current stabilising two-terminal device (8), a first balancing capacitor (9), a first frequency setting resistor (10), a second balancing capacitor (11), a third input transistor (12), a fourth input transistor (13), a third current stabilising two-terminal device (14), a fifth input transistor (15) base, a voltage source (16), a fourth current stabilising two-terminal device (17), a third balancing capacitor (18).

EFFECT: high Q-factor of the amplitude-frequency curve of the amplifier and its voltage gain at quasi-resonance frequency f₀.

2 cl, 11 dwg

Description

The present invention relates to the field of radio engineering and communications and can be used in microwave filtering devices of radio signals from cellular communication systems, satellite television, radar, etc.

Integrated operational amplifiers with special RC correction elements that form the amplitude-frequency characteristic of the resonance type are widely used today in the tasks of extracting high-frequency and microwave signals [1, 2]. However, the classical construction of such selective amplifiers (RC filters) is accompanied by significant energy losses, which are mainly used to ensure the static mode of a sufficiently large number of transistors forming an operational amplifier of the microwave range [1, 2]. In this regard, it is quite urgent to build microwave selective I / O amplifiers on two or three transistors, which provide a narrow signal spectrum with a sufficiently high quality factor of the resonant characteristic Q = 2 ÷ 10 and f ₀ = 1 ÷ 5 GHz.

Known amplifier circuits integrated into the architecture of RC filters based on transistors that provide the formation of the amplitude-frequency characteristics of the voltage gain in a given frequency range Δf = f _B -f _H [3-28]. Moreover, their upper cutoff frequency f _{B is} sometimes formed by the inertia of the transistors of the circuit (capacitance per substrate), and the lower f _H is determined by a correction capacitor.

The closest prototype of the claimed device is a selective amplifier (DUT), presented in patent US 4.267.518 fig.6. It contains a signal source 1, the first 2 input transistor, the emitter of which is connected through the first 3 current-stabilizing two-terminal to the first 4 bus of the power source, and the collector is connected to the second 5 bus of the power source, the second 6 input transistor, the collector of which is connected to the output of the device and through the first 7, the load resistor is connected to the second 5 bus of the power supply, and the emitter is connected to the first 4 bus of the power supply through the second 8 current-stabilizing two-terminal, the first 9 correction capacitor connected between the emitter mi of the first 2 and second 6 input transistors.

амплитудно-частотной характеристики (АЧХ) и коэффициент усиления по напряжению K₀>1 на частоте квазирезонанса (f₀).A significant disadvantage of the known device is that it does not provide high quality factor

amplitude-frequency characteristics (AFC) and voltage gain K ₀ > 1 at the frequency of quasi-resonance (f ₀ ).

The main objective of the invention is to increase the quality factor of the frequency response of the amplifier and its voltage gain at the frequency of quasi-resonance f ₀ . This allows in some cases to reduce the total power consumption and to implement a high-quality microwave device with f ₀ = 1 ÷ 5 GHz.

The problem is solved in that in the selective amplifier of figure 1, containing the signal source 1, the first 2 input transistor, the emitter of which is connected through the first 3 current-stabilizing two-terminal to the first 4 bus of the power source, and the collector is connected to the second 5 bus of the power source, second 6 an input transistor, the collector of which is connected to the output of the device and through the first 7 load resistor is connected to the second 5 bus of the power source, and the emitter is connected to the first 4 bus of the power supply through the second 8 current-stabilizing two-field Yusnik, the first 9 correction capacitor connected between the emitters of the first 2 and second 6 input transistors, new elements and connections are provided - in series with the first 9 correction capacitor, the first 10 frequency-setting resistor, a common node of the first 9 correction capacitor and frequency-setting resistor 10 connected to the signal source 1 through the second 11 correction capacitor, the base of the first 2 input transistor is connected to the output of the device, the emitter of the second 6 input transistor is connected to the base of the third o 12 input transistor, the emitter of which is connected to the emitter of the fourth 13 input transistor and is connected to the first 4 bus of the power supply through the third 14 current-stabilizing two-terminal, the base of the second 6 input transistor is connected to the base of the fifth 15 of the input transistor and connected to the voltage source 16, the emitter of the fifth 15 the input transistor is connected to the first 4 bus of the power source through the fourth 17 current-stabilizing bipolar and connected to the base of the fourth 13 output transistor, the collector of the fourth 13 input transi the stator is connected to the output of the device, and the collector of the third 12 and fifth 15 input transistors are connected to the second 5 bus of the power supply, and the third 18 correction capacitor is connected via alternating current parallel to the first 7 collector load resistor.

The amplifier circuit of the prototype is shown in the drawing of figure 1. The drawing of figure 2 presents a diagram of the inventive device in accordance with claim 1 of the claims.

The drawing of figure 3 shows a diagram of the DUT in accordance with claim 2.

The drawing of FIG. 4 is a diagram of the DUT of FIG. 2 in a Cadence environment on SiGe transistor models (SiGe: npnVs, W = 2, L = 2, SGB25VD process technology, Ik.max = 6 mA), and in the drawing of FIG. 5 is a logarithmic the amplitude-frequency characteristic of the DUT 4.

The drawing of Fig.6 shows the logarithmic amplitude and phase frequency characteristics of the DUT of Fig.4 on a smaller scale.

The drawing of Fig. 7 shows a diagram of the DUT of Fig. 2 in a Cadence environment on SiGe transistor models in the quality control mode by changing the collector current of the transistor Q ₁₅ (I _k15 = I _var ).

The drawing of Fig. 8 shows the logarithmic amplitude-frequency characteristics of the DUT of Fig. 7 in the Q factor control mode (graph 1, I _var = 2.5 mA, Q factor Q = 5; graph 2, I _var = 3 mA, Q = 10; graph 3, I _var = 3.5 mA, Q = 11; Q = 5 ÷ 11, f _p = f ₀ = 1,062 GHz ÷ 1,045 GHz).

The drawing of Fig.9 shows the logarithmic phase-frequency characteristics of the DUT of Fig.7 with a change in the collector current of the transistor 15 I _var = 2.5 ÷ 3.5 mA.

The drawing of Fig. 10 shows a filter diagram of Fig. 2 in a Cadence environment on SiGe transistor models (I _e10 = I _var = 1 ÷ 0.75 mA), which provides measures for adjusting the quasi-resonance frequency (f _p = f ₀ ).

The drawing of Fig. 11 shows the logarithmic amplitude and phase frequency characteristics of the DUT of Fig. 10 in the quasi-resonance frequency adjustment mode (f _p = f ₀ ) when the emitter current of the transistor Q10 changes within I _e10 = I _var = 1 ÷ 0.75 mA.

The selective amplifier of Fig. 2 contains a signal source 1, a first 2 input transistor, the emitter of which is connected through the first 3 current-stabilizing two-terminal to the first 4 bus of the power source, and the collector is connected to the second 5 bus of the power source, the second 6 input transistor, the collector of which is connected to the output devices and through the first 7 load resistor is connected to the second 5 bus of the power source, and the emitter is connected to the first 4 bus of the power source through the second 8 current-stabilizing two-terminal device, the first 9 correction capacitor connected between the emitters of the first 2 and second 6 input transistors. In series with the first 9 correction capacitor, the first 10 frequency-setting resistor is turned on, the common node of the first 9 correction capacitor and frequency-setting resistor 10 is connected to the signal source 1 through the second 11 correction capacitor, the base of the first 2 input transistor is connected to the output of the device, the emitter of the second 6 the input transistor is connected to the base of the third 12 input transistor, the emitter of which is connected to the emitter of the fourth 13 input transistor and is connected to the first 4 bus of the power source through thirds 14th current-stabilizing two-terminal, the base of the second 6 input transistor is connected to the base of the fifth 15 input transistor and connected to a voltage source 16, the emitter of the fifth 15 input transistor is connected to the first 4 bus power supply through the fourth 17 current-stabilizing two-terminal and connected to the base of the fourth 13 output transistor, the collector of the fourth 13 input transistor is connected to the output of the device, and the collector of the third 12 and fifth 15 input transistors are connected to the second 5 bus of the power source, and a first collector load resistor 7 is turned on by the third alternating current compensation capacitor 18.

In the drawing of Fig. 3, in accordance with claim 2, the emitter of the third 12 input transistor is connected to the emitter of the fourth 13 input transistor through the fourth 19 correction capacitor, the emitter of the fourth 13 output transistor connected to the first 4 bus of the power supply through the fifth 20 current-stabilizing two-terminal device. To balance the static mode, a resistor 21 is introduced.

Consider the operation of the DUT figure 2.

The source of the input variable signal u _in (1) through the complex input conductivity of the DUT formed by the first 9 and second 11 correction capacitors, a frequency-setting resistor 10 and the input resistance of the second 6 input transistor changes its emitter and collector currents, and with increasing frequency (f) input signal, these currents increase. The currents of the third 12 and fourth 13 input transistors change in a similar way. The total collector current of the second 6 and fourth 13 input transistors due to the voltage drop on the third 18 corrective capacitor, the first 7 load resistor implements the output voltage of the DUT (output 1). The frequency dependence of this voltage in the low-frequency range (f <f ₀ ) is determined by the nature of the input conductivity of the DUT (first 10 frequency-setting resistor, the first 9 and second 11 correcting capacitors), and in the high-frequency range (f> f ₀ ) - by the nature of the resistance load (the first 7 load resistor and the third 18 correction capacitor). That is why, in the DUT scheme, the necessary form of its amplitude-frequency characteristic is realized (maximum gain at the frequency of quasi-resonance f ₀ ). The interaction of the base circuit of transistor 2 with the output circuit of the DUT by means of a capacitive divider in the circuit of its emitter (the first 9 and second 11 correcting capacitors) ensures the implementation of the general feedback in the DUT, aimed at increasing the quality factor Q and gain K ₀ . In the low-frequency region due to the first 9 correcting capacitor, this feedback is reactive, and, therefore, weakly affects the total collector current of the second 6 and fourth 13 input transistors. As the frequency increases (its approach to the frequency of quasi-resonance f ₀ ), these currents increase, increasing Q and K ₀ . Due to the fact that basically the first 7 load resistor and the first 10 frequency-setting resistor, the first 9, second 11 and third 18 correction capacitors determine the frequency of quasi-resonance, the depth of this feedback reaches its maximum value at this frequency, and the transmission coefficients of the cascades at the second 6, third 12, fourth 13 and first 2 input transistors determine a relatively large figure of merit and proportional to this parameter - the gain of the DUT.

Let us show analytically that higher values of K ₀ and Q in the high frequency range are implemented in the scheme of figure 2.

Indeed, the integrated voltage transfer coefficient of the DUT of FIG. 2 is determined by the formula:

Where

τ ₁ = (C ₉ + C ₁₁ ) (R ₁₀ + h _11.2 + h _11.6 );

τ ₂ = C ₁₈ R ₇ ,

where α _i is the transfer coefficient of the emitter current of the i-th transistor, h _11.i is the input differential resistance (h-parameter) of the i-th transistor in a circuit with a common base, I _i is the current of the i-ro current source.

Relation (3) shows that the required value of Q in the inventive circuit is implemented regardless of the given frequency of quasi-resonance (2) by choosing the ratio between the currents I ₁₄ and I _{8 of the} third 14 and second 8 of the current-stabilizing two-terminal devices. In this case, the capacitance of the first 9, second 11 and third 18 correction capacitors and the resistance of the first 10 frequency-setting resistor and the fourth 17 current-stabilizing bipolar can be used to implement the numerical value f ₀ (2), and the ratio between the capacitances C ₉ and C ₁₁ to ensure the necessary value of the gain of the DUT (4), which is proportional to the realized Q factor Q.

If the emitter circuits of the third 12 and fourth 13 input transistors are separated by the fourth 19 correction capacitor of Fig. 3, then this circuit can be used when implementing the DUT with a mode-controlled quasi-resonance frequency f ₀ .

Indeed, in this case

τ ₁ = (C ₉ + C ₁₁ ) (R ₁₀ + h _11.2 + h _11.6 ) + C ₁₉ (h _11.13 + h _11.12 );

τ ₂ = C ₁₈ R ₇ ,

where h _11.13 = φ _T / I ₂₀ , h _11.12 = φ _T / I ₁₄ , φ _T = kT / q.

As follows from (5), a change in the currents of the fifth 20 and third 14 current-stabilizing bipolar leads to a change in f ₀ . Moreover, the nature of the change in Q and K ₀ is determined by the relations between the time constants τ ₁ and τ ₂ and the numerical value of the realized Q factor Q.

These theoretical conclusions confirm the graphs of FIG. 5, FIG. 6, FIG. 8, FIG. 9, FIG. 11.

Thus, the claimed circuit solution is characterized by higher values of the gain at the frequency of the quasi-resonance f ₀ and increased values of the quality factor characterizing its selective properties.

BIBLIOGRAPHIC LIST

1. Design of Bipolar Differential OpAmps with Unity Gain Bandwidth up to 23 GHz / N.Prokopenko, A. Budyakov, K.Schmalz, C.Scheytt, P. Ostrovskyy // Proceeding of the 4-th European Conference on Circuits and Systems for Communications - ECCSC'08 / - Politehnica University, Bucharest, Romania: July 10-11, 2008. - pp.50-53

2. Microwave SF blocks of communication systems based on fully differential operational amplifiers / Prokopenko NN, Budyakov AS, K. Schmalz, S.Scheytt // Problems of developing promising micro- and nanoelectronic systems - 2010. Proceedings / under the general ed. Academician of the Russian Academy of Sciences A.L. Stempkovsky. - M .: IPPM RAS, 2010. - P.583-586

3. Patent WO / 2006/077525

4. Patent US 4.267.518, fig. 6

5. Patent RU 2101850, fig. 1

6. Patent WO / 2007/022705

7. Patent application US 2006/0186951, fig.3

8. Patent application US 2007/0040604, fig.3

9. Patent WO / 03052925 A1, fig. 3

10. Patent US 6.011.431, fig. 4

11. Patent US 5.331.478, fig. 3

12. US patent 4.885.548, fig. 9

13. Patent US 4.974.916, fig. 1

14. Patent application US 2008/0122530, fig. 4

15. Patent US 5.298.802

16. Patent US 2009/0261899, fig. 3

17. Patent CN 101204009

18. Patent EP 1844547

19. Patent UA 17276

20. Patent US 2009/0289714, fig. 4

21. Patent US 7.202.762

22. Patent US 6.188.272

23. Patent US 5.847.605

24. Patent US 7.116.961

25. Patent application US 2011/0109388, fig.2

26. Patent application US 2006/0186951, fig.2

27. Patent US 5.012.201, fig.2

28. Patent application US 2010/0201437, fig.2

Claims (2)

1. A selective amplifier containing a signal source (1), a first (2) input transistor, the emitter of which through the first (3) current-stabilizing two-terminal device is connected to the first (4) bus of the power source, and the collector is connected to the second (5) bus of the power source, a second (6) input transistor, the collector of which is connected to the output of the device and through the first (7) load resistor is connected to the second (5) bus of the power source, and the emitter is connected to the first (4) bus of the power source through the second (8) current-stabilizing two-terminal device, first (9) corrective an on-capacitor connected between the emitters of the first (2) and second (6) input transistors, characterized in that the first (10) frequency-setting resistor, the common node of the first (9) correction-capacitor and the frequency-voltage are connected in series with the first (9) correction capacitor the driving resistor (10) is connected to the signal source (1) through the second (11) correction capacitor, the base of the first (2) input transistor is connected to the output of the device, the emitter of the second (6) input transistor is connected to the base of the third (12) input transistor, emitter to connected to the emitter of the fourth (13) input transistor and connected to the first (4) bus of the power supply through the third (14) current-stabilizing two-terminal device, the base of the second (6) input transistor is connected to the base of the fifth (15) input transistor and connected to a voltage source ( 16), the emitter of the fifth (15) input transistor is connected to the first (4) bus of the power source through the fourth (17) current-stabilizing two-terminal device and connected to the base of the fourth (13) output transistor, the collector of the fourth (13) input transistor is connected to the output device, and the third collector (12) and fifth (15) input transistors connected with the second (5) power supply bus, and parallel to the first (7) of the collector load resistor switched AC third (18) correction capacitor. 2. The selective amplifier according to claim 1, characterized in that the emitter of the third (12) input transistor is connected to the emitter of the fourth (13) input transistor through the fourth (19) correction capacitor, the emitter of the fourth (13) output transistor connected to the first (4 ) power supply bus through the fifth (20) current-stabilizing two-terminal network.

Images