RU2454792C2 - Generation of oscillator signal with suppression of spurious peaks in wireless communication device - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: phase-locked loop can be used to generate an oscillator signal for a selected frequency channel. Different settings of the phase-locked loop can be used for units in the phase-locked loop for different frequency channels. Different settings of the phase-locked loop can exist for different ranges of the phase-locked loop bandwidth, for different current values of the charge pump, for different frequency equations corresponding to different sets of high and low divider coefficients, for different frequency division systems corresponding to different prescaler coefficients and/or integral divider coefficients, for adjusting the signal amplitude in the upper or lower part for the superheterodyne receiver or transmitter, and/or for different supply voltages for one or more units of the circuit, such as an oscillator. The suitable set of settings of the phase-locked loop can be selected for each frequency channel.

EFFECT: reduced negative effect of spurious peaks, and improved operating characteristics for the frequency channel.

26 cl, 11 dwg

Description

This application claims priority based on provisional application US No. 60/972721 entitled "FORMATION OF A HETERODYN SIGNAL WITH SUPPRESSION OF VARIABLE PEAKS IN A WIRELESS COMMUNICATION DEVICE", filed September 14, 2007, which is owned by the copyright holder of this application and incorporated into this document by reference; and based on provisional application US No. 60/976285, entitled "FORMATION OF A HETERODYN SIGNAL WITH SUPPRESSION OF VARIABLE PEAKS IN A WIRELESS COMMUNICATION DEVICE", filed September 28, 2007, the rights to which are owned by the copyright holder of this application and incorporated herein by reference.

Technical field

The present disclosure generally relates to electronics and, in particular, to methods for generating signals of an oscillation generator in a wireless communication device.

State of the art

A wireless communication device (eg, a cell phone) may have a transmitter and a receiver to support two-way radio communication with a wireless communication system. For data transmission, the transmitter can convert the up-converted baseband output signal using one or more transmit local oscillator (LO) signals to receive the up-converted signal. The transmitter may further filter and amplify the upconverted signal to obtain an output radio frequency (RF) signal, and then may transmit the signal through a wireless channel to base stations in a wireless communication system. To receive data, the receiver can receive signals from base stations and receive a received radio frequency signal. The receiver can amplify, filter, and downconvert the received RF signal using one or more receive local oscillator signals to obtain an input signal of the base band. The local oscillator signals can be generated based on the signals of the oscillation generator, which can be generated by the oscillation generators in the wireless device.

A wireless device typically includes various analog circuits for processing analog signals in a transmitter and a receiver. Analog circuits may include amplifiers, mixers, filters, phase locked loop (PLL), local oscillators, etc. Analog circuits can work with analog signals with low signal levels. Therefore, analog circuits should be subject to as little noise as possible in order to maintain signal quality and achieve good performance.

A wireless device typically also includes digital circuits for digitally processing transmitted and / or received data. The digital circuit may include microprocessors, memory units, controllers, etc., which can operate on the basis of clock pulses. Digital circuits typically have large signal spans and generate a lot of digital noise, including spurious peaks. A sharp peak is an unwanted signal at a given frequency or tone generated within a wireless device. Spurious peaks can be formed by means of clock pulses, by summing the clock pulses and signals of the oscillation generator, etc. Spurious peaks from digital circuits can have large levels due to large and sharp changes in the signals of digital circuits.

Spurious peaks from digital circuits can degrade the performance of analog circuits in various ways. First, the oscillator signals used to generate the local oscillator signals for frequency conversion by means of analog circuits may contain spurious peaks, which can then degrade the received or transmitted useful signal. Secondly, spurious peaks can add to the out-of-band signal components and produce in-band noise, which can degrade the signal-to-noise ratio (SNR) of the desired signal. Thirdly, spurious peaks can appear at the inputs of the receiver and / or the outputs of the transmitter in the target frequency band due to the connecting lines of the substrate or the housing, when analog and digital circuits are integrated in the same integrated circuit (IC), and thereby degrade the signal ratio to noise (SNR) of the desired signal.

To suppress the negative effects due to spurious peaks, analog circuits can be isolated from digital circuits, which can reduce the spurious peaks from digital circuits pointing to analog circuits. This isolation can be achieved by (i) implementing analog and digital circuits on separate printed circuit boards or separate sections of a printed circuit board, or (ii) implementing analog circuits on one or more crystals of analog integrated circuits (ICs; IC) and implementing digital circuits on one or more crystals of digital ICs. However, it may be difficult to achieve the desired insulation value, or even to predict the amount of insulation that can be achieved, due to design constraints. In addition, it may be desirable to integrate analog and digital circuits (for example, on the same IC chip) in order to reduce the size and cost of the device. Thus, methods that can suppress the negative effects of spurious peaks are very desirable.

SUMMARY OF THE INVENTION

Methods for generating waveform generator signals in a wireless communication device with non-uniform frequency programming are described herein to suppress the harmful effects of spurious peaks. To generate the signal of the oscillation generator for the selected frequency channel, a phase-locked loop (PLL) can be used. The PLL system may include a phase-frequency detector, a charge pump generator, a loop filter, and a divider. Using non-uniform frequency programming, different PLL settings can be used for different blocks in the PLL system designed for different frequency channels. In general, the tuning of the PLL system can be performed for any parameter related to the formation of the signal of the oscillation generator. A suitable set of PLL settings can be selected for each frequency channel so that the negative effects of spurious peaks can be suppressed, and a good performance can be achieved for the frequency channel.

In an aspect of the invention, different PLL system frequency ranges may be supported, and a suitable PLL loop bandwidth may be selected for each frequency channel. A narrow contour bandwidth can be selected when spurious peaks are outside the contour bandwidth to reduce spurious peaks. A wider loop bandwidth can be used when spurious peaks outside the loop bandwidth are not present at problematic frequencies in order to better suppress sources of non-parasitic (unmanned) noise, such as an oscillator. The loop bandwidth can be variable, for example, by adjusting the current value of the charge pump generator.

In another aspect, different frequency equations may be supported, and a suitable frequency equation may be selected for each frequency channel. Different sets of high and low divider coefficients in a fractional divider can correspond to different frequency equations. Different spurious peaks and / or different levels of spurious peaks may be present for different frequency equations. For each frequency channel, a frequency equation can be selected with good performance in terms of spurious peaks.

In yet another aspect, different frequency division schemes may be supported, and a suitable frequency division scheme may be selected for each frequency channel. Different patterns of frequency division may correspond to different coefficients of the preliminary divider and / or different coefficients of the integer divider. For different frequency division schemes, different spurious peaks and / or different levels of spurious peaks may be present. For each frequency channel, a division circuit with good performance can be selected in terms of spurious peaks.

In yet another aspect, for the frequency channel in the superheterodyne receiver or transmitter, a local oscillator amplitude adjustment at the top or bottom may be selected. The local oscillator signal will be higher in frequency than the selected frequency channel to adjust the signal amplitude in the upper part, and lower than the selected frequency channel to adjust the signal amplitude in the lower part. Adjusting the amplitude in the upper or lower part may correspond to different spurious peaks and / or different levels of spurious peaks. The adjustment of the local oscillator amplitude in the upper or lower part can be selected based on the operating characteristic in terms of spurious peaks.

In yet another aspect, different supply voltages may be supported for a given circuit block, and a suitable supply voltage may be selected for the circuit block intended for each frequency channel. In one embodiment, different supply voltages may be used for the oscillator. High supply voltage can be used to increase the signal amplitude of the oscillation generator, which can reduce the negative effects due to spurious peaks. A low supply voltage can be used when large spurious peaks are not present to save power.

There may also be different PLL settings for other parameters. Various aspects and features of the disclosure are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

1 shows a wireless communication device supporting different systems.

Figure 2 shows a block diagram of a wireless device.

Figure 3 shows a block diagram of a direct conversion receiver.

4 shows a block diagram of a superheterodyne receiver.

5 shows a block diagram of a direct conversion transmitter.

6 shows a block diagram of a superheterodyne transmitter.

7 shows a block diagram of a PLL system in a frequency synthesizer.

Fig. 8 shows a block diagram of an embodiment of a divider in a PLL system.

9 shows a block diagram of another embodiment of a divider in a PLL system.

10 shows a PLL system settings table for different frequency channels.

11 shows a process for generating an oscillator signal for a frequency channel.

DETAILED DESCRIPTION OF THE INVENTION

1 shows a wireless communication device 110 that can communicate with various wireless communication systems and networks. The terms “system” and “network” are often used interchangeably. In the example shown in FIG. 1, the wireless communication device 110 can communicate with a wireless wide area network (WWAN) 120, a wireless local area network (WLAN) 130, a wireless personal area network (WPAN) 140, a satellite positioning system (SPS) 150, and a system 160 broadcasting. In general, a wireless communication device 110 may interact with any number, any type, and any combination of one or more systems and networks.

WWAN 120 provides a communications coverage area for a large geographic area, such as a city, region, or an entire country. WWAN 120 may be a code division multiple access (CDMA) network, a time division multiple access network (TDMA), a frequency division multiple access network (FDMA), an orthogonal frequency division multiple access network (OFDMA), a multiple access network with single-carrier frequency division (SC-FDMA), etc. A CDMA network can implement wireless technology such as CDMA2000 Universal Terrestrial Wireless Access (UTRA). CDMA2000 technology covers IS-2000, IS-95, and IS-856 standards. UTRA technology includes CDMA Broadband Access (W-CDMA) and other options for CDMA networks. A TDMA network can implement wireless technology such as Global System for Mobile Communications (GSM), Digital Advanced Mobile Communications System (D-AMPS), etc. An OFDMA network can implement wireless technology such as Advanced UTRA (E-UTRA), Ultra Mobile Broadcast (UMB), IEEE 802.16 (WiMAX), IEEE 802.20, Flash-OFDM®, etc. UTRA and E-UTRA technologies are part of the Universal Mobile Communications System (UMTS). The Long-Term Development Project (LTE) system of the Third Generation Network Partnership Project (3GPP) is the upcoming release of the UMTS system that uses E-UTRA technology. These various networks, wireless technologies and standards are known in the art.

The WLAN network 130 provides a communication coverage area for an average geographical area, such as for example a building, a house, etc. A WLAN 130 can implement wireless technology such as any standard in the IEEE 802.11 family of standards, Hiperlan technology, etc. The 140 WPAN network provides communications coverage for a small geographic area. The WPAN 140 may implement Bluetooth technology, which is short-range wireless technology adopted as the IEEE 802.15 standard.

The satellite positioning system 150 may be an American global positioning system (GPS), the Russian GLONASS system, the European Galileo system or some other satellite positioning system. The GPS system is a collection of 24 satellites with good diversity, plus some spare satellites in low Earth orbit. Each GPS satellite transmits a coded signal that allows the receivers on the ground to accurately determine their location based on measurements for a sufficient number of satellites (usually four) and the known locations of these satellites. Broadcasting system 160 may be a MediaFLO system, a digital television system for handheld computers (DVB-H), a digital broadcasting system with integrated services for terrestrial television broadcasting (ISDB-T), a digital broadcasting system (DMB), or some other broadcasting system.

The wireless communication device 110 may be fixed or mobile, and may also be called a mobile station, user equipment, terminal, station, subscriber unit, etc. The wireless communication device 110 may be a cell phone, PDA, wireless modem, handheld device, laptop computer, cordless phone, etc. As shown in FIG. 1, the wireless communication device 110 can communicate bi-directionally with base stations 122 in the WWAN 120, an access point 132 in the WLAN 130, and / or a portable telephone 142 in the WPAN 140 at any given time. Wireless device 110 may also receive signals from satellites 152 in SPS system 150 and / or broadcast stations 162 in broadcast system 160 at any given point in time. Wireless device 110 may process the received signal and / or generate a transmission signal for each system based on the wireless technology used by this system.

2 shows a block diagram of an embodiment of a wireless communication device 110. In this embodiment, the wireless communication device 110 includes a transceiver 214 having a receiver 220a and a transmitter 230a for WWAN 120, a receiver 220b and a transmitter 230b for WLAN 130, a receiver 220c and a transmitter 230c for WPAN 140, a receiver 220d for SPS 150 and a receiver 220e for the broadcast system 160. Each receiver 220 may process the received signal for a respective system and provide an input signal of a baseband to a digital processor 250. Each transmitter 230 may receive an output signal of a baseband from a digital processor 250 and generate a transmission signal for the corresponding system. The antenna switch module 212 connects the receivers 220a-220e and the transmitters 230a-230c to the antennas 210a and 210b. Module 212 may include one or more switches, antenna switches, antenna branching devices, etc., to direct received signals from antennas 210 to receivers 220 and direct transmission signals from transmitters 230 to antennas 210. In general, the device 110 is wireless Communications may include any number of antennas, any number of receivers and any number of transmitters for any number of systems and frequency bands.

Digital processor 250 may include various processing units for transmitting and receiving data and for performing other functions. For example, the digital processor 250 may include one or more digital signal processors (DSPs), processors for computers with a reduced instruction set (RISC), central processing units (CPUs), etc. The controller / processor 260 may control operation in the wireless device 110. A memory 262 may store program codes and data for the wireless device 110. Processor 250, controller / processor 260, and / or memory 262 may be implemented on one or more specialized integrated circuits (ASICs) and / or other ICs.

The reference signal generator 268 generates a reference signal having a frequency f _ref that is relatively accurate. Generator 268 may be a crystal oscillator (XO), a voltage controlled crystal oscillator (VCXO), a temperature compensated crystal oscillator (TCXO), a voltage controlled TCXO oscillator (VC-TCXO), or some other type of generator. Frequency synthesizers 270 receive the reference signal and generate the signals of the oscillation generator. The local oscillator generators 272 receive the oscillator signals from the frequency synthesizers 270 and generate the local oscillator signals for the receivers 220 and the transmitters 230. The frequency synthesizers 270 may include any number of phase-locked loop systems to generate any number of oscillator signals. The clock generator 274 also receives a reference signal and generates clock pulses for the digital processor 250, controller / processor 260, and memory 262. All receivers 220a-220e, transmitters 230a-230c, oscillation generator 268, frequency synthesizers 270 and / or local oscillator generators 272 or part of they can be implemented on one or more radio frequency integrated circuits (RFIC), analog-to-digital ICs, specialized integrated circuits (ASIC), etc.

In general, a transmitter or receiver may be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, a signal frequency is converted between a radio frequency (RF) and a base band in a plurality of steps, for example, from a radio frequency to an intermediate frequency (IF) in one step and then from an intermediate frequency to a base band in another step for the receiver. In direct conversion architecture, also called Zero Intermediate Frequency (ZIF) architecture, the signal frequency is converted between the radio frequency and the base band in a single step. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements.

Each system can operate on one or more frequency channels in one or more frequency bands. A frequency channel may also be called a CDMA channel, a radio frequency channel, etc. For the CDMA2000 system, each frequency channel has a bandwidth of 1.23 MHz and a center frequency located at 30 kHz discrete or incremental. For a W-CDMA system, each frequency channel has a bandwidth of 3.84 MHz and a center frequency discrete at 200 kHz. For a GSM system, each frequency channel has a bandwidth of 200 kHz and a center frequency located at 200 kHz discretely. The center frequency and bandwidth of each frequency channel may vary by system.

FIG. 3 shows a block diagram of an embodiment of a direct conversion receiver 220x that can be used for any of the receivers 220a-220e in FIG. 2. At a 220x receiver, a low noise (LNA) amplifier 310 amplifies a received V _RX signal from an antenna switch module 212 and provides an amplified signal. Filter 312 filters the amplified signal to skip signal components in the frequency band of interest and remove out-of-band noise and unwanted signals. The mixer 314 down-converts the filtered signal using the local oscillator V _{RX_LO} signal from the local oscillator generators 272 and provides a down-converted signal. The frequency f _{RX_LO of} the local oscillator signal is selected so that the useful signal in the selected frequency channel is converted with decreasing frequency into the main band or almost to the main band.

A variable gain amplifier (VGA) 316 amplifies the downconverted signal with a variable gain and provides a signal having a desired signal level. The low-pass filter 318 filters the signal from the VGA amplifier 316 to skip the desired signal in the selected frequency channel and remove noise and unwanted signals that may be generated by the down-conversion process. An amplifier 320 amplifies and buffers a signal from a filter 318 and provides an input signal V _{IN of a} baseband to a digital processor 250.

FIG. 4 shows a block diagram of an embodiment of a superheterodyne receiver 220y, which can also be used for any of the receivers 220a-220e in FIG. 2. At receiver 220y, the received V _RX signal is amplified by an LNA amplifier 410, filtered by a filter 412, and downconverted from the radio frequency to an intermediate frequency by the mixer 414 using the first local oscillator signal V _{RX_LO1} from the local oscillator 272. The frequency f _{RX_LO1 of the} first local oscillator signal can be selected so that the useful signal in the selected frequency channel is converted with decreasing frequency to a predetermined intermediate frequency.

The intermediate frequency signal from the mixer 414 is amplified by a VGA amplifier 416, filtered by a filter 418, and downconverted from the intermediate frequency to the main band or almost to the main band by the mixer 420 using the second V _{RX_LO2} local oscillator signal from the local oscillator 272. The frequency f _{RX_LO2 of the} second local oscillator signal depends on the intermediate frequency. The downconverted signal from mixer 420 is filtered by a filter 422 and amplified by an amplifier 424 to receive an input signal V _{IN of the} base band, which is provided to the digital processor 250.

FIG. 5 shows a block diagram of an embodiment of a direct conversion transmitter 230x that can be used for any of the transmitters 230a-230c in FIG. 2. In the 230x transmitter, the output signal V _{OUT of the} base band is amplified by an amplifier 510, filtered by a low-pass filter 512 to remove the displayed signals caused by digital-to-analog conversion, amplified by a VGA amplifier 514 and converted with increasing frequency from the main band to the radio frequency by the mixer 516 using the V _{TX_LO} local oscillator signal generators 272 local oscillators. The down-converted signal is filtered by a band-pass filter 518 to remove the displayed signals caused by the up-conversion, and then amplified by a power amplifier 520 (PA) to generate a V _TX transmission signal.

FIG. 6 shows a block diagram of an embodiment of a superheterodyne transmitter 230y, which can also be used for any of the transmitters 230a-230c in FIG. 2. In the transmitter 230y, the output signal V _{OUT of the} main band is amplified by an amplifier 610, filtered by a low-pass filter 612, amplified by a VGA amplifier 614 and converted with increasing frequency from the main band to an intermediate frequency by a mixer 616 using the first local oscillator signal V _{TX_LO1} from the oscillator 272. The intermediate frequency signal is filtered by a filter 618, amplified by a VGA amplifier 620, and converted with increasing frequency from the intermediate frequency to the radio frequency by the mixer 622 using the second local oscillator signal V _{TX_LO2} from the local oscillator generators 272. The down-converted signal is filtered by a band-pass filter 624 and then amplified by a power amplifier 626 to generate a V _TX transmission signal.

Figures 3-6 show some illustrative embodiments of a transmitter and a receiver. In general, signal processing at a transmitter or receiver may be performed by one or more amplifier, filter, mixer, etc. circuits. These circuit blocks may be placed differently from the configurations shown in FIGS. 3-6. In addition, other circuit blocks not shown in FIGS. 3-6 can be used to process the signals at the transmitter and receiver. Some blocks of the circuit in FIGS. 3-6 may also be omitted. For example, filters 312 and 412 in FIGS. 3 and 4 can be omitted, and the output of the LNA amplifiers can be connected directly to the mixers.

FIG. 7 shows a block diagram of an embodiment of a frequency synthesizer 700 that can be used for frequency synthesizers 270 in FIG. 2. Frequency synthesizer 700 includes a phase locked loop (PLL) system 702 and a voltage controlled oscillator 740 (VCO). VCO 740 generates a VCO signal having a frequency V _VCO , which is determined by the control signal V _CTRL from the filter 730 feedback circuit in the system 702 PLL.

In the PLL system 702, a divider 750 divides the VCO signal in frequency with a factor R _k and provides a feedback signal. In the general case, the coefficient R _k may have an integer or non-integer value and may be determined as described below. A phase-frequency detector 710 (PFD) receives a reference signal from an oscillation generator 268 and a feedback signal from a divider 750. A detector 710 compares the phases of the two signals and provides a detector signal that indicates the phase difference / error between the two signals. The charge pump generator 720 generates an error signal _{CP CP} , which is proportional to the detected phase error. The loop filter 730 filters the error signal and provides a control signal for the VCO 740. The loop filter 730 corrects the control signal so that the phase and frequency of the feedback signal are aligned with the phase and frequency of the reference signal. The loop filter 730 has a frequency response that can be selected to achieve the desired closed loop response for the PLL system 702. For example, the frequency response of the loop filter 730 may be selected based on the balance between the location and tracking response and the noise response.

The local oscillator generator 760 may be used for the local oscillator generators 272 of FIG. 2. The local oscillator 760 may receive a VCO signal from the VCO 740 and provide a local oscillator signal having a frequency f _LO . The local oscillator generator 760 may include a buffer, divider, quadrature splitter, etc. In one embodiment, the VCO 740 operates at a local oscillator frequency such that f _VCO = f _LO . In another embodiment, the VCO 740 operates at a frequency of S times the local oscillator frequency, so that f _VCO = S · f _LO , and the VCO signal can be frequency divided by an integer coefficient S to obtain the local oscillator signal.

The voltage regulator 770 can generate a supply voltage V _{DD_VCO} for VCO 740, a supply voltage V _{DD_DIV} for a divider 750, and possibly other supply voltages for other elements in the frequency synthesizer 700. In general, the voltage regulator 770 can generate any number of supply voltages for any number elements in the frequency synthesizer 700.

7 shows an illustrative embodiment of a PLL system 702 and a frequency synthesizer 700. A PLL system 702 and a frequency synthesizer 700 may also include other and / or additional blocks. Each block in the PLL system 702 may be implemented using digital circuits, analog circuits, or combinations thereof.

In the embodiment shown in FIG. 7, various blocks in the PLL system 702 or frequency synthesizer 700 may be controlled based on appropriate control signals to achieve good performance. The control signal PFD_Control can adjust the gain of the phase-frequency detector 710. The control signal CP_Control can adjust the amount of current through the current sources 722a and 722b in the charge pump generator 720, which would change the gain of the charge pump generator. The control signal LF_Control can adjust the values of the circuit components (eg, capacitors) in the loop filter 730. The control signal VCO_Control can adjust the values of the circuit components (e.g. capacitors) in the VCO 740 to achieve the desired oscillation frequency. The control signal Divider_Control can select a suitable common factor R _{k of the} divider and determine the configuration of the divider 750, as described below. The VR_Control control signal can set the supply voltage for the VCO 740, divider 750, etc. In general, a frequency synthesizer may include one or more control signals for one or more blocks in a frequency synthesizer. The frequency synthesizer may include all control signals shown in FIG. 7, or a subset thereof, and may also include other control signals not shown in FIG. 7.

7 shows a frequency synthesizer 700 and a local oscillator 760 for generating one VCO signal and one local oscillator signal, respectively. A plurality of frequency synthesizers and a plurality of local oscillator generators 760 can be used to generate a plurality of VCO signals and a plurality of local oscillator signals simultaneously. For example, two frequency synthesizers 700 can be used to generate two VCO signals, and two local oscillators can be used to generate two local oscillator signals at frequencies f _{RX_LO1} and f _{RX_LO2} for superheterodyne receiver 220y in FIG. 4. The frequency f _{RX_LO1 of the} local oscillator can be variable and depend on the selected frequency channel, while the frequency f _{RX_LO2 of the} local oscillator can be at a fixed intermediate frequency. In general, any number of frequency synthesizers 700 and any number of local oscillator generators 760 can be used to generate any number of VCO signals and any number of local oscillator signals that can be designed for any number of receivers and transmitters.

Frequency synthesizer 700 may support multiple frequency channels for one or more systems and one or more frequency bands. Each frequency channel has a predetermined center frequency. Frequency synthesizer 700 can be controlled to generate the proper VCO signal, which can be used by the local oscillator 760 to generate the local oscillator signal at the appropriate frequency and with the desired characteristics for the selected frequency channel. For example, the desired _VCO frequency _VCO VCO can be obtained by selecting the appropriate common factor R _k for the divider 750. The desired characteristics of the VCO signal can be obtained by controlling the gain of the phase-frequency detector 710, the current value in the charge pump generator 720, the values of the components of the loop filter 730, configuration divider 750 and / or supply voltage for VCO 740, divider 750, etc.

The analog and digital circuits in the wireless device 110 may be implemented in close proximity to each other. For example, analog and digital circuits can be implemented on the same printed circuit board or on the same integrated circuit chip (IC). As the manufacturing technology of the IC improves, it will be possible to construct high-frequency analog circuits (for example, with a frequency of the order of GHz) using the technology of complementary metal oxide semiconductors (CMOS; CMOS), which was originally used for digital circuits. Then this can allow the integration of analog and digital circuits on the same IC chip. However, digital circuits typically form many spurious peaks that can be added to analog circuits through a substrate and / or other mechanisms. Spurious peaks can adversely affect the performance of analog circuits and interfere with the integration of analog circuits with digital circuits.

Spurious peaks can be formed within the wireless device 110 in different ways. Spurious peaks can be generated by sync pulses within the wireless device 110 and can appear at the harmonics of these sync pulses. For example, clock pulses may be generated based on a reference signal from oscillation generator 268, and spurious peaks in harmonics of frequency f _ref may be set within wireless device 110. Clock pulses with higher frequencies (eg, on the order of hundreds of MHz) may be generated by clock generator 274 and output digital microprocessor 250 and other digital circuits. Then spurious peaks can be present in harmonics of sync pulses with higher frequencies. Spurious peaks can also be formed by mixing the harmonics of the clock and VCO frequencies. For example, spurious peaks can be formed at frequencies f _VCO ± n · f _ref , where n is the serial number of the harmonic of the reference signal. If the local oscillator frequency is obtained by dividing the VCO frequency by the coefficient S, then spurious peaks can be formed at frequencies f _VCO / S ± n · f _ref . Thus, the wireless device 110 may have fixed spurious peaks at particular frequencies (e.g., in harmonics), as well as channel-dependent spurious peaks at frequencies determined based on the _VCO VCO frequency f and the PLL system configuration for the selected frequency channel.

Frequency programming refers to the programming of various blocks in the PLL system or frequency synthesizer to obtain the desired frequency and characteristics for the VCO signal. The PLL system can support multiple frequency channels and can be programmed in the same way for all supported frequency channels. For example, all frequency channels may have the same settings for all blocks in the PLL except for the full division coefficient R _k in the divider 750. In this case, some of the supported frequency channels may have excessive degradation due to spurious peaks, while other frequency channels channels may not experience spurious peaks.

In an aspect of the invention, non-uniform frequency programming can be used to eliminate spurious peaks or reduce spurious peak levels for frequency channels supported by the wireless device 110. For non-uniform frequency programming for different frequency channels, different settings for blocks in the PLL or frequency synthesizer system can be used. A suitable set of PLL settings can be selected for each frequency channel so that negative effects due to spurious peaks can be suppressed, and good performance can be achieved for the frequency channel. Inhomogeneous frequency programming may be supported by one or more of the following means:

- The use of different ranges of the frequency band of the PLL,

- The use of different frequency equations,

- The use of different frequency division schemes,

- Using signal amplitude adjustment at the top or bottom for superheterodyne architecture, and

- The use of different supply voltages for blocks in the frequency synthesizer.

In an aspect of the invention, the PLL loop bandwidth can be adjusted based on the frequency placement of spurious peaks. The PLL system can be configured to have a nominal loop bandwidth (for example, of the order of tens of kHz), which can be selected based on the balance between the detection and tracking characteristic and the noise characteristic. If spurious peaks are located outside the bandwidth of the contour, then the width of the band of the contour can be reduced to achieve greater suppression of spurious peaks. A smaller loop bandwidth can be obtained by decreasing the gain of the phase-frequency detector 710, decreasing the current value from the charge pump generator 720, selecting a larger capacitor capacitance for the loop filter 730, etc. Conversely, if spurious peaks located within the bandwidth of the contour occur due to the direct addition of spurious peaks to the VCO, then the bandwidth of the contour can be increased to reduce in-band gain from the VCO, which can then reduce the levels of spurious peaks. A large loop bandwidth can be obtained by increasing the gain of the phase-frequency detector 710, increasing the current magnitude from the charge pump generator 720, selecting a smaller capacitor capacitance for the loop filter 730, etc. A suitable loop bandwidth can be selected for each frequency channel based on spurious peaks observed for that frequency channel. The choice of loop bandwidth can be based on computer simulation, empirical measurements, field trials, etc.

FIG. 8 shows a block diagram of a divider 750a, which is an embodiment of a divider 750 in the PLL system 702 of FIG. 7. In the divider 750a, the integer divider 810 divides the VCO signal in frequency by an integer coefficient M _k , which may be 1, 2, 3, 4, etc. The divider coefficient M _k may be configurable for the frequency channel k and may be selected by the signal M_Select. A switch 812 routes the output of the divider 810 to one of T pre-dividers 814a-814t based on the P_Select signal, where T can be any integer value. Each pre-divider 814 can divide the signal from the divider 810 in frequency either by the coefficient U or by the coefficient U + 1 at any given moment, where U can be different for different preliminary dividers. For example, the preliminary divider 814a can divide by either 8 or 9 (for U ₁ = 8) and so on, and the preliminary divider 814t can divide by either 4 or 5 (for U _T = 4). The multiplexer 816 routes the pre-divided signal from the selected pre-divider 814 to the fractional divider 818. The pre-divided signal has a frequency f _PRE , which can be expressed as:

where f _VCO is the frequency of the VCO signal, and

P _k is the coefficient of the preliminary divider selected for the frequency channel k.

The VCO signal may be used by the local oscillator 760 to generate the local oscillator signal at the local oscillator frequency. The local oscillator frequency f _LO depends on the center frequency of the frequency channel k and can correspond to the frequency f _{RX_LO} for the local oscillator signal V _{RX_LO} in FIG. 3, the frequency f _{RX_LO1} for the local oscillator signal V _{RX_LO1} in FIG. 4, the frequency f _{TX_LO} for the local oscillator signal V _{TX_LO} in FIG. .5 or frequency f _{TX_LO2} for the local oscillator signal V _{TX_LO2} in FIG. 6.

The coefficient P _{k of the} pre-divider depends on the coefficients U _k and U _k +1 of the selected pre-divider, as well as on the percentage of time when each coefficient of the divider is used. For example, if the selected preliminary divider for the frequency channel k divides by the coefficient U _k +1 for V from W cycles, and divides by the coefficient U _k for the remaining WV cycles, then the coefficient of the preliminary divider can be set as P _k = U _k + V / W. The values of V and W may be fixed or may depend on the frequency channel k.

A divider 818 divides the pre-divided signal from the multiplexer 816 in frequency either into an integer coefficient N _L or an integer coefficient N _H based on the selector signal of the divider from the sigma-delta modulator 830. The divider 818 can divide for some part of the time by the coefficient N _L , and in the rest of the time - by the coefficient N _H to obtain the desired frequency for the feedback signal.

In one embodiment, the divider control unit 832 receives the selected frequency channel and determines a coefficient N _k for the divider 818, which can be expressed as:

The factor N _{k of the} divider for the frequency channel k is between the integer values N _L and N _H , or N _L ≤N _k ≤N _H. The factor N _{k of the} divider can be expressed based on the values of N _L and N _H as follows:

where Frac _k is the percentage of time to use the coefficient N _H , and (1-Frac _k ) is the percentage of time to use the coefficient N _L. The value of Frac _k can be determined as follows:

For example, if N _k = N _H , then Frac _k = 1, the coefficient N _{H is} used all the time, and the coefficient N _{L is} not used.

Block 832 control divider can receive a signal N_Select, which indicates the values of the coefficients N _L and N _H for the frequency channel k. Block 832 may determine the value of Frac _k , as shown in equation (4), and then quantize the value of Frac _k to L bits. The value of L may be selected to achieve the desired frequency resolution and may be 10, 16, 23, etc. Block 832 provides a L bit value of Frac _k sigma-delta to modulator 830.

The sigma-delta modulator 830 receives a L bit value of Frac _k and generates a divider select signal for the divider 818. In one embodiment, the divider select signal is a 1-bit control signal that instructs the divider 818 to perform division with either a factor of N _L or with coefficient N _H. For example, a low logic level ('0') in the divider selection signal may correspond to division by a factor of N _L , and a high logic level ('1') in the divider selection signal may correspond to division by a factor of N _H. The percentage of units in the divider select signal is determined using the value of Frac _k . However, the units are distributed in the divider selection signal so that the quantization noise shifts to higher frequencies, and a good phase noise characteristic for the VCO signal from the VCO 740 is achieved. FIG. 8 shows the use of the sigma-delta modulator 830 to select between factors N _L and N _H for the divider 818. The choice of the coefficient N _L or N _H for the divider 818 can also be done in other ways.

FIG. 9 shows a block diagram of a divider 750b, which is another example of a divider 750 in the PLL system 702 of FIG. 7. In the divider 750b, the switch 910 routes the VCO signal to one of the T divider circuits 912a-912t. Each chain of dividers 912 includes an integer divider 914, which divides by an integer value M a preliminary divider 916, which divides by either a coefficient U or a coefficient U + 1, and a fractional order-N divider 918, which divides either by a factor N _L or by the coefficient N _H. A multiplexer 920 provides a signal from a selected chain of 912 dividers as a feedback signal.

In one embodiment, the pre-divider coefficient P _k and the divider coefficient N _k for the frequency channel k can be jointly determined as follows:

where Z _k is the combined divider coefficient for both the preliminary divider 916 and the fractional divider 918 in the selected chain of 912 dividers for the frequency channel k. The coefficient Z _k can be between the integer values Z _L and Z _H , or Z _L ≤Z _k <Z _H. The value of Z _L can be defined as Z _L = N _L + U _k , and the value of Z _H can be defined as Z _H = N _H + U _k +1. The values of Z _L and Z _H can also be determined in other ways.

The combined divider coefficient Z _k may be expressed based on the values of Z _L and Z _H as follows:

where Frac _k is the percentage of time using the coefficient Z _H , and (1-Frac _k ) is the percentage of time using the coefficient Z _L. The value of Frac _k can be determined as follows:

The divider control unit 932 may receive a frequency channel and an N_Select signal for frequency channel k. Block 932 may determine the value of Frac _k , as shown in equation (7), and then quantize Frac _k to L bits. The sigma-delta modulator 930 can receive the Frac _k value consisting of L bits from block 930 and generate a divider select signal for both the pre-divider 916 and the divider 918 in the selected divider circuit 912.

8 and 9 show two illustrative embodiments of the divider 750. In general, the divider 750 may be implemented using various configurations having a fixed or configurable integer divider, a fixed or configurable pre-divider, and a fixed or configurable fractional order-N divider. The integer divider, pre-divider and fractional order-N divider for each frequency channel can be controlled jointly or separately.

In another aspect, a plurality of frequency equations may be determined for each supported frequency channel. When combining equations (1) - (3), the frequency equation can be expressed as:

Similarly, when combining equations (5) and (6), the frequency equation can be expressed as:

, где

- оператор нижней целой части числа, то первое частотное уравнение может быть задано с помощью коэффициентов N_L=N и N_H=N+1, второе частотное уравнение может быть задано с помощью коэффициентов N_L=N и N_H=N+2, третье частотное уравнение может быть задано с помощью коэффициентов N_L=N-1 и N_H=N+1, четвертое частотное уравнение может быть задано с помощью коэффициентов N_L=N-1 и N_H=N+2 и т.д. Как пример, если N_k=8.7 для варианта на фиг.8, то N=8, и первое частотное уравнение может быть задано с помощью делителя 818, выполняющего деление на 8 или 9, второе частотное уравнение может быть задано с помощью делителя 818, выполняющего деление либо на 8, либо на 10, третье частотное уравнение может быть задано с помощью делителя 818, выполняющего деление либо на 7, либо на 10, и четвертое частотное уравнение может быть задано с помощью делителя 818, выполняющего деление либо на 7, либо на 11. В общем случае разные частотные уравнения могут быть заданы для разных значений разности между значениями N_L и N_H или Δ=N_H-N_L, где согласно описанному выше варианту Δ = 1, 2, 3 и 4. Для каждого частотного уравнения процент времени деления на N_L и процент времени деления на N_H определяется посредством значения Frac_k, которое зависит от отношения коэффициента N_k делителя, а также от значений N_L и N_H. Значения N_L и N_H для выбранного частотного канала могут быть обозначены посредством сигнала N_Select, который может быть выдан блоку 832 и делителю 818.The set of frequency equations can be determined for each frequency channel using different sets of values for the coefficients N _L and N _H in equation (8), or different sets of values for the coefficients Z _L and Z _H in equation (9). In one embodiment, if N =

where

is the operator of the lower integer part of the number, then the first frequency equation can be set using the coefficients N _L = N and N _H = N + 1, the second frequency equation can be set using the coefficients N _L = N and N _H = N + 2, the third frequency equation can be set using the coefficients N _L = N-1 and N _H = N + 1, the fourth frequency equation can be set using the coefficients N _L = N-1 and N _H = N + 2, etc. As an example, if N _k = 8.7 for the embodiment of FIG. 8, then N = 8, and the first frequency equation can be defined using a divider 818 divided by 8 or 9, the second frequency equation can be set using a divider 818, performing division by either 8 or 10, the third frequency equation can be set using a divider 818, performing division by either 7 or 10, and the fourth frequency equation can be set using a divider 818, performing division by either 7, or by 11. In the general case, different frequency equations can be given for the known values of the difference between the values of N _L and N _H or Δ = N _H -N _L , where, according to the above option, Δ = 1, 2, 3 and 4. For each frequency equation, the percentage of division time by N _L and the percentage of division time by N _{H is} determined by the value of Frac _k , which depends on the ratio of the factor N _{k of the} divider, as well as on the values of N _L and N _H. The values of N _L and N _H for the selected frequency channel can be indicated by the signal N_Select, which can be issued to block 832 and divider 818.

In another embodiment, the sigma-delta modulator 830 or 930 receives the Frac _k value of L bits from the divider control unit 832 or 932 and generates a divider selection signal of Q bits for the divider 818 or 918, where Q can be any integer value greater than one . A divider 818 or 918 can divide the pre-divided signal into one of 2 ^Q possible integer divider coefficients, as determined by a divider selection signal consisting of Q bits. Different frequency equations can be defined for different values of Q. Different frequency equations can also be determined in other ways.

Different frequency equations may provide different performance with respect to spurious peaks. In one embodiment, a single frequency equation (e.g., with Δ = 1) can be used as the default frequency equation. For each frequency channel that detects excessive degradation due to spurious peaks at the default frequency equation, each of the other frequency equations can be estimated. For the frequency channel, a frequency equation can be selected that provides the best performance with respect to spurious peaks and possibly based on other factors. The performance can be quantified by various indicators, such as signal-to-noise ratio (SNR), error vector amplitude (EVM), bit error rate (BER), packet error rate (PER), etc. The EVM is an indication of the amplitude and phase errors of the modulation symbols due to errors in the transmitted local oscillator signal, and errors can occur due to spurious peaks. In general, the phase noise of the local oscillator signal may be worse for large Δ values at some bias frequencies, but an improvement due to the reduction of spurious peaks can more than offset the deterioration in phase noise and can improve performance.

In yet another aspect, different frequency division schemes may be available, and a suitable frequency division scheme may be selected for each frequency channel. The frequency division circuit includes a specific value for each divider coefficient used to divide the VCO signal in frequency. In the embodiments shown in FIGS. 8 and 9, the overall divider coefficient R _k for the frequency channel k can be expressed as:

The frequency division scheme is set by means of a specific value for each of the coefficients M _k , P _k and N _{k of the} divider. Different frequency division schemes can be specified using different sets of values for the coefficients M _k , P _k and N _k for a given value of R _k . In one embodiment, T different frequency division schemes may be set using T coefficients P ₁ -P _{T of the} pre-divider. The coefficient N _k can be appropriately changed for each coefficient of the preliminary divider. As an example, for a given frequency f _VCO VCO, the coefficients of the preliminary divider 8/9 and 4/5 lead to different frequencies f _{PRE of the} signal with preliminary division, which, in turn, lead to different coefficients N _{k of the} divider. In another embodiment, different frequency division schemes may be defined using different coefficients M _{k of} an integer divider. A larger value of M _k leads to the fact that the selected pre-divider operates at a lower frequency, which can save power. In the general case, different frequency division schemes can be defined for the frequency channel k using different values of P _k and / or different values of M _k . For each set of values of P _k and M _{k, the} values of N _k can be selected to obtain the desired common divider coefficient R _k for the frequency channel k.

Different frequency division schemes may have different spurious peaks and / or different levels of spurious peaks. A frequency division circuit may be selected for each frequency channel to achieve good performance for that frequency channel. In one embodiment, a set of default values may be used for the coefficients P _k and M _k . For each frequency channel detecting excessive degradation due to spurious peaks at a default set of values for the coefficients P _k and M _k , other possible sets of values for the coefficients P _k and M _k can be estimated. For the frequency channel, a frequency division circuit can be selected that provides good performance (for example, the lowest levels of spurious peaks).

In yet another aspect, either a higher frequency oscillator signal or a lower frequency local oscillator signal may be used to prevent spurious peaks for frequency conversion in a superheterodyne receiver or transmitter. For the superheterodyne receiver 220y of FIG. 4, the received signal can be downconverted from the radio frequency to the intermediate frequency by a mixer 414 using the local oscillator signal V _{RX_LO1} . The frequency of this local oscillator signal will be higher than that of the selected frequency channel to adjust the signal amplitude in the upper part, and lower than that of the selected frequency channel to adjust the signal amplitude in the lower part. The frequency of the local oscillator signal to adjust the amplitude of the signal in the upper or lower part can be expressed as:

where f _IF is the intermediate frequency,

f _CH is the center frequency of the selected frequency channel,

f _{RX_LO1_HS} is the local oscillator frequency for adjusting the amplitude of the signal in the upper part, and

f _{RX_LO1_LS} - local oscillator frequency for adjusting the signal amplitude in the lower part.

The local oscillator signals in the upper and lower parts (in frequency) can be obtained by selecting the appropriate values for the total divider coefficient R _k . For each frequency channel, the levels of spurious peaks with the local oscillator signal in the upper part can be compared with the levels of spurious peaks with the local oscillator signal in the lower part. And for the frequency channel, a local oscillator signal with lower levels of spurious peaks can be selected.

In yet another aspect, different supply voltages for the VCO 740, divider 750, and / or other blocks of the PLL system 700 can be used to suppress the negative effects of spurious peaks. The VCO 740 can operate at one of many possible supply voltages, such as 1.8 V, 2.0 V, 2.2 V, etc. A low supply voltage can save power, while a high supply voltage can increase the VCO signal span. The system may have strict technical requirements at certain offset frequencies, for example 400 kHz and 1.8 MHz for the GSM system. When large spurious peaks are located far from the PLL loop bandwidth, adjusting the PLL loop bandwidth can have a critical effect. Instead, increasing the supply voltage for the VCO 740 can increase the span of the VCO signal, which can then sharpen the transition edges of the VCO signal and reduce the effects caused by spurious peaks. A higher VCO supply voltage can be used if necessary, for example, when stray peaks of a sufficiently high level are located within frequency ranges with strict technical requirements. A lower VCO supply voltage can be used in other scenarios to save power. In general, the span of a VCO signal can be adjusted by adjusting the VCO supply voltage, VCO bias current, a resistor in a bias circuit with a fixed VCO supply voltage, etc. or through any combination of these adjustments.

All or part of the divider 750 may operate on one of the many possible supply voltages. An integer divider, pre-divider, fractional order-N divider, sigma-delta modulator and / or divider control unit may be sources of large spurious peaks. For each block that can be the source of large spurious peaks, one can control the supply voltage to reduce the spurious peaks generated by this block. Variable supply voltages can be applied to an integer divider, pre-divider, fractional order-N divider, sigma-delta modulator, divider control unit, or to any combination thereof. Variable supply voltages may depend on the selected frequency channel.

10 shows an embodiment of a PLL system tuning table 1000 for different frequency channels with non-uniform frequency programming. Table 1000 may be configured for all frequency channels supported by wireless device 110, and may include one entry or row for each supported frequency channel. The frequency channel can be designed for downlink (receiver) or for uplink (transmitter), depending on the specific system. Table 1000 may also include columns for various settings of the PLL system, which may be intended for circuit blocks in the PLL system, as well as circuit blocks (eg, VCO) external to the PLL system. In the embodiment shown in FIG. 10, table 100 includes one column for the PLL loop bandwidth, one column for the frequency equation (e.g., N _L and N _H coefficients, as shown in Table 1000, or Z _L and Z _H coefficients divider), one column for the frequency division circuit (for example, the divider coefficients M _k and P _k ), one column for indicating the amplitude adjustment of the signal at the top or bottom, one column for the total divider coefficient R _k and one column for the VCO supply voltage. For each frequency channel in each column, a suitable value for the parameter (s) can be selected to achieve good performance for that frequency channel. For each frequency channel, the desired PLL loop bandwidth can be obtained via the PDF_Control signal for the phase detector 710, the CP_Control signal for the charge pump generator 720 and / or the LF_Control signal for the loop filter 730.

For each frequency channel, the overall divider factor R _k may be selected to obtain the desired local oscillator frequency. For a superheterodyne receiver or transmitter, the coefficient R _k can also be selected based on whether the local oscillator amplitude control is selected at the top or bottom for the frequency channel. For each frequency channel, the coefficients N _L and N _H (or Z _L and Z _H ) of the dividers can be obtained based on the frequency equation selected for this frequency channel from among all available frequency equations. For each frequency channel, the coefficients P _k and / or M _{k of the} dividers can be obtained based on the frequency division scheme selected for this frequency channel from among all available frequency division schemes. The values of N _L , N _H , P _k and M _k can be provided to the divider 750 through the signal Divider_Control. For each frequency channel, the VCO supply voltage can be selected from the set of available supply voltages, and the selected supply voltage can be indicated by the VR_Control signal.

Figure 10 shows a variant of a table that can be used to store PLL settings for different frequency channels with non-uniform frequency programming. A column with a lower or higher local oscillator frequency and a column with a common divisor coefficient may be omitted, since the information in these columns can be included in the coefficients N _L , N _H , P _k and M _k . In general, the PLL system settings for the supported frequency channels can also be stored using any data structure.

11 shows an embodiment of a process 1100 for generating a waveform generator signal, such as a VCO signal. The frequency channel may be selected from a plurality of frequency channels (block 1112). Each frequency channel may be associated with a set of PLL settings for at least one parameter in addition to the overall divider coefficient R _k , which may, by its nature, be different for different frequency channels. The plurality of frequency channels may correspond to at least two different sets of PLL settings. The set of PLL settings for the selected frequency channel can be determined, for example, from a frequency programming table, such as table 1000 in FIG. 10 (step 1114). The signal of the oscillation generator for the selected frequency channel can be generated based on the set of PLL settings (step 1116).

The PLL system settings for the selected frequency channel may include a setting that selects one of the many PLL loop bandwidth ranges. One or more blocks in the PLL system can be tuned to achieve a certain PLL loop bandwidth for the selected frequency channel. The set of PLL settings for the selected frequency channel may include a setting that selects one of the many current values of the charge pump generator. The control signal for VCO can be generated based on the current value of the charge pump generator for the selected frequency channel.

The set of PLL settings for the selected frequency channel may include a divider setting that selects one of the many frequency equations that different sets of high and low divider coefficients can correspond to. The divider can be programmed using a set of high and low divider coefficients for the selected frequency channel. The divider can then divide the frequency generator signal based on this set of high and low divider coefficients.

The PLL system settings for the selected frequency channel may include a frequency division setting that selects one of the many frequency division schemes for dividing the signal of the oscillation generator by frequency. Many frequency division schemes may correspond to different coefficients of the preliminary divider, different coefficients of the integer divider, etc. The signal of the oscillation generator can be divided by frequency based on the coefficient of the preliminary divider and / or the coefficient of the integer divider for the selected frequency channel.

The set of PLL settings for the selected frequency channel may include a setting that selects the adjustment of the signal amplitude at either the top or bottom for the local oscillator signal, which can be generated based on the signal from the oscillation generator. The local oscillator signal can be generated at a frequency higher than that of the selected frequency channel if the signal amplitude control at the top is selected, or at a frequency lower than that of the selected frequency channel if the signal amplitude control at the bottom is selected.

The set of PLL settings for the selected frequency channel may contain a setting that selects one of the many supply voltages for the circuit block, such as VCO, divider, etc. The supply voltage selected for the selected frequency channel can be generated and applied to some block of the circuit. The set of PLL settings for the selected frequency channel may include a setting for controlling the bias current for the block circuit. The bias current control selected for the selected frequency channel can be generated and applied to the block circuit. In general, tuning a PLL system may select one of a plurality of bias circuits for a circuit block, and a plurality of bias circuits may correspond to different supply voltages and / or different bias currents for the circuit block.

There may also be sets of PLL settings for other and / or additional parameters for multiple frequency channels.

The methods described here for generating an oscillator signal may provide some advantages. Firstly, when using different settings of the PLL system for different frequency channels, negative effects caused by spurious peaks can be suppressed, and a good performance characteristic for each frequency channel can be achieved. Secondly, these methods can allow the integration of digital and analog circuits on the same IC chip, which can reduce the cost, size of devices, etc.

In another aspect, non-uniform frequency programming can be used to control the operation of transmitters and / or receivers in wireless device 110. Various parameters of the transmitter or receiver can be controlled based on the selected frequency channel. For the receiver, the bias current and / or gain of the LNA amplifier, the bias and / or gain of the mixer, the filter bandwidth, the gain in the VGA amplifier, etc. can be set based on the selected frequency channel. For the transmitter, bias current and / or amplifier gain PA, bias current and / or mixer gain, filter bandwidth, VGA amplifier gain, etc. can be set based on the selected frequency channel. In non-uniform programming for blocks in the transmitter or receiver, different settings can be used for different frequency channels of frequencies. A suitable set of transceiver settings can be selected for each frequency channel to achieve good performance for that frequency channel. Thus, each frequency channel may correspond to a set of transceiver settings for at least one parameter in the transmitter or receiver, in addition to the overall divider coefficient R _k . At least two different sets of transceiver settings can correspond to different frequency channels. The transceiver settings set for the selected frequency channel can be applied to the transmitter or receiver.

The methods described here can be implemented by various means. For example, the methods may be implemented in hardware, firmware, software, or through a combination thereof. For implementation using hardware, the various blocks described herein may be implemented on one or more specialized integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), programmable gate arrays (FPGA), processors, controllers, microcontrollers, microprocessors, electronic devices and other electronic units configured to perform the functions described here, as well as using a computer Or based on any combination of the foregoing.

The circuits described here (for example, frequency synthesizers 270 and 700, local oscillators 272 and 760, PLL system 702, etc.) can be implemented on an integrated circuit (IC; IC), radio frequency integrated circuit (RFIC), analog-to-digital IC , specialized integrated circuit (ASIC), printed circuit board (PCB), etc. Circuits can also be fabricated using various IC processing technologies such as complementary metal oxide semiconductors (CMOS; CMOS), n-channel metal oxide semiconductors (N-MOS), p-channel metal oxide semiconductors (P-MOS), bipolar junction transistors (BJT ), bipolar complementary metal oxide semiconductors (BiCMOS), silicon-germanium alloy (SiGe), gallium arsenide (GaAs), etc.

Some aspects of the methods can be implemented using firmware and / or software (for example, modules, such as procedures, functions, etc.) that performs the functions described herein. The instructions / codes of the firmware and / or software may be stored in a memory (for example, such as a memory 262 in FIG. 2) and executed by a microprocessor (for example, a microprocessor 260). The memory may be implemented in a microprocessor or external to the microprocessor in a manner. Commands / code of firmware and / or software can also be stored on a computer / processor-readable medium such as random access memory (RAM), read-only memory (ROM), non-volatile random access memory (NVRAM) , programmable read-only memory (EPROM; PROM), electrically erasable programmable read-only memory (EEPROM; EEPROM), flash memory, floppy disk, compact disk (CD), digital universal disk (DVD), magnetic or optical storage device, etc. Commands / code may be executed by one or more processors and may prompt (instruct) the processor (s) to execute certain aspects of the functions or functionality described herein.

A device implementing the methods described herein may be a standalone device or may be part of a larger device. The device may be (i) a stand-alone integrated circuit (IC; IC), (ii) a set of one or more ICs, which may include memory ICs for storing data and / or commands, (iii) a radio frequency IC (RFIC), such as a radio frequency receiver (RFR) or radio frequency transmitter / receiver (RTR), (iv) a specialized integrated circuit (ASIC), such as a mobile station modem (MSM), (v) a module that can be integrated into other devices, (vi ) receiver, cell phone, wireless device, portable telephone or mobile unit (vii), etc.

The foregoing description of the disclosure of the invention is given to enable a person skilled in the art to make or use the disclosure of the invention. Various modifications to this disclosure may be understood by those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited by the examples and schemes described herein, but should receive the broadest scope consistent with the principles and new features disclosed herein.

Claims (26)

1. A wireless communication device, comprising:
a phase locked loop (PLL) system used to generate an oscillator signal for a frequency channel selected from a first frequency channel and a second frequency channel, with each frequency channel having a set of PLL settings for at least one parameter in addition to the overall divider factor , and the first and second frequency channels correspond to at least two different sets of PLL settings, and the PLL system works on the basis of the system settings we are PLL for the selected frequency channel; and
a memory containing at least two different sets of PLL settings, containing the first set of PLL settings, which leads to lower spurious peaks in the first frequency channel than the second set of PLL settings, and a second set of PLL settings, which leads to lower levels of spurious peaks in the second frequency channel than the first set of PLL settings, and the implementation of the first set of PLL settings instead of the second set of PLL settings leads to the use of at least one th of different frequency equations, different frequency dividing circuits on the high side injection for a super-heterodyne architecture and supply voltages for different units within the integrated circuit. 2. The wireless communication device according to claim 1, in which the set of PLL settings for the selected frequency channel contains a setting that selects one of the many values of the PLL loop bandwidth. 3. The wireless communications apparatus of claim 1, wherein the PLL system comprises a charge pump generator, wherein the set of PLL systems for the selected frequency channel comprises a setting that selects one of a plurality of different current values of the charge pump generator. 4. The wireless communication device according to claim 1, wherein the set of PLL settings for the selected frequency channel comprises a divider setting that selects one of the many frequency equations for dividing the signal of the oscillation generator by frequency. 5. The wireless communications apparatus of claim 4, wherein the plurality of frequency equations correspond to different sets of high and low divider coefficients, wherein the divider setting indicates a predetermined set of high and low divider coefficients for dividing the oscillator signal by frequency. 6. The wireless communications apparatus of claim 1, wherein the set of PLL settings for the selected frequency channel comprises a frequency division setting that selects one of a plurality of frequency division schemes for dividing the signal of the oscillation generator in frequency. 7. The wireless communications apparatus of claim 6, wherein the plurality of frequency division circuits correspond to different coefficients of the preliminary divider, wherein the frequency division setting indicates a predetermined coefficient of the preliminary divider to divide the frequency oscillator signal. 8. The wireless communications apparatus of claim 6, wherein the plurality of frequency division circuits correspond to different coefficients of an integer divider, wherein the frequency division setting indicates a predetermined coefficient of an integer divider to divide the frequency generator signal. 9. The wireless communications apparatus of claim 1, wherein the set of PLL settings for the selected frequency channel comprises a setting that selects injection on the high or low side for the local oscillator (LO) signal generated from the oscillator signal, the local oscillator signal having a frequency higher than than the selected frequency channel for injection on the high side, and lower than the selected frequency channel for injection on the low side. 10. The wireless communication device according to claim 1, in which the set of PLL settings for the selected frequency channel contains a setting that selects one of the many bias circuits for the oscillator used to generate the signal of the oscillator, and the multiple bias circuits correspond to different supply voltages and / or different bias currents for the oscillation generator. 11. The wireless communications apparatus of claim 1, further comprising:
memory for storing the PLL system settings table for a plurality of frequency channels. 12. The wireless communications apparatus of claim 1, wherein the plurality of frequency channels comprises at least one of a plurality of code division multiple access (CDMA) channels and a plurality of channels of a global mobile communication system (GSM). 13. A phase locked loop device comprising:
a phase-frequency detector for receiving a reference signal and a feedback signal and outputting a detector signal showing a phase difference between the reference signal and the feedback signal;
a charge pump generator for generating an error signal based on a detector signal;
loop filter for filtering the error signal and issuing a control signal for the oscillation generator; and
a divider for receiving a signal of the oscillation generator from the oscillation generator, dividing the signal of the oscillation generator in frequency and providing a feedback signal, wherein at least one of the charge pump generator, the loop filter and the divider has many settings for a parameter other than the overall divider coefficient, and settings can be selected for each of the many frequency channels and contains the first set of settings, which leads to lower levels of spurious peaks in the first frequency channel than the second the first PLL system settings, and the second PLL system settings, which leads to lower spurious peaks in the second frequency channel than the first PLL system settings, and many settings lead to the use of at least one of different frequency equations, different schemes frequency division, high side injection for superheterodyne architecture and different supply voltages for blocks in an integrated circuit. 14. The phase-locked loop device of claim 13, wherein the divider comprises a fractional order-N divider having multiple settings for different sets of high and low divider coefficients used to divide the frequency generator signal. 15. The phase locked loop device according to claim 13, wherein the divider has a plurality of settings for a plurality of pre-dividers and in which one of the plurality of pre-dividers is selected for each frequency channel to divide the oscillator signal by frequency. 16. The phase locked loop according to claim 13, wherein the divider comprises an integer divider having a plurality of settings for different coefficients of the integer divider used to divide the frequency generator signal. 17. The phase-locked loop device according to item 13, in which the charge pump generator has many settings for different current values of the charge pump generator. 18. A method of generating a signal of an oscillation generator, comprising the steps of:
a frequency channel is selected from a plurality of frequency channels, and each frequency channel corresponds to a set of phase locked loop (PLL) settings for at least one parameter in addition to the overall divider factor, while at least two different sets of system settings correspond to a plurality of frequency channels PLL;
define a set of PLL settings to reduce spurious peak levels for the selected frequency channel;
implement a certain set of PLL system parameters, and the implementation of a certain set of PLL system parameters leads to the use of at least one of different frequency equations, different frequency division circuits, high-side injection for a superheterodyne architecture and different supply voltages for blocks in an integrated circuit; and
generating an oscillator signal for the selected frequency channel based on the aforementioned set of PLL settings. 19. The method according to p, in which the set of PLL settings for the selected frequency channel contains a setting that selects one of the many sets of high and low divider coefficients, and generating an oscillator signal for the selected frequency channel comprises the steps of:
program the divider using a set of high and low divider coefficients for the selected frequency channel and
divide the oscillator signal in frequency based on the said set of high and low divider coefficients. 20. The method according to p, in which the set of PLL settings for the selected frequency channel contains a setting that selects one of the many coefficients of the preliminary divider, and generating a signal of the oscillator for the selected frequency channel comprises the step of dividing the signal of the oscillator in frequency by based on the pre-divider coefficient for the selected frequency channel. 21. The method according to p, in which the set of PLL settings for the selected frequency channel contains a setting that selects the injection on the high or low side, and generating a signal of the oscillation generator for the selected frequency channel contains the steps in which:
generating an oscillator signal to obtain a local oscillator signal with a frequency higher than that of the selected frequency channel, if injection on the high side is selected for the selected frequency channel, and
form the signal of the oscillation generator to obtain a local oscillator signal with a frequency lower than that of the selected frequency channel, if injection is selected on the low side. 22. The method according to p. 18, in which the set of PLL settings for the selected frequency channel contains a setting that selects one of the many different values of the current of the charge pump generator, and generating a signal of the oscillation generator for the selected frequency channel comprises the step of generating a control signal for an oscillator based on the current value of the charge pump generator for the selected frequency channel, while the oscillator generates this signal from the oscillator. 23. The method according to p, in which the set of PLL settings for the selected frequency channel contains a setting that selects one of the many supply voltages for the oscillation generator used to generate the signal of the oscillation generator, the method further comprising the step of:
apply the supply voltage selected for the selected frequency channel to the oscillation generator. 24. A wireless communication device, comprising:
means for selecting a frequency channel from a plurality of frequency channels, wherein each frequency channel corresponds to a set of phase locked loop (PLL) settings for at least one parameter in addition to the overall divider coefficient, selected to suppress the effects of spurious peaks, while the plurality of frequency channels correspond to at least two different sets of PLL settings;
means for selecting a set of PLL settings to reduce spurious peak levels for a selected frequency channel;
means for implementing the selected set of PLL system parameters, the implementation of the selected set of PLL system parameters leading to the use of at least one of different frequency equations, different frequency division schemes, high-side injection for a superheterodyne architecture and different supply voltages for units in an integrated circuit; and
means for generating a signal of the oscillation generator for the selected frequency channel based on said set of PLL settings. 25. A wireless communications device, comprising:
a controller configured to determine a frequency channel selected from a plurality of frequency channels, determine a set of transceiver settings to lower spurious peaks for a selected frequency channel, and apply a set of transceiver settings for a selected frequency channel to a transmitter or receiver, and each frequency channel has a set transceiver settings for at least one parameter in the transmitter or receiver in addition to the overall divider factor, and a plurality At least two different sets of transceiver settings correspond to these channels, while the implementation of the said one set of transceiver parameters instead of the other set leads to the use of at least one of different frequency equations, different frequency division schemes, high-side injection for a superheterodyne architecture and different voltages power supply for blocks in an integrated circuit. 26. A computer-readable read-only medium containing instructions stored on it that are configured to, when executed by a processor, cause the processor to perform operations to generate a waveform generator, said operations comprising:
selecting a frequency channel from a plurality of frequency channels, wherein each frequency channel corresponds to a set of phase locked loop (PLL) settings for at least one parameter in addition to the overall divider coefficient, and at least two different sets of PLL settings correspond to a plurality of frequency channels ;
definition of a set of PLL settings to reduce spurious peak levels for a selected frequency channel;
the implementation of a certain set of PLL system parameters, moreover, the implementation of a certain set of PLL system parameters leads to the use of at least one of different frequency equations, different frequency division circuits, high side injection for a superheterodyne architecture and different supply voltages for blocks in an integrated circuit; and
generating a signal of the oscillation generator for the selected frequency channel based on the said set of PLL settings.

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