RU2451997C1 - Special-purpose processor for solving task of searching for shortest path between objects on plane - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: special-purpose processor for solving the task of searching for the shortest path between objects on a plane has a parallel-series circuit for connecting processors-accelerators on eight orthogonal and diagonal connections in form of a homogeneous flat array. Each processor-accelerator is connected with eight neighbouring two-way connections for transmitting and receiving signals, and has a clock generator with true and complementary outputs, an octal register (FDCPE), two AND circuits (AND2B1 and AND2) and one OR circuit (OR2), wherein the orthogonal connections of registers of each processor-accelerator are connected to neighbouring processors-accelerators through BUFE1 switches, and the diagonal connections of registers of each processor-accelerator are connected to neighbouring processors-accelerators through BUFE2 switches.

EFFECT: faster operation.

5 dwg

Description

The special processor (SPKP) is designed to create a 2D model for placing objects on a plane and solve the problem of finding the shortest path on this model using accelerator processors. SPKP can be used in various networks when laying routes, tracing connections between elements on printed circuit boards and integrated circuits, etc.

Currently, examples of the use of specialized accelerator processors for solving problems associated with the visualization of graphical information are known. For example, the Roadrunner (IBM) supercomputer contains 32,000 processors, of which 16,000 are video accelerators that were previously developed for the Playstation-3 game console (http://en.wikipedia.org/wiki/RSX).

Such special processors allow, in the particular case, as well as in the claimed device, to create 2D models for placing objects on the plane, however, due to the solution of more complex tasks related to visualization, these special processors turn out to be more difficult to implement and, in addition, not solve the problem of determining the shortest path between objects on the plane.

The objective of the present invention is to expand the arsenal of technical means aimed at creating a 2D model for placing objects on a plane and solving the problem of finding the shortest path on this model.

The technical result of the invention is that it has fewer equipment with higher speed and can be used in systems for automatically tracing connections on printed circuit boards.

The technical result is achieved by the fact that the special processor for solving the problem of finding the shortest path between objects on the plane contains a parallel-serial connection diagram along eight orthogonal and diagonal connections of processor accelerators in the form of a uniform flat matrix in which each processor accelerator implements the functions of fixing the start point or the end of the path, storing information about the presence of an obstacle, about the direction number of the input signals, calculating the direction numbers of the input signals of neighboring processors - speakers and transferring them from the start point of the path to the end point, with each processor-accelerator connected to eight adjacent bidirectional links for transmitting and receiving signals corresponding to the number of the direction of their propagation, and contains a clock generator with direct and inverse outputs, eight-bit register (FDCPE ), two AND circuits (AND2B1 and AND2) and one OR circuit (OR2), moreover, the orthogonal register registers of each processor-accelerator are connected to neighboring processor-accelerators through the BUFE1 keys controlled by the direct clock output about the generator, and the diagonal connections of the registers of each processor-accelerator are connected to the neighboring ones via BUFE2 keys controlled by the inverse output of the clock generator, which makes it possible to distinguish the length of orthogonal connections in the search for the shortest path from the length of the diagonal connections.

SPKP is executed on integrated circuits (XC95288XL pleats of the Vertex 4 series of Xilinx firm).

Figure 1 presents the structural diagram of the matrix M.

Figure 2 - cell matrix of the special processor.

Figure 3 is a schematic diagram of a memory cell.

Figure 4 - schematic diagram of the connections (SS) cells of the model of the trace field.

Figure 5 is a schematic diagram of the control cell.

The structure of the SPKP contains three main blocks: a homogeneous matrix M of cells of the tracing field model, a connection diagram (CC) between the cells of the matrix M, and a control unit (CU).

For simplicity, the image in figure 1 presents an example from a matrix of 5 × 5 cells of the model of the trace field. Each cell of the matrix is numbered from the outside. The cells in the matrix are interconnected in eight directions: north (0), northeast (1), east (2), southeast (3), south (4), southwest (5), west (6) , northwest (7). The connections between the cells (indicated by arrows in the drawing) show the directions for calculating the shortest path. In this case, for example, the indices C denote the cell of the beginning of the route, D - the end of the route, p - obstacle.

The general principle of calculating the weights of the vertices resembles the process of propagating the wave front from point C to point D. In Fig. 1, the front of each wave corresponds to one line of the “algorithm step” and is marked with numbers inside the matrix cells. The calculations end at the (n-1) -th step, when the wave front reaches the peak D.

The functionality of the cell I / O ports is as follows:

СОМ0-СОМ7 - bidirectional communication ports of cells of the trace field with each other.

DATA (7: 0) - data bus. A bi-directional 8-bit bus designed to interrogate and configure the device.

C is a clock signal.

RST - circuit reset signal.

CS - cell selection signal for read / write operations.

WR - a signal of permission to write data to the cell registers. When this signal is applied to the CS pair, the value present on the DATA data bus (7: 0) is recorded in the cell registers.

RD is a permission signal for reading data from a cell. When this signal is applied to the CS pair on the DATA data bus (7: 0), the value stored in the cell registers is set.

The matrix of the special processor matrix consists of three main parts:

- memory cells;

- Interfacing schemes with neighboring cells;

- control schemes.

The schematic diagram of a memory cell (Fig. 3) contains: 8-bit register (FDCPE), two AND circuits (AND2B1 and AND2) and one OR circuit (OR2). The register stores information about the direction number of the wave propagation signal that came to this cell.

The functionality of the I / O signals is as follows:

D (X) is the data bus. The 8-bit bus is designed to transfer information to the register from neighboring cells through AND circuits using the INT_WR pulse.

INT_WR - internal recording signal for the cell, formed from the signals WR and CS.

RST - reset the circuit, resetting all registers.

Q (X) - cell register outputs. Connected to data bus and control circuit.

NACT (not activated) - has a value of "1" at the time of writing information to the register. It is formed by a control circuit.

Figure 4 presents a schematic diagram of the connections (SS) cells of the model trace field. It contains the left and right parts of the circuit, each of which contains four AND circuits (AND2B1) and four buffers with enable input (BUFE) for organizing bidirectional data transmission on the lines СОМ0-СОМ7. The difference between these parts of the circuit are the NCLK signals coming to the left, and the CLK signals coming to the right. These are mutually inverse signals generated from the same control pulse C, which makes it possible to distinguish between the length of the orthogonal joints in the path and the length of the diagonal joints. The functionality of the I / O signals in the wiring diagram is as follows:

COM0, COM2, COM4, COM6 - orthogonal interconnections of adjacent cells;

COM1, COM3, COM5, COM7 - diagonal interconnections of adjacent cells;

Q (0) -Q (7) - cell register outputs;

CLK, NCLK - internal mutually inverse clock signals.

Schematic diagram of the control cell is presented in figure 5. It contains: two AND circuits (AND2), two groups of buffers with enable input (BUFE8) for organizing a bi-directional DATA data bus (7: 0), OR circuit (OR8), one key (BUF) and two NOT circuits (INV).

The SPKP special processor, in comparison with the known ones, has fewer equipment with higher speed and can be used in systems for automatically tracing connections on printed circuit boards.

Claims (1)

A special processor for solving the problem of finding the shortest path between objects on a plane, characterized in that it contains a parallel-serial connection diagram along eight orthogonal and diagonal connections of the accelerator processors in the form of a uniform flat matrix in which each accelerator processor implements the functions of fixing the start or end point ways, storing information about the presence of an obstacle, about the direction number of the input signals, calculating the direction numbers of the input signals of adjacent accelerator processors and transmitting them from the start point of the path to the end point, with each processor-accelerator connected to eight neighboring bidirectional communications for transmitting and receiving signals corresponding to the number of their propagation direction, and contains a clock generator with direct and inverse outputs, eight-bit register (FDCPE), two AND circuits (AND2B1 and AND2) and one OR circuit (OR2), and the orthogonal register registers of each processor-accelerator are connected to neighboring processor-accelerators through the BUFE1 keys controlled by the direct output of the clock generator, and iagonalnye communication registers of each processor connected to the accelerator through BUFE2 adjacent keys operated inverted output clock generator, which makes it possible to distinguish between the length of the orthogonal connections to find the shortest path from the length of diagonal joints.

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