RU2446455C1 - Apparatus for estimating mean-square deviation of discrete signal - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: apparatus has two digital comparators and two bidirectional counters, where the second input of the second digital comparator is a code corresponding to the constant [0.68·N], where N is the number of readings in a sample, the output of the second digital comparator is connected to the counting direction control input of the second bidirectional counter.

EFFECT: high accuracy of estimating mean-square deviation of a discrete signal.

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Description

The invention relates to specialized means of computer technology and can be used in systems that require hardware-based implementation of algorithms for estimating the standard deviation of discrete signals, for example, when evaluating noise levels and threshold detection.

по формуле:Known algorithm for calculating sample standard deviation

according to the formula:

- среднее арифметическое по выборке, N - количество отсчетов в выборке [1]. Данный алгоритм используется, например, в цифровом устройстве квантования видеосигнала на фоне комбинированной помехи [2]. Он содержит ресурсоемкие для аппаратной реализации операции умножения, деления и вычисления квадратного корня. Для вычисления квадратного корня существует несколько известных алгоритмов, например итерационная формула Герона [3], однако она требует использования операции деления на каждом шаге алгоритма. Наиболее простым для аппаратной реализации является целочисленный алгоритм извлечения квадратного корня, основанный на подсчете суммы арифметической прогрессии нечетных натуральных чисел [4].where x _i - digital samples of the input signal,

is the arithmetic average of the sample, N is the number of samples in the sample [1]. This algorithm is used, for example, in a digital device for quantizing a video signal against a background of combined noise [2]. It contains hardware-intensive operations for multiplying, dividing, and calculating the square root. There are several well-known algorithms for calculating the square root, for example, the Heron iterative formula [3], however, it requires the use of the division operation at each step of the algorithm. The simplest for hardware implementation is an integer square root algorithm based on the calculation of the sum of the arithmetic progression of odd natural numbers [4].

In addition to significant hardware costs, a drawback of a device that implements algorithm (1) is the bias of the estimate of the standard deviation under the influence of random pulsed interference.

The closest technical solution to the proposed device scheme for estimating the standard deviation of a discrete signal is a device that includes a comparator and two reversible counters. This device is designed to estimate the median of a discrete signal [5].

The objective of the invention is to increase the accuracy of estimating the standard deviation compared to a quantization device for a video signal against a background of combined interference, while maintaining the circuitry simplicity of the prototype device.

The problem is solved due to the fact that the device for estimating the standard deviation contains two digital comparators and two reversible counters, while the first clock signal is connected to the clock input of the first reversing counter, and the second clock signal is connected to the clock input of the second reversing counter and with the preset input the first reverse counter, the input signal bus is connected to the first code input of the first digital comparator, the output signal bus is connected to the code you the second reversible counter and the second code input of the first digital comparator, the output of the first digital comparator is connected to the control input direction of the counting of the first counter, the first input of the second digital comparator is connected to the code output of the first reversible counter, and the second input of the second digital comparator is a code corresponding to the constant [ 0.68 · N], the output of the second digital comparator is connected to the input of the direction control of the account of the second reversible counter.

The introduction of the second comparator in the device [5] allows you to implement the following evaluation algorithm:

,

,

, i=0,1,2… Состоятельность оценки следует из свойств нормального распределения:where x _i - samples of the amplitude of the input signal,

, i = 0,1,2 ... Consistency of the estimate follows from the properties of the normal distribution:

where μ and σ are the true values of the mean and standard deviation.

The proposed device uses the discrete distribution property to estimate the standard deviation, that the sum of the probabilities of all events in the distribution is unity, as well as the calculated standard deviation for the standard normal distribution. The device [2] uses the signal amplitude values to estimate the standard deviation, because of this the error of the estimate increases significantly when there is pulsed noise in the signal. The introduction of the second comparator into the prototype device allows you to get a consistent estimate of the standard deviation in accordance with algorithm (2), without using signal amplitude values, reducing the estimation error when exposed to random impulse noise.

Figure 1 shows a block diagram of a device for estimating the standard deviation of a discrete signal, where: 1 and 3 are the first and second digital comparators, 2 and 4 are the first and second reversible counters, x, y are the input and output signal buses, respectively, S - digital code corresponding to the number

[0.68 · N], f _∂ is the first clock signal corresponding to the sampling frequency, f _∂ / N is the second clock signal corresponding to the sampling frequency divided by N = 2 ^R (R = 1,2,3 ...), r is the input control the direction of counting of the first counter, C is the code accumulated in the first counter supplied to the first input of the second digital comparator, q is the input of controlling the direction of counting of the second counter.

Figure 2 shows the dependences of the general normalized error of estimating ε on the bit length of the sample length R obtained from the results of modeling the operation of devices that implement algorithms (1) and (2) when exposed to normal white noise, where: 1 is the experimental curve, 2 is its approximation , 3 - the result obtained using algorithm (1).

Figures 3a and 3b show the dependences of the total normalized error in estimating ε under the influence of impulse noise with a uniform distribution of amplitude and duty cycle on the probability of occurrence of noise p, devices that implement algorithms (2) and (1), respectively. Curves 1, 2, 3, 4, 5 correspond to sample bit sizes R = 8, 9, 10, 11, 12.

The device works as follows: the first reversible counter 2 has a bit depth of R + 1, the value in it increases by a unit of the least significant digit, if the next sample x is less than the standard deviation y obtained from the previous N samples, it decreases otherwise. After N comparison and accumulation operations, the value C obtained in the first counter goes to the input of the second comparator, where it is compared with the number S. If C <S, then the value of the second reverse counter increases, otherwise it decreases by a unit of the least significant digit. The width of the second reverse counter is equal to the width of the samples of the input signal.

Modeling the operation of devices implementing algorithms (1) and (2) under the influence of white normal noise showed that the proposed evaluation device has a total error of 2–3% larger than a device that implements a selective standard deviation algorithm. Studies have shown that the largest contribution to the overall estimation error is made by the systematic component, which can be compensated using the values given in table 1, while the overall errors of the proposed and known evaluation devices are approximately equal.

Table 1 The dependence of the systematic error on the bit length of the sample R 5 6 7 8 9 10 eleven 12 13 fourteen fifteen 16 ε _b ,% 7.74 4.70 3.19 2.44 2.07 1.88 1.79 1.74 1.72 1.71 1.71 1.70

Modeling the operation of devices that implement algorithms (1) and (2) under the influence of impulse noise with a uniform distribution of amplitude and duty cycle showed that with a high probability of the appearance of an interference pulse (p≥0.1%), the error of the proposed device is 2 to 4 times less than the error of the device that implements the algorithm (1).

Table 2 shows the comparative data on the hardware costs by the example of processing 8-bit samples based on the FPGA of the Xilinx Spartan 2 series. It can be seen that the proposed device for estimating the standard deviation of a discrete signal provides a significant reduction (from 4 to 6 times) in hardware costs compared with a device that implements the algorithm (1).

table 2 Comparative data on hardware costs R The number of logical blocks Proposed device Known device 8 6 33 10 7 34 12 8 35 fourteen 9 36 16 9 37

Thus, the developed device circuit for estimating the standard deviation of a discrete signal has the following features:

- high accuracy of the assessment under the influence of pulsed noise (the error of the proposed device is 2-4 times less than the error of the device that implements the algorithm (1) with a high probability of the occurrence of pulsed noise (p≥0.1%));

- simplicity of circuitry implementation;

- significant saving of system resources (4-6 times reduction in hardware costs compared to a device that implements algorithm (1)).

Information sources

1. Smith S.W. The scientist and engineer's guide to digital signal processing. - San Diego: California technical publishing, 1999 .-- 650 p.

2. RF patent for the invention No. 2277715.

3. Vygodsky M.Ya. Arithmetic and Algebra in the Ancient World. - M .: Nauka, 1967 .-- 368 p.

4. Kiselev A.P. Algebra. C.P. - M .: FIZMATLIT, 2005 .-- 248 p.

5. RF patent for the invention No. 2400809 - prototype.

Claims (1)

A device for estimating the standard deviation of a discrete signal, comprising a digital comparator and two reversing counters, characterized in that a second comparator is additionally introduced, the first clock signal being connected to the clock input of the first reversing counter and the second clock signal being connected to the clock input of the second reversing counter and with the preset input of the first reversible counter, the input signal bus is connected to the first code input of the first digital comparator, the bus is output the signal is connected to the code output of the second reversible counter and the second code input of the first digital comparator, the output of the first digital comparator is connected to the input direction control of the counting of the first counter, the first input of the second digital comparator is connected to the code output of the first reversible counter, and the second input of the second digital comparator the code corresponding to the constant [0.68 · N], where N is the number of samples in the sample, the output of the second digital comparator is connected to the direction control input We have accounts of the second reversible counter.

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