RU2421935C1 - Device to record and reproduce stereo video information - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: device to record and reproduce stereo video information comprises a video information accumulator, including the first-third channels of colour signals R, G, B of the left frame of a stereo mate and the fourth-sixth channels of colour signals R₂, G₂, B₂ of the right frame of a stereo mate, and the device includes the left and right flat panel screens and glasses of the divided field of vision.

EFFECT: recording complete stereo video information of three resolution modes and its reproduction in a double-screen manner.

12 dwg, 3 tbl

Description

The invention relates to the hardware of a personal computer / PC / and can be used to record and play stereo video information.

The prototype adopted a video player DVD player [1, p. 406, 409], comprising a video storage device / DVD-video disc / and a DVD drive. The disadvantages of the prototype are the presence of the drive, performing only the function of reading video information, does not reproduce stereo information.

The purpose of the invention is the recording and playback of stereo video in a two-screen way.

Technical results include recording full / non-compressible / stereo video information of three resolution modes and playing it in a two-screen way [1, p. 540].

The essence of the invention is that the device for recording and reproducing stereo video information contains a video information storage device including the first and third channels of color signals R, G, B of the left frame of the stereo pair and the fourth and sixth channels of color signals R ₂ , G ₂ , B _{2 of the} right frame of the stereo pair, and left and right flat-panel screens and glasses of separate field of view are introduced into the device.

Stereo video information is recorded from a PC video adapter forming left and right frames of stereo pairs, and from TVs of digital stereo television systems [2]. The codes of the left and right frames of stereo pairs are recorded in parallel, the frames of stereo pairs are played synchronously on two adjacent left and right screens, the image from which the viewer sees separately through the glasses of a separate field of view. The input signals during recording are the 8-bit color codes of the left frame R, G, B and the color codes of the right frame R ₂ , G ₂ , B _{2 of the} stereo pair from the video adapter of the PC or TV set of the stereo television system. Recording and playback are performed in two resolution modes from a PC 1280 × 1024 and 1600 × 1200 and HDTV resolution mode 1920 × 1080 from a TV.

A diagram of a stereo video recording and reproducing device is shown in FIG. 1, a color signal code storage device in FIG. 2, a frame code storage device in FIG. 3, register blocks in FIGS. 4-9, a general view of one matrix element in FIG. 10, the cell of the matrix element is shown in FIG. 11, the diaphragm of the cell in the closed position is shown in FIG. 12, the arrangement of the matrix elements in the screen is shown in FIG. 13.

The device for recording and reproducing stereo video information includes a video storage device including / Fig. 1/ the first to third channels of color signals R, G, B of the left frame of the stereo pair and the fourth to sixth channels of color signals R ₂ , G ₂ , B _{2 of the} right frame of the stereo pair. All channels are identical, each includes a series-connected drive 1 of the color signal codes and block 2 of pulse amplifiers, the outputs of blocks 2 of the first and third channels are connected to the inputs of the left flat panel 3, the outputs of blocks 2 of the fourth and sixth channels are connected to the inputs of the right flat panel 4, image on screens 3, 4, the viewer examines through the glasses 5 a separate field of view, and the device includes a pulse generator 6 and a pulse distributor 7 connected in series.

The drives 1 of the color signal codes of the first to sixth channels are identical, each contains (Fig. 2/) drives 8 frame codes for the number of recorded frames and a pulse distributor 9, the input of which is the first control input of the drive 1 of the color signal codes and is connected to the first control output U _to clock frame of the video adapter PC, and the outputs of the distributor of 9 pulses are connected to the first control inputs U _to sequentially from the first to the last drive 8 frame codes. The information input of the drive 1 color code codes are the bit-wise combined first to eighth inputs of all drives 8 frame codes, which are connected in the first and third channels of color signals R, G, B / Fig. 1/ to the information first and eighth outputs of color signals, respectively R, G, B of the PC video adapter, and in the fourth to sixth channels of the color signals R ₂ , G ₂ , B _{2 are} connected to the information first-eighth outputs of the color signals R ₂ , G ₂ , B _{2 of the} PC video adapter. The control inputs of drive 1 of the color signal codes are / Fig. 2/: the first is the input of the distributor of 9 pulses, the second is the combined second control U _page inputs of all drives 8 frame codes, the third is the combined third control U _d inputs of all drives 8 frame codes, fourth the control inputs are the fourth control U _output inputs of the drives 8 frame codes connected to the corresponding outputs of the distributor 7 pulses / 2 /. The first, second, third control inputs of the same name of the drives 1 color signal codes / Fig. 1/ of the first to sixth channels are combined and connected respectively to the first U _to , U _p , third U _d control outputs of the PC video adapter. The outputs of the drive 1 color code codes are the parallel outputs of all drives 8 frame codes connected to the inputs of the unit 2 of the pulse amplifiers of their channel. The drives 8 frame codes are identical, each includes / Fig. 3/ blocks of registers 10 by the number of lines 1200 resolution mode 1600 × 1200. The information input of the drive 8 frame codes are the bit- _wise combined first to eighth inputs of all blocks of 10 _1-1200 registers, the control inputs are: the first is the first control U _{to the} input of the first block of 10 ₁ registers, the second is the combined second control U _page inputs of 10 register blocks, the third is the combined third control U _d inputs of blocks of 10 registers, the fourth is the combined fourth control U _output inputs of blocks of 10 registers.

The control output of each previous block of 10 registers is the first control input of each subsequent block of registers. The outputs of the drive 8 frame codes are parallel outputs of all blocks of 10 registers. The blocks of registers from the first to 1024 are identical, each includes / Fig. 4/ series-connected key 11 and the distributor 12 pulses, three elements And 13 _1-3 and eight registers 14 _1-8 , each of 1920 digits. The first-eighth information inputs of the register block are the bitwise combined third / information / bit inputs of the eight registers 14. The control inputs are: the first is the first control / U _from / key input 11, the second is the combined second inputs U _{page of the} first-third elements And 13, third - the signal U _d key input 11, the fourth - the combined second control inputs U _vyd bits eight registers 14. The pulse distributor 12 outputs sequentially from the first one, connected to the first / clock / Parallel input bits flax eight registers. The first inputs of the elements And 13 _{1-3 are} connected respectively to 1280, 1920 and 1600 outputs of the distributor 12 pulses, the second inputs of the elements And 13 _{1-3 are} combined and connected to the second control input U _p , and the outputs of the elements And 13 _1-3 in blocks 1 - registers 1023 are combined and connected to the U _of the second control input key 11 and is a control output of the next register block. The outputs of the register block are the parallel outputs of all bits of the eight registers 15360/1920 × 8 /. In the block of 1024 registers, the outputs of the second and third elements And 13 _{2, 3 are} combined, connected to the second control U _s input of the key 11 through the diode and are the control output of the block 1024 registers in the next block of registers, and the output of the first element And 13 ₁ in the block 1024 registers connected to the second control U _s key input 11 after the diode, therefore, with a resolution mode of 1280 × 1024 from block 10 ₁₀₂₄ registers of the control signal in the next block 10 ₁₀₂₅ no.

Blocks 10 registers from 1025 to 1079 are identical, each includes / Fig.6/ key 11, the distributor 12 pulses, two elements And 13 _{2,3 the} second and third and eight registers 14 _1-8 , each of 1920 digits. The first-eighth information inputs are the bitwise combined third / information / inputs of the bits of eight registers 14, the control inputs are: the first is the first control U _{from the} key input 11, the second is the combined second inputs of the second and third elements And 13 connected to the second control U _p the input of the block of 10 registers, the third - signal U _d key input 11, the fourth - the combined second U _output inputs of bits in parallel to eight registers 14. The outputs of the distributor 12 pulses in series, starting from the first, connect are connected to the first / clock / bit inputs parallel to eight registers 14. The first inputs of the And 13 _2,3 elements are connected respectively to 1920 and 1600 outputs of the 12 pulse distributor, their second inputs are combined and connected to the second control input of the block of 10 registers U _p , and outputs of aND gates 13 _2.3 10 registers in blocks 1025-1079 are combined, connected to the second control input U _of the key 11 and is a control output of the next block register 10 / 1025-1080 /. In block 1080 of the registers the output of the third element And 13 _{3 is} connected to the second control U _s input of the key 11 through the diode and is the control output to the block 10 ₁₀₈₁ registers, and the output of the second element And 13 _{2 is} connected to the second control U _{s the} input of the key 11 after the diode, and with a resolution mode of 1920 × 1080 with a block of 10 ₁₀₈₀ registers of the control signal in the next block 10 ₁₀₈₁ will not be.

Blocks 10 registers from 1081 to 1200 are identical, each includes a key 11, a pulse distributor 12, one / third / element And 13 _{3 /} Fig.8/ and eight registers 14 _1-8 , each of 1600 bits. Information first-eighth inputs are the bitwise combined third / information / inputs of the bits of eight registers 14, the control inputs are: the first is the first control U _{from the} input of the key 11, the second is the second U _page input of the element And 13 ₃ , the third is the signal U _d key input 11, fourth - the combined second control U _output inputs of bits in parallel to eight registers 14 _1-8 . The outputs of the distributor of 12 pulses are connected in series to the first / clock / inputs of the bits of eight registers 14. The first input of the And 13 ₃ element is connected to the 1600 output of the distributor of 12 pulses, the second input of the And 13 ₃ element to the second U _page control input to the block of 10 registers, and the output of the element And 13 ₃ in blocks 10 of _1081-1199 registers is connected to the second control U _s input of key 11 and is a control output in the following blocks 10 of _1082-1200 registers. The outputs are the parallel outputs of all blocks 10 _1-1200 registers _12800/1600 × 8 /. In block element registers October ₁₂₀₀ and March ₁₃ /fig.9/ asked to close key 11 October ₁₂₀₀ in the block of registers 1600, the pulse distributor 12 is connected directly to the output of the second control input U _of the key blocks 11. The two pulse amplifiers are identical, each including pulse amplifiers according to the number of the largest number of screen resolutions 3, 4 and the number of bits in the code 18432000/1920 × 1200 × 8 /. The output signals from the amplifiers of blocks 2 are control signals — the unit pulses in the codes for cells in the matrix elements of screens 3, 4. In the HDTV format resolution mode of 1920 × 1080 and a stereo frequency of 50 Hz, the code sampling rate is:

f _d = 1920 × 1080 × 50 Hz = 103.68 MHz, where 1920 is the number of samples in a line, 1080 is the number of lines in a frame, 50 Hz is the frequency of stereo pairs. Images of stereopair frames from a PC video adapter are output to drives 8 frame codes by raster method, from drives 8 frame codes to flat-panel screens 3, 4 are entered in full frames, and the elements of the matrix screens keep the brightness and color tone of the pixels unchanged for a duration of 20 ms frame, which increases perception by sight of brightness and clarity of the image on the screen.

Resolution mode parameters at a stereo Hz frequency of 50 Hz in table 1.

Table 1 Resolution mode Sampling Rate, MHz Line frequency, kHz Write Speed, MB / s Frame capacity, MB Recording hour capacity, GB / hour 1,280 × 1,024 65,536 51,2 65,536 1,310720 235.9296 1600 × 1200 96 60 96 MHz 1.92 345.6 1920 × 1080 103.68 54 103.68 2,0736 373,248 1920 × 1200 - - - 2,3040 -

The number of drives 8 frame codes for hourly recording of stereo video in table 2.

table 2 Resolution Mode Capacity of one drive 8 frames Hourly recording capacity, MB / h Number of drives 8 frame codes 1,280 × 1,024 1,310720 MB 235929.6 180 × 10 ³ 1600 × 1200 1.92 MB 345600 180 × 10 ³ 1920 × 1080 2.0736 MB 373248 180 × 10 ³

Flat-panel screens 3, 4 are identical, each contains 2304000 matrix elements in the number of maximum number of rows 1200 and samples in row 1920. A general view of one matrix element is shown in Fig. 10 and includes an opaque case 15 of an insulating material of the corresponding form, combining three cells : the lower left cell 16 emits a red R, the upper cell 17 emits a green G, the lower right cell 18 emits a blue B. Each cell contains / Fig. 10/ in the front end of the housing 15 a microlens 19, which acts as a micro lens, in the bottom end of the body 15, the cell contains a color filter 20, one of the primary colors R, G, B, between the microlens 19 and the color filter 20, a diaphragm 21 type / iris / /fig.11/ comprising a cylindrical body 22 with eight slots 23 and the first ₁ through the eighth 23 ₈ micropiezoelectric elements, the first ends of which with two control inputs are rigidly fixed in the housing 15 / Fig.12/ of the matrix element, the second free ends of the micropiezoelectric elements 23 _1-8 are the shutters of the diaphragm 21 and are placed in the slots of its housing 22 / Fig.11 / so as not to interfere with each other. The free ends are made in the form of flat opaque very thin petals, each of the corresponding shape and area / Fig.12/. The values of the areas from the first 23 ₁ to the eighth 23 ₈ micro-piezoelectric element correspond to the principle of binary code: 2 ⁷ , 2 ⁶ ... 2 ² , 2 ¹ , 2 ⁰ . The control inputs of the micropiezoelectric elements 23 _1-8 are the control inputs of the cells and are connected to the corresponding outputs of the corresponding pulse amplifiers in blocks 2. The amplitude of the pulses is amplified in the pulse amplifiers to the operating voltage of the micropiezoelectric elements 23 _1-8 , and the duration is 20 ms

/. Лепестки микропьезоэлементов 23 являются исполнительными элементами /шторками/ диафрагмы 21 и каждый по управляющему импульсу открывает часть поперечного пространства диафрагмы /фиг.12/ соответственно весу своего разряда./

/. The petals of the micropiezoelectric elements 23 are actuators / shutters / diaphragms 21 and each of the control pulse opens part of the transverse space of the diaphragm / 12 / according to the weight of its discharge.

Table 3 Code bit number one 2 3 four 5 6 7 8 Code Weight 2 ⁷ 2 ⁶ 2 ⁵ 2 ⁴ 2 ³ 2 ² 2 ¹ 2 ⁰ The opening part of the diaphragm,% fifty% 25 12.5 6.25 3,125 1,56 0.78 0.39

In screens 3, 4, all cells of the matrix elements are illuminated from the microlenses 19 (Fig. 10/) with super-bright white LEDs, which are located in the appropriate amount in a certain order in the back of the screen housing 3, 4 and continuously irradiate microlenses 19 cells of the matrix elements. The microlens 19 directs the radiation through the diaphragm 21 to its color filter 20. In the absence of control signals / units in the code / micropiezoelectric elements 23 are in the initial unstressed state: all the petals overlap the plane of the aperture / Fig. 12/ and close the path to the radiation to the color filter 20. When the receipt of the control pulse from block 2, the corresponding micro-piezoelectric element 23 performs bending / or torsion / and outputs its lobe from the diaphragm 21, revealing its part according to the weight of the discharge. When the code 11111111 arrives, eight control pulses drive eight micro-piezoelectric elements 23 _1-8 , the diaphragm 21 is fully open for the entire period of 20 ms frame. For different values of the codes, parts of the diaphragm 21 are opened, respectively, to units in the code: the brightness of the cell radiation is directly proportional to the code of the video signal. In the open state, the petal is 20 ms / frame period /. The cells of the matrix elements and the diaphragm 21 with micropiezoelectric elements are extremely miniature to obtain matrix elements of meager sizes. Screens 3, 4 are typed from matrix elements by the number of rows 1200 and the number of reports in row 1920, their location on the screen in Fig.13. Each element of the matrix forms one pixel with brightness and color tone, respectively, for three codes of video signals R, G, B in the left screen 3 and three codes of video signals R ₂ , G ₂ , B ₂ in the right screen 4. The maximum brightness of the cells depends on the brightness of their LEDs backlights, which are used in an amount that provides the required brightness, and are placed in the screen body on its back in an order that performs uniform illumination of microlenses 19 of all cells.

Glasses 5 of a separate field of view / Fig. 1/ represent a frame with ear arches, glasses windows without glasses, are interconnected movably by a vertical axis for rotation relative to each other. To separate the fields of view of the eye, each point has a conical hood at the end of a rectangular shape / under the shape of screens /. A two-part hood: the first part is screwed into the point, the second part is movable: it is pushed into or out of the first to change the length of the hood. Screens 3, 4 are placed at a distance of 20 ... 30 cm from each other, the viewer with a distance of 1.5 ... 2 meters / depending on the size of the screens / turning the glasses and moving the hood adjusts the field of view of the eyes so that each eye sees its own screen and does not I saw the second screen. Images of the left and right frames of stereo pairs are displayed on screens 3, 4 in parallel and synchronously with a single output signal from the distributor of 7 pulses.

The process of recording stereo video information.

кодов кадра. В накопителе 8₁ кодов кадра /фиг.3/ первый импульс с распределителя 9 импульсов открывает ключ 11 в блоке 10₁ регистров /фиг.4/, пропускающий импульсы дискретизации U_д /табл.1/ в распределитель 12 импульсов, тактовые импульсы с которого последовательно поступают на первые /тактовые/ входы разрядов параллельно восьми регистрам 14_1-8, которые заполняются кодами первой строки первого кадра. С 1280, 1920 и 1600 выходов распределителя 12 импульсов импульсы поступают на первые входы трех элементов И 13_1-3, на вторые входы которых поступают импульсы частоты строк принимаемого режима разрешения /табл.1/ с видеоадаптера ПК /либо телевизора/. При совпадении передних фронтов этих импульсов в соответствующем элементе И 13 с выхода его следует импульс, закрывающий ключ 11 и являющийся управляющим выходным сигналом в следующий блок 10₂ регистров и открывающий в нем ключ 11. Регистры 14 блока 10₂ регистров заполняются кодами второй строки. Таким же образом заполняются кодами строк остальные блоки 10 регистров, относящихся к принимаемому режиму разрешения. При разрешении 1280×1024 в накопителе 8₁ кодами строк заполняются блоки 10 регистров с первого по 1024, а в регистрах 14_1-8 заполняются 1280 разрядов. Импульс с элемента И 13₁ в блоке 10₁₀₂₄ регистров /фиг.5/ закрывает ключ 11, на управляемом выходе этого блока сигнала нет, так как выход элемента И 13₁ подключен к входу U_з ключа 11 после входа, и в следующем блоке 10₁₀₂₅ регистров ключ 11 не открывается. Далее заполняются кодами строк блоки 10_1-1024 регистров накопителя 82 кодов кадра и так до последнего накопителя

кодов кадра. При разрешении 1920×1080 кодами строк заполняются блоки 10 регистров с первого по 1080, а в регистрах 14_1-8 заполняются разряды 1920 кодами. В блоке 10₁₀₈₀ регистров импульс с элемента И 13₂ /фиг.7/ закрывает ключ 11 и в следующий блок 10₁₀₈₁ регистров управляющий сигнал не приходит. Далее заполняются кодами строк регистры 14_1-8 остальных накопителей 8 кодов кадра. При разрешении 1600×1200 кодами строк заполняются регистры 14_1-8 в блоках 10 регистров с первого по 1200 /фиг.8, 9/. Блок 10₁₂₀₀ регистров /фиг.9/ элемента И 13 не имеет, ключ в нем закрывается импульсом с 1600-го выхода распределителя 12 импульсов. Второй импульс с распределителя 9 импульсов открывает ключ 11 в первом блоке 10₁ регистров накопителя 8₂ кодов кадра, повторяется процесс заполнения кодами строк регистров 14_1-8. Аналогично заполняются все остальные накопители 8 с третьего по 180·10³ кодов кадра. Такой же процесс заполнения кодами строк накопителей 8 кодов кадра идет параллельно во всех шести каналах цветовых сигналов. Накопители

в шести каналах представляет собой наборы микросхем флэш-памяти /твердотельного носителя/, являющиеся энергонезависимыми в режиме хранения с большим числом циклов стирания записи [3 с.517].The sync pulse of the stereo pair U _k from the first control output / Fig. 1/ of the PC video adapter is sent in parallel to each of the six drives 1 color code codes to the input of the 9 pulse dispenser / Fig. 2/. From the outputs of the distributor of 9 pulses, the pulses of the frequency of stereo pairs of 50 Hz sequentially open 8 drives of codes from the first to 180 × 10 ³ frames for recording. The drive 8 ₁ frame codes are filled with codes of the first frame, the drive 8 _{2 is} filled with codes of the second frame, etc. to the last drive

frame codes. In the drive 8 ₁ frame codes / Fig. 3/, the first pulse from the 9-pulse distributor opens the key 11 in the block 10 ₁ registers / Fig. 4/, which passes the sampling pulses U _{d /} table 1/ into the 12-pulse distributor, clock pulses from which sequentially arrive at the first / clock / bit inputs parallel to eight registers 14 _1-8 , which are filled with codes of the first line of the first frame. From 1280, 1920 and 1600 outputs of the distributor of 12 pulses, the pulses are fed to the first inputs of the three elements And 13 _1-3 , the second inputs of which are pulses of the frequency of the lines of the received resolution mode / table 1 / from the video adapter of the PC / or TV /. If the leading edges of these pulses coincide in the corresponding element And 13, an output follows a pulse that closes the key 11 and is the control output signal to the next block of 10 ₂ registers and opens the key in it 11. Registers 14 of the block 10 of ₂ registers are filled with the codes of the second line. In the same way, the remaining blocks of 10 registers related to the received resolution mode are filled with row codes. At a resolution of 1280 × 1024 in the drive 8 _1, row codes fill blocks of 10 registers from the first to 1024, and 1280 bits are filled in registers 14 _1-8 . A pulse from the AND January ₁₃ October ₁₀₂₄ in the block closes /fig.5/ register key 11 on the control outputs of this block is no signal, as an output of AND 13 ₁ is connected to the input U _of the key 11 after entry, and in the next block 10 ₁₀₂₅ registers key 11 does not open. Next, block codes 10 _{1-1024 of the} drive registers 82 frame codes are filled with row codes until the last drive

frame codes. At a resolution of 1920 × 1080, block codes are filled in blocks of 10 registers from the first to 1080, and in registers 14 _1-8, bits of 1920 are filled in with codes. In the block 10 ₁₀₈₀ registers the pulse from the element And 13 _{2 /} Fig.7/ closes the key 11 and in the next block 10 ₁₀₈₁ registers the control signal does not come. Next, registers 14 _{1-8 of the} remaining drives 8 frame codes are filled with row codes. At a resolution of 1600 × 1200, row codes are filled in registers 14 _1-8 in blocks of 10 registers from the first to 1200 / Fig. 8, 9 /. Block 10 ₁₂₀₀ registers / 9 / And element 13 does not have, the key in it is closed by a pulse from the 1600th output of the distributor of 12 pulses. The second pulse from the distributor of 9 pulses opens the key 11 in the first block 10 _{1 of the} drive registers 8 ₂ frame codes, the process of filling in the codes of the register lines 14 _{1-8 is} repeated. Similarly, all other drives 8 from the third to 180 · 10 ³ frame codes are filled. The same process of filling in the codes of the rows of the drives 8 frame codes goes in parallel in all six channels of color signals. Drives

in six channels is a flash memory chipset / solid-state carrier /, which are non-volatile in storage mode with a large number of write erase cycles [3 p. 517].

Reproduction process.

The playback process consists in sequential frame-by-frame issuing of frame codes synchronously and in parallel from the drives 8 frame codes (Fig. 2/) of each of the six drives 1 color signal codes / Fig. 1/ into their blocks 2 pulse amplifiers. When the power is turned on, the 6-pulse generator / Fig. 1/ generates stereo pulses / 50 Hz / at the input of the 7-pulse distributor. The 7 pulse distributor has outputs for the number of drives 8 frame codes: from the first to 180 × 10 ³ . The first output pulse distributor 7 is connected parallel to the fourth control inputs U _vyd all blocks in storage registers 10 _August 1st frame codes /fig.2/ six color channel signals, the second output pulse distributor 7 is connected parallel to the fourth control inputs U _vyd registers 10 of all the blocks Storage at ₈ February color signals of six channels, and so on, the last output pulse distributor 7 is connected parallel to the fourth control inputs U _vyd all blocks in the latter 10 registers Storage 8180 · 10 ³ frames codes. From each drive 8 frame codes, all frame codes are issued synchronously and in parallel to their units 2 pulse amplifiers. The pulses of code units generated by the amplitude and duration are fed to the corresponding inputs of the corresponding cells of the matrix elements of the screens 3, 4, displaying the left and right images of the frames of the stereo pair.

The operation of the device.

Before recording stereo information, the information inputs of the drives of codes 1 color signals are connected by connecting cables to the information outputs R, G, B and R ₂ , G ₂ , B _{2 of the} PC video adapter / 1/1, the first and third control inputs of the device are connected respectively to the first or third control outputs of the PC video adapter. The device’s power is turned on, the personal computer is turned on to issue codes from the PC video adapter. The speed of recording information corresponds to the resolution mode and is 65.536 MB / s / 1280 × 1024 /, 96 MB / s at 1600 × 1200, 103.68 MB / s at 1920 × 1080.

To play stereovideoinformatsii switched pulse generator 6 /fig.1/ frequency pulses stereopairs 50 Hz are input to the pulse distributor 7, which outputs sequentially supplied to the fourth control inputs U _vyd storage frame 8 parallel to the first-codes of six channels and output the color signals of the they are codes of left and right frames of stereo pairs in their blocks 2 pulse amplifiers, the outputs of which control pulses are fed to the inputs of their cells of the matrix elements of screens 3, 4.

The viewer puts on glasses 5, adjusts the visual fields of view on screens 3 and 4. The inventive device records stereo video information of two resolution modes from a PC video adapter and 1920 × 1080 mode from a TV system of stereo television and plays it in a two-screen way. The drive volume is accepted for one hour, to increase the recording volume, increase the number of drives 8 frame codes and increase the number of outputs from the 7 pulse distributor and the 9 pulse distributor. In the absence of stereo video information, the device is suitable for recording and playing back mono video information.

Used sources

1. Kolesnichenko OV, Shishigin I.V. PC hardware. 5th ed. St. Petersburg, 2004, p. 406, 409, 540.

2. RF patent No. 2369041 C1, cl. H04N 15/00, bull. No 27 on 09/27/09

3. M. Guk. Hardware BM PC. Encyclopedia. 3rd ed., St. Petersburg, Peter, 2006, p. 517.

4. A personal computer today. RS MAGAZINE, No. 11 for 2008, p.13, the third column, below.

Claims (1)

A device for recording and reproducing stereo video information containing a video information storage device, characterized in that the video information storage device includes first-third channels of color signals R, G, B of the left frame of the stereo pair, fourth and sixth channels of color signals R ₂ , G ₂ , B _{2 of the} right frame of the stereo pair and the pulse generator and the pulse distributor are connected in series, and left and right flat-panel screens and glasses of a separate field of view are introduced into the device for recording and reproducing stereo video information, the first and third to the color signal channels R, G, B and the fourth to sixth channels of color signals R ₂ , G ₂ , B _{2 are} identical, each contains a series-connected drive of color signal codes and a block of pulse amplifiers, informational first to eighth inputs of drives of color signal codes of the first to third color channels R, G, B are connected to the informational first to eighth outputs of color signals, respectively R, G, B of the video adapter of a personal computer (PC), informational first to eighth inputs of drives of color codes of four rtogo-sixth channel color signals R _2, G _2, B ₂ are connected to data first-eighth outputs color signals, respectively, R _2, G _2, B ₂ video PC same name first, second, third control inputs of the drives color signal codes of the first to sixth channels are combined and connected respectively to the first (U _to ), second (U _p ), third (U _d ) control outputs of the PC video adapter, the pulse distributor contains the corresponding number of outputs connected to the corresponding fourth control inputs of the drives codes of color signals in the first to sixth channels, drives of codes of color signals of the first to sixth channels are identical, each contains drives of frame codes by the number of recorded frames and a pulse distributor, the input of which is the first control input of the drive of color signal codes, and its outputs are connected to the first control the inputs (U _to ) sequentially from the first to the last drive codes of the frame, the second control input of the drive codes color signals are the combined second control inputs (U _p ) in all the drive codes of the frame, the third control input is the combined third control inputs (U _d ) of all drive codes of the frame, the fourth control inputs of the drive codes of color signals are the fourth control inputs (U _output ) of all drives code codes connected to the corresponding outputs of the pulse distributor recording device and playback of stereo video information, the outputs of the color code code storage device are the parallel outputs of all frame code storage devices, the frame code storage drives are are typical, each includes blocks of registers according to the number of lines (1200) of the resolution mode containing a larger number of lines, the information input of the frame code storage device is the bit-wise combined first to eighth inputs of all blocks (1200) of registers, the control inputs are: the first is the first control (U _to ) the input of the first block of registers, the second is the combined second control inputs (U _p ) the inputs of the blocks of registers, the third is the combined third control inputs (U _d ) of the blocks of registers, the fourth is the combined fourth control inputs (U _output ) of the blocks of re histories, the control output of each previous block of registers is the first control input of each subsequent block of registers, the outputs of the frame code storage device are the parallel outputs of all register blocks, the register blocks 1 to 1024 are identical, each includes a series-connected key and pulse distributor, three AND elements from the first the third and eight registers, each of 1920 digits, the informational first-eighth inputs of the register block are the bitwise combined third inputs of the digits of the eight registers , Control inputs are: first - the first control (U _off) of the key input, the second - the combined second control (U _p) inputs of the first and third AND gates, the third - the signal input (U _d) of the key, the fourth - the combined second control (U _vyd ) the inputs of the bits of eight registers, the outputs of the pulse distributor in series, starting from the first, are connected to the first (clock) inputs of the bits parallel to eight registers, 1280, 1920 and 1600 the outputs of the pulse distributor are connected to the first inputs of the first and third elements , and their outputs in blocks 1 - 1023 of the registers are combined and connected to the second control input (U _З ) of the key and are the control output to the next block of registers, the outputs of the register block are the parallel outputs of all bits of eight registers 15360 (1920 × 8), in the block 1024 registers the outputs of the second and third elements AND are combined, connected to the second control (U _h ) key input through a diode and are the control output of the 1024 register block, and the output of the first AND element in block 1024 registers is connected to the second control (U _h ) key input after iodine, the register blocks from 1025 to 1079 are identical, each contains a key and a pulse distributor, two elements And the second and third and eight registers, each of 1920 bits, the information first-eighth inputs are the bit-wise combined third (information) inputs of the bits of eight registers that control entrances are: first - the first control (U _off) of the key input, the second - the combined second control (U _p) inputs of second and third aND gates, the third - the signal (U _d) of the key input, the fourth - the combined second (U _vyd) inputs discharge parallel to eight registers, the outputs of the pulse distributor are sequentially, starting from the first, connected to the first (clock) inputs of the bits in parallel to eight registers, 1920 and 1600 the outputs of the pulse distributor are connected to the first inputs of the second and third elements And their outputs in blocks 1025-1079 are combined are connected to the second control (U _z) and the input key is a control output of the next register block, the register outputs of these blocks are parallel outputs of register blocks 15360 (1920 × 8) in the block 1080 registers O d a third AND gate connected to the second control (U _h) entry key through a diode and a control output unit 1080 registers in the next register block, and an output of the second AND gate is connected to the second control (U _h) entry key after diode register blocks 1081 1200 are identical, each contains a key, a pulse distributor, one (third) element And and eight registers, each of 1600 bits, the information first-eighth inputs are the bit-wise combined third (information) inputs of the bits of eight registers that control and the inputs are: first - the first control (U _off) of the key input, the second - the second (U _p) input AND gate, the third - the signal (U _d) input key, the fourth - the combined second control (U _vyd) inputs of bits of parallel eight registers , the key output is connected to the input of the pulse distributor, the outputs of which, starting from the first, are sequentially connected to the first (clock) inputs of the bits of eight registers, 1600 the output of the pulse distributor is connected to the first input of the And element, the output of which is connected to the second control (U _h ) input cl Cha and is a control output of the next register unit outputs are parallel outputs of register blocks 12800 (1600 × 8), at block 1200 the element registers and not a 1600 pulse distributor output connected directly to the second control (U _h) entry key blocks pulse amplifiers are identical, each includes pulse amplifiers in terms of the number of resolution of the flat panel screen and the number of bits in the code 18432000 (1920 × 1200 × 8), the inputs of the pulse amplifiers are connected to the corresponding outputs of the corresponding drives of color codes signals, flat-panel screens are identical, each contains 2304000 matrix elements in terms of the maximum number of rows (1200) and samples in a row (1920), each matrix element includes an opaque body of insulating material of the corresponding form, combining three cells: the lower left cell emits red color, the upper cell emits green, the lower right cell emits blue, each cell in the front end of the housing of the matrix element contains a microlens, in the output end of the body of the cell contains a color filter p (one of the primary colors R, G, B), between the microlens and the color filter there is a diaphragm that includes a cylindrical body with eight slots and eight micro-piezoelectric elements in them, the first ends of the micro-piezo elements with two control inputs are rigidly fixed in the matrix element body, the second free ends micro-piezoelectric elements are the shutters of the diaphragm, are placed in the slots of the diaphragm body and are made in the form of flat thin opaque petals of the corresponding shape and area, the dimensions of which correspond to binary code, the control inputs of the micropiezoelectric elements are the control inputs of the cells and are connected to the corresponding outputs of the respective pulse amplifiers in the blocks of pulse amplifiers, the cells are illuminated with superbright white LEDs, in an appropriate amount and in a certain order located on the back of the flat-panel screen housing, split-field glasses the view is made with a frame with arches for the ears, the windows of glasses without glasses, interconnected movably by a vertical axis, ach point has a tapered hood on the end of a rectangular shape, consisting of two parts: the first part is screwed into a point, the second movable portion is extended or pushed into the first, changing the length of the hood.

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