RU2418373C2 - Receiver for wireless communication network with expanded range - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: signals are detected in several stages using correlation in time domain for the first stage, processing in frequency domain for the second stage and processing in time domain for the third stage. Products of symbols are formed for the first stage, at least for two different delays, correlation is carried out between products for each delay and available values, and results of correlation for all delays are combined and used to announce the signal availability. For demodulation, synchronisation of input samples is adjusted to produce time-adjusted samples. Frequency deviation is assessed and removed from time-adjusted samples to produce samples with frequency correction, which are processed with the help of channel assessment to produce detected symbols. Phases of detected symbols are corrected to produce symbols with phase correction, which are demodulated, alternated backwards and decoded.

EFFECT: provision of wireless communication network and station, functioning with expanded coverage range.

40 cl, 11 dwg

Description

FIELD OF THE INVENTION

The present disclosure generally relates to communications, and more particularly to a receiver for wireless communications.

BACKGROUND

Wireless networks are widely used to provide various communication services, such as data, voice, video, etc. These networks include wireless regional radio communications networks (WWANs) that provide a radio communications zone for large geographic areas (such as cities), wireless local area networks (WLANs) that provide a radio communications networks for medium sized geographical areas (such as buildings and campuses ), and Personal Wireless Networks (WPANs), which provide a radio communication area for small geographic areas (such as homes). A wireless network typically includes one or more access points (or base stations) that support communication for one or more user terminals (or wireless devices).

IEEE 802.11 is a family of standards developed by the Institute of Electrical and Electronics Engineers (IEEE) for WLAN. These standards describe a wireless interface between an access point and a user terminal or between two user terminals. 1999 IEEE 802.11 Standard (or simply “802.11”), which is entitled “Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications” (Part 11: Media Access Control Protocol (MAC) and physical layer protocol (PHY) for wireless LAN), supports data transfer rates of 1 and 2 megabits per second (Mbps) in the frequency range of 2.4 gigahertz (GHz), using either spectrum expansion by frequency hopping (FHSS), or direct spectrum spreading (DSSS). The IEEE 802.11a-1999 standard (or simply “802.11a”) is in addition to 802.11, uses Orthogonal Frequency Division Multiplexing (OFDM) instead of FHSS or DSSS, and supports data rates up to 54 Mbps in the 5 GHz frequency band. The IEEE 802.11b-1999 standard (or simply “802.11b”) is another addition to 802.11 and uses DSSS to support data rates up to 11 Mbps. The IEEE 802.11g-2003 standard (or simply “802.11g”) is another addition to 802.11, uses DSSS and OFDM, and supports data rates of up to 54 Mbps in the 2.4 GHz band. These different standards are well known in the art and are publicly available.

The lowest bit rate supported by 802.11, 802.11a, 802.11b and 802.11g is 1 Mbps. For 802.11b and 802.11g (or simply “802.11b / g”), a special DSSS scheme and a special modulation scheme are used to send transmission (transmitted data) at the lowest transmission speed (data) of 1 Mbps. DSSS and a modulation scheme for 1 Mbit / s require a certain minimum ratio of signal level to the total level of mutual interference and noise (SNR) for reliable reception of the transmission (transmitted data). The transmission range (transmitted data) is then determined by the geographical area within which the receiving station can achieve the desired or best SNR. In some cases, it is desirable to send transmissions (transmitted data) with a range that is larger than the range for the lowest data rate supported by 802.11b / g.

Therefore, in the art there is a need for a wireless communications network and stations capable of operating with an extended coverage range.

SUMMARY OF THE INVENTION

This document describes techniques for detecting and demodulating a signal / transmission (transmitted data) in poor channel conditions (e.g., low SNR). In one aspect, signal detection is performed in several steps using different types of signal processing to achieve good detection efficiency. In an embodiment, signal detection is performed using time domain correlation for the first stage, frequency domain processing for the second stage, and time domain processing for the third stage. Signal detection for each stage can be additionally performed based on an adaptive (self-adjusting) threshold value that is derived based on the received energy for the symbol interval (window) so that the detection efficiency is less sensitive to the level of the received signal. The presence of a signal can be announced based on the results of all three stages.

In an aspect of the first step, the input samples at the receiving station may be narrowed down using a code sequence for generating narrowed symbols. Then form the product of narrowed characters for at least two delays, for example 1-character and 2-character delays. A correlation is performed between the products for each delay and the known values for that delay. Then, the correlation results for all delays are combined, for example, incoherently or coherently for a plurality of expected phases. Signal presence and signal timing can be determined based on the combined correlation results.

In another aspect, demodulation is performed in such a way as to achieve good efficiency under poor channel conditions. In an embodiment, the timing of the input samples is adjusted (for example, using a multiphase filter) to obtain time-adjusted samples. Frequency drift is estimated and removed from time-adjusted samples to obtain frequency-corrected samples, which are processed using channel estimation (for example, using a multi-tap (rake) receiver) to obtain detected characters. The phases of the detected symbols are corrected to obtain phase corrected symbols. Then, phase-corrected symbols are demodulated to obtain demodulated symbols, which are interleaved and decoded to obtain decoded data.

Signal processing for each detection step and for demodulation is described in detail below. Various aspects and embodiments of the invention are also described below.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and essence of the present invention will become more apparent from the following detailed description, taken in conjunction with the drawings, in which the same reference numbers are determined respectively throughout the document.

1 shows a transmitting station and a receiving station.

2 shows a transmission processor in a transmitting station.

Figure 3 shows the PPDU structure used by 802.11b / g.

4 shows a receive processor at a receiving station.

Fig. 5 shows a first detection step and a time synchronization entry unit.

6 shows a second detection step and a frequency synchronization acquisition unit.

7 shows a third detection step and a channel estimator.

Fig. 8 shows a phase correction block.

9 shows a process for performing signal detection for a first step.

10 shows a process for performing signal detection in several steps.

11 shows a process for receiving transmission (transmitted data).

DETAILED DESCRIPTION

The word “typical” is used throughout this document to mean “serving as an example, individual case, or illustration”. Any embodiment or sample described herein as “typical” is not necessarily to be construed as preferred or advantageous over other embodiments or samples.

1 shows a block diagram of a transmitting station 110 and a receiving station 150 in a wireless network 100. The transmitting station 110 is equipped with a single antenna and may be an access point or a user terminal. The receiving station 150 is equipped with several (eg, R = 2) antennas and may also be an access point or a user terminal. In general, each station can be equipped with any number of antennas that can be used to transmit and receive data. An access point is usually a fixed station that communicates with user terminals and may also be called a base station, base transceiver system (BTS), or some other terminology. A user terminal may be stationary or mobile, and may also be called a mobile station, wireless device, subscriber equipment (UE), or some other terminology.

At transmitting station 110, a transmit processor 130 receives traffic data from a data source 120, processes the traffic data in accordance with a data rate selected for transmission, and provides output chips. The following describes the processing by the transmit processor 130. Transmitter module (TMTR) 132 processes (e.g., converts to analog form, amplifies, filters, and upconverts) the output chips and generates a modulated signal that is transmitted through antenna 134.

At a receiving station 150 R, antennas 152a-152r receive the transmitted signal, and each antenna 152 provides the received signal to a respective receiver module (RCVR) 154. An antenna may also be called “diversity,” and R receive antennas provide a multiplicity of R diversity. Each receiver module 154 processes its received signal and provides a stream of input samples to the reception processor 160. A receive processor 160 processes the input samples from all R receiver modules 154a-154r in a manner complementary to the processing performed by the transmit processor 130 and provides decoded data to the data receiver 170. The decoded data is an estimate of the traffic data sent by the transmitting station 110.

Processors 140 and 180 control the operation of processing units at transmitting station 110 and receiving station 150, respectively. Storage devices 142 and 182 store data and / or program codes used by processors 140 and 180, respectively.

Stations 110 and 150 may support 802.11b and / or 802.11g. 802.11g is backward compatible with 802.11b and supports all operating modes defined by 802.11b. Stations 110 and 150 may further support a band extension mode that supports at least one data rate that is less than the lowest data rate of 802.11b / g. A lower data rate (s) can be used to extend the range of coverage that is beneficial for some applications, such as walkie-talkies.

Table 1 lists the two lowest data rates supported by 802.11b and 802.11g and the processing for each data rate. Table 1 also lists the three data rates supported by the range extension mode and the processing for each data rate in accordance with an embodiment. In Table 1, DBPSK stands for differential on-off phase shift keying, and DQPSK stands for differential quadrature phase shift keying.

Table 1 Mode Data rate Code rate Modulation Spread coding Efficiency 802.11b / g 2 Mbps no DQPSK Dsss 2 bit / character 1 Mbps no DBPSK Dsss 1 bit / character Range Extend Mode 1 Mbps 1/2 DQPSK Dsss 1 bit / character 500 kbps 1/2 DBPSK Dsss 0.5 bit / character 250 kbps 1/4 DBPSK Dsss 0.25 bit / character

For clarity in the following description, the term “bit” refers to the number before modulation (or symbol conversion) at the transmitting station, the term “symbol” refers to the number after symbol conversion, and the term “chip” refers to the number after spread spectrum spectral coding. The term “sampling” refers to the amount before spectral coding with a narrowing of the spectrum at the receiving station.

FIG. 2 shows an embodiment of a transmit processor 130 at a transmitting station 110. A transmit processor 130 includes a pilot signal generator 210, a DSSS transmit processor 240 for 802.11b / g, a DSSS transmit processor 250 for a band extension mode, and a multiplexer (Mux) 270 .

A pilot signal generator 210 generates a pilot signal (also called a preamble or reference signal) for both 802.11b / g and range extension mode. In pilot generator 210, a symbol converter 214 receives pilot bits, converts these bits to BPSK-based modulation symbols, and provides pilot symbols to a spread spectrum device 216. For the purposes of this document, a pilot symbol is a modulation symbol for a pilot signal, a data symbol is a modulation symbol for traffic data, a modulation symbol is a complex value for a point in a signal constellation for a modulation scheme (e.g., for M-PSK or M-QAM) , and a symbol is any complex quantity. Spectrum spreading apparatus 216 spectrally spreads pilot symbols and provides chip output. In a spectrum spreading device 216, a pseudo random number (PN) code generator 222 generates a PN code sequence. In some embodiments, this may be called a Barker sequence. The 11-chip Barker sequence has a transmission rate of 11 million chips per second (Mcps) and consists of the following 11-signal sequence {+1, -1, +1, +1, -1, +1, +1, +1, -1, -1, -1}. A multiplier 224 receives pilot symbols at a rate of 1 million symbols per second (Msps) from a symbol converter 214 and a Barker sequence from a PN code generator 222. A multiplier 224 multiplies each pilot symbol by all 11 chips from the Barker sequence, generates 11 output chips for each pilot symbol, and provides a sequence of output chips for the pilot. The output bit rate is 11 times the pilot symbol rate, or 11 Mcps. Each output chip is a complex quantity that needs to be sent in one chip period T _c , which is approximately 90.9 nanoseconds (ns) for 802.11b / g.

DSSS transmit processor 240 performs spread spectrum differential modulation and spectral coding for 802.11b / g. In processor 240, differential encoder 242 receives information bits for traffic data, differential encodes information bits for DBPSK or DQPSK, and provides differential encoded bits. For DBPSK, information bit “0” leads to a phase change of 0 °, and information bit “1” leads to a phase change of 180 °. For DQPSK, a pair of information bits “00” leads to a phase change of 0 °, a pair of information bits “01” leads to a phase change of + 90 °, a pair of information bits “11” leads to a phase change of + 180 ° and a pair of information bits “ 10 "leads to a phase change of + 270 °. In some embodiments, a symbol mapper 244 converts the differential encoded bits to BPSK based modulation symbols for a data rate of 1 Mbps and QPSK based for a data rate of 2 Mbps. However, other modulation schemes for transmission rates may be used. The 244 symbol converter provides 1 Msps BPSK modulation symbols for a 1 Mbps data rate and provides 1 Msps QPSK modulation symbols for a 2 Mbit / s data rate. A spreading device 246 spectrally spreads the data symbols from the symbol converter 244 and provides chip output for traffic data.

The DSSS transmit processor 250 performs forward error correction coding (FEC), symbol conversion, and spread spectrum spectral coding for the spreading mode. At processor 250, an FEC encoder 252 receives information bits for traffic data, encodes information bits in accordance with the FEC coding scheme, and provides code bits. The FEC encoder 252 may provide for the execution of a convolutional code, a turbo code, a low-density parity check (LDPC) code, a block code, some other code, or a combination thereof. Repetition / exclusion unit 254 may either repeat or exclude some or all of the code bits to obtain the desired code rate. An interleaver 256 interleaves or reorders the code bits based on an interleaving scheme. Differential encoder 262 performs differential encoding of the interleaved bits, for example for DBPSK or DQPSK, and provides differential encoded bits. A symbol mapper 264 converts the differential-coded bits into modulation symbols based on a modulation scheme such as BPSK or QPSK. A spreading device 266 spectrally spreads the data symbols from the symbol converter 264 and provides output chips for the traffic data. The spreading devices 246 and 266 can be implemented in the same way as the spreading device 216, and can expand each data symbol with an 11-signal Barker sequence to generate 11 output chips for this data symbol.

A multiplexer 270 receives the chip output from the pilot generator 210 and the DSSS transmit processors 240 and 250, provides chip output at the desired time, provides chip output from the processor 240 if 802.11b / g mode is selected, and provides chip output from processor 250 if a range extension mode is selected.

For IEEE 802.11, data is processed through a medium access control protocol (MAC) protocol layer as MAC layer protocol data units (MPDUs). Each MPDU is processed by the Physical Layer Convergence Protocol (PLCP) and placed in the PLCP Protocol Data Unit (PPDU). Each PPDU is processed by a physical layer (as shown in FIG. 2) and transmitted through a radio channel.

3 shows a PPDU structure 300 used by 802.11b / g. For the PPDU structure 300, the PPDU 310 includes a PLCP preamble 320, a PLCP header 330, and an MPDU 340. The MPDU 340 serves as a traffic data medium for the PPDU 310 and has a variable length. The PLCP preamble 320 includes a PLCP synchronization field 322 (SYNC) and a frame start limiter (SFD) field 324. The SYNC field 322 serves as a carrier of a fixed 128-bit sequence, which can be used by the receiving station to detect a signal, enter synchronism, and other purposes. Bits in a 128-bit sequence are denoted by d ₀ , d ₁ , ..., d ₁₂₇ . The SFD field 324 serves as a carrier of a fixed 16-bit sequence that indicates the start of the PLCP header. The PLCP header 330 includes a SIGNAL field 332, which indicates the data rate for the MPDU, a SERVICE field 334, which is set to “0” to indicate IEEE 802.11 compliance, a LENGTH field 336, which indicates the amount of time (in units of milliseconds), required to send the MPDU 340, and the CRC field 338, which serves as the carrier of the CRC value, formed on the basis of the SIGNAL, SERVICE and LENGTH fields. PLCP preamble 320 and PLCP header 330 are sent at 1 Mbps using DBPSK. PLCP preamble 320 contains a total of 144 bits, which are processed to generate 144 BPSK characters. Each BPSK symbol consists of 11 elementary output signals, which are obtained by spreading coding this BPSK symbol using 11 elementary signals from the Barker sequence. 144 BPSK symbols are transmitted in 144 symbol periods, with each symbol period having a duration of 1 microsecond (μs).

For range extension mode, a PPDU structure 300 or another PPDU structure may be used. The PPDU structure for the extension mode may include a SYNC field, a CHANEST field that serves as a carrier of a fixed (e.g. 32-bit) sequence used for channel estimation, one or more signaling fields, and MPDUs.

The receiving station 150 performs synchronization entry for detecting PPDUs sent by the transmitting station 110. The synchronization entry for the range extension mode is more promising than the usual synchronization entry for 802.11b / g due to the following differences:

1. Low SNR / diversity. The required ratio of bit energy to total noise level (Eb / No) is lower, for example, for 802.11b / g it is approximately 8 decibels (dB), while the required Eb / No for the range extension mode is approximately 3 dB. The required ratio of the symbol energy to the total noise level by the diversity factor (Es / No / div) is approximately -6 dB at the lowest data rate of 250 kbit / s. It is desirable to achieve a detection better than 90% at this threshold value Es / No / div in dispersive channel conditions.

2. Entering synchronism in frequency. An 802.11b / g receiver typically performs differential demodulation. The receiver for the band extension mode may perform coherent demodulation to increase efficiency. To obtain a good estimate of the channel used for coherent demodulation, the receiver may need to determine the frequency deviation between the generators at the transmitting and receiving stations. A frequency deviation of ± 20 ppm at the receiving station is interpreted as a frequency deviation of ± 232 kHz at 5.8 GHz, which may degrade performance.

3. Channel rating. The noise power in the channel estimate should be much lower than the total noise power in order to achieve good efficiency for coherent demodulation.

FIG. 4 shows an embodiment of a reception processor 160 at a receiving station 150 in FIG. 1. At receive processor 160, a sample buffer 402 receives a stream of input samples from each of receiver modules 154a-154r. An synchronization processor 404 performs synchronization entry for the PPDUs. In the processor 404, a first detection step and a time synchronization unit 410 receives input samples from a buffer 402, detects a PPDU, and determines the timing of each detected PPDU. The second detection step and the frequency synchronization block 420 also detects the PPDUs and further estimates the frequency deviation in the input samples. The third detection step and the channel estimator 430 also detects the PPDUs and further evaluates the response of the radio channel between the transmitting station 110 and the receiving station 150. The units 410, 420 and 430 can perform processing based on a 128-bit sequence in the SYNC field from the PPDU preamble, as described below .

5 shows an embodiment of a first detection step and a time synchronization block 410 that performs signal detection using time domain correlation. Block 410 performs operations on complex-valued input samples at a sampling frequency that is greater than or equal to the transmission speed of the elementary signal. For simplicity, the following description assumes that input samples are provided at a chip rate. In the following description, “ m ” is an index for a receiving antenna, “ n ” is an index for a chip period, “ k ” is an index for a frequency element, and “ i ” is an index for 128 bits in a fixed sequence sent in the SYNC field. The symbol rate is equal to the bit rate for the pilot sent in the SYNC field. The coherent sum refers to the sum of the complex quantities, and the incoherent sum refers to the sum of the actual quantities (for example, the values of the quantities).

At a block 410, delay correlators 510a-510r receive input samples from receiver modules 154a-154r, respectively. In the delay correlator 510a for antenna 1 (or m = 1), the Barker spectral narrowing device 512a decodes the input samples with the narrowing of the spectrum using the 11-signal Barker sequence and provides narrowed symbols at the chip rate. For each chip period n , the Barker spectral narrower 512a multiplies 11 input samples for chip periods n through n -10 by 11 chips from the Barker sequence, sums the multiplication results, and provides a narrowed symbol x _m ( n ) for that chip period signal. The Barker spectrum narrowing device 512a correlates with a tunable Barker reference signal with input samples to obtain a narrowed symbol for each chip period (instead of each symbol period) and provides narrowed symbols to a symbol buffer 514a and a delay multiplier 520a.

Delay multiplier 520a generates 1-character and 2-character products with a delay of narrowed characters. In the delay multiplier 520a, the narrowed symbols are provided to two delay units 522a and 522b connected in series, each delay unit providing a delay of one symbol period T _s , which is equal to 11 chip periods, or T _s = 11 · T _c . Blocks 524a and 524b provide complex conjugation of narrowed characters from delay blocks 522a and 522b, respectively. A multiplier 526a multiplies the narrowed symbol for each chip period n by the output of block 524a and provides a 1-symbol product y _{1, m} ( n ) with a delay for this chip period. Similarly, a multiplier 526b multiplies the narrowed symbol for each chip period n by the output of block 524b and provides a 2-character delay product y _{2, m} ( n ) for that chip period.

The delay correlator for each remaining antenna processes the input samples for this antenna in the manner described above for antenna 1. Each delay correlator provides 1-character products y _{1, m} ( n ) with delay and 2-character products y _{2, m} ( n ) with delay for the associated antenna m. For each chip period n , adder 528a coherently sums the products y _{1, m} ( n ) for m = 1, ..., R from all R delay correlators 510a-510r and provides the product y ₁ ( n ) for this chip period. For each chip period n , adder 528b sums the products y _{2, m} ( n ) for m = 1, ..., R from all delay correlators 510a-510r and provides the product y ₂ ( n ) for this chip period. The products y ₁ ( n ) and y ₂ ( n ) can be expressed as:

,

, Ur (1a)

Ur (1b)

The 1-character product y _{1, m} ( n ) with a delay indicates the phase difference between the two narrowed characters x _m ( n ) and x _m ( n- T _s ), which are separated by one symbol period for antenna m. The 2-character product y _{2, m} ( n ) with a delay indicates the phase difference between the two narrowed characters x _m ( n ) and x _m ( n -2T _s ), which are separated by two symbol periods for the antenna m. 5 shows the use of 1-character and 2-character delayed products for signal detection. In general, products for any number of different delays (for example, 1, 2, 3 symbol periods, etc.) can be used to detect a signal. Using works for longer delays can improve SNR and detection efficiency. However, since frequency drift causes phase rotation in the input samples, the maximum delay can be limited by frequency drift. The amount of delay also affects the complexity of the differential correlators 530a and 530b. For example, there are 127 operations of multiplication and summation for a delay of one symbol period, 126 operations of multiplication and summation for a delay of two symbol periods, etc.

{0, …, 126}. Группа из 127 умножителей 538a соединяется с группой из 127 сумматоров 536a и также принимает 1-символьную дифференциальную последовательность, содержащую 127 известных значений. Эта последовательность образуется посредством побитового произведения первой последовательности d ₀ - d ₁₂₆ на вторую последовательность d ₁-d ₁₂₇, где d ₀-d ₁₂₇ являются 128 битами фиксированной последовательности (или битами пилот-сигнала), используемой для поля SYNC. Поскольку биты пилот-сигнала являются действительными значениями,

для i

{0, …, 126}. Каждый умножитель 538a умножает выходной сигнал ассоциированного сумматора 536a на d _i d _i+1 . Для каждого периода n элементарного сигнала сумматор 540a добавляет выходные сигналы от всех 127 умножителей 538a и предоставляет результат c ₁(n) корреляции для этого периода элементарного сигнала.Differential correlators 530a and 530b accept the products y ₁ ( n ) and y ₂ ( n ), respectively. In the differential correlator 530a of the product y ₁ ( n ), sequences of alternating delay elements 532a and 534a are provided. Each delay element 532a provides a delay of one chip period, each delay element 534a provides a delay of 10 chip periods, each pair of adjacent delay elements 532a and 534a provides a delay of 11 chip periods (which is equal to one symbol period), and the whole sequence delay elements 532a and 534a provide a delay of approximately 126 symbol periods. A group of 127 adders 536a is connected to 127 delay elements 532a. Each adder 536a sums the input signal and the output signal of the associated delay element 532a and provides an output signal y ₁ ( n −11 · i ) · y ₁ ( n −11 · i −1), where i

{0, ..., 126}. A group of 127 multipliers 538a is connected to a group of 127 adders 536a and also takes a 1-character differential sequence containing 127 known values. This sequence is formed by bitwise multiplying the first sequence d ₀ - d ₁₂₆ by the second sequence d ₁ - d ₁₂₇ , where d ₀ - d ₁₂₇ are 128 bits of a fixed sequence (or pilot bits) used for the SYNC field. Since the pilot bits are valid values,

for i

{0, ..., 126}. Each multiplier 538a multiplies the output of the associated adder 536a by d _i d _{i + 1} . For each chip period n , adder 540a adds output from all 127 multipliers 538a and provides a correlation result c ₁ ( n ) for that chip period.

{0, …, 125}. Группа из 126 умножителей 538b соединяется с группой из 126 сумматоров 536b и также принимает 2-символьную дифференциальную последовательность, содержащую 126 известных значений. Эта последовательность образуется посредством побитового произведения последовательности d ₀-d ₁₂₅ с последовательностью d ₂-d ₁₂₇. Каждый умножитель 538b умножает выходной сигнал ассоциированного сумматора 536b на d _i d _i+2 . Для каждого периода n элементарного сигнала сумматор 540b добавляет выходные сигналы от всех 126 умножителей 538b и предоставляет результат c ₂(k) корреляции для этого периода элементарного сигнала.The differential correlator 530b is similar to the differential correlator 530a. Products y ₂ ( n ) are provided with a sequence of alternating delay elements 532b and 534b that provide a delay of approximately 125 symbol periods. A group of 126 adders 536b is connected to 126 delay elements 532b. Each adder 536b sums the input signal and the output signal of the associated delay element 532b and provides an output signal y ₂ ( n −11 · i ) · y ₂ ( n −11 · i −1), where i

{0, ..., 125}. A group of 126 multipliers 538b is connected to a group of 126 adders 536b and also takes a 2-character differential sequence containing 126 known values. This sequence is formed by the bit product of the sequence d ₀ - d ₁₂₅ with the sequence d ₂ - d ₁₂₇ . Each multiplier 538b multiplies the output of the associated adder 536b by d _i d _{i + 2} . For each chip period n , adder 540b adds output from all 126 multipliers 538b and provides a correlation result c ₂ ( k ) for that chip period.

Differential correlator 530a correlates between 1-character products y ₁ ( n ) with a delay with a 1-character differential sequence. Differential correlator 530b correlates between 2-character products y ₂ ( n ) with a delay with a 2-character differential sequence. The embodiment shown in FIG. 5 assumes that the radio channel has a delay spread (i.e., scattering or pollution) from a small number of chips. Adders 536a and 536b are used to accumulate energy in this delay spread. Energy can also be heated by more elementary signals for a greater delay spread or can be skipped if the radio channel has zero or very small delay spread (for example, for a strict trajectory of a radio wave propagating within line of sight).

для L различных предполагаемых фаз и предоставляет множество из L повернутых по фазам результатов корреляции. Например, предполагаемыми фазами могут быть {0, 90°, 180°, -90°} для L=4, {0, 60°, -60°} для L=3 и т.д. L предполагаемых фаз могут выбираться для охвата возможного диапазона относительных фаз. Например, максимальный уход частоты может составлять 232 кГц для отклонения частоты в ±20 ppm и 5,8 ГГц несущей частоты. Максимальная разность фаз между 1-символьными и 2-символьными корреляциями с задержкой равна ±232 кГц умножить на 1 мкс, что приблизительно равно 90 градусам. Отсюда, если используются предполагаемые фазы 0, 60° и -60°, то по меньшей мере одна предполагаемая фаза находится в пределах 30°. Если разность фаз больше (например, вследствие использования большей задержки или большего ухода частоты), то предполагаемые фазы должны охватывать больший диапазон, вплоть до полных ±180°.Each differential correlator 530 provides a correlation result for each chip period. The phases of the correlation results c ₂ ( n ) from the differential correlator 530b may not coincide with the phases of the corresponding correlation results c ₁ ( n ) from the differential correlator 530a. A multiplier 542 multiplies each correlation result c ₂ ( n ) from the differential correlator 530b by a complex vector

for L different putative phases and provides a lot of L phase-rotated correlation results. For example, the intended phases could be {0, 90 °, 180 °, -90 °} for L = 4, {0, 60 °, -60 °} for L = 3, etc. L prospective phases may be selected to cover a possible range of relative phases. For example, the maximum frequency offset may be 232 kHz for a frequency deviation of ± 20 ppm and 5.8 GHz carrier frequency. The maximum phase difference between 1-character and 2-character correlations with a delay of ± 232 kHz is multiplied by 1 μs, which is approximately equal to 90 degrees. Hence, if prospective phases of 0, 60 ° and -60 ° are used, then at least one putative phase is within 30 °. If the phase difference is larger (for example, due to the use of a greater delay or a greater frequency drift), then the expected phases should cover a wider range, up to a full ± 180 °.

Multiplier 542 rotates c ₂ ( n ) into different phases. For each elementary period n of the elementary signal, adder 544 coherently adds the correlation result c ₁ ( n ) from adder 540a with each of the L corresponding rotated phase correlation results from multiplier 542 and provides L combined correlation results z _p ( n ) for p = 1, ... , L. If K differential correlators are used for K different delays, where K> 1, then one differential correlator can be used as a reference (without phase shift). Then one combined correlation result is obtained for each assumption corresponding to a certain phase for each of the K-1 remaining differential correlators. For example, if K = 3, then one combined correlation result is obtained for each assumption corresponding to another pair of proposed phases for two differential correlators. For L ^K-1 possible assumptions, up to L ^K-1 combined correlation results are obtained. For each elementary signal period n , block 546 calculates the squared value of each of the L combined correlation results (for K = 2), determines the largest value of the value squared among the L values of the values squared, and provides this largest value Z ( n ) of the value squared . For each chip period n, the signal detector 548 compares the largest value Z ( n ) of the squared value with the predetermined threshold value Z _th and announces the presence of PPDU if Z (n) exceeds the threshold value, or Z (n)> Z _th . Signal detector 548 continues to monitor squared values to find the maximum value and provides a chip period for that maximum value as the initial tau synchronization for the detected PPDU.

Alternatively, the results of c ₁ ( n ) and c ₂ ( n ) correlations for each elementary signal period may be incoherently combined. This can be achieved by calculating the value of c ₁ ( n ) squared, calculating the value of c ₂ ( n ) squared and summing the two squared values to obtain Z (n). The threshold value Z _th can be set to various values depending on how Z ( n ) is derived.

The threshold value Z _th used for the first detection step may be a self-tuning threshold value that changes, for example, together with the received energy E _rx for the 128-bit SYNC field. For example, the threshold value Z _th may be set equal to the received energy E _rx times the scale factor S ₁ , or Z _th = E _rx · S ₁ . The use of normalized received energy for signal detection results in similar detection efficiency for a wide range of received signal levels. Computer simulation shows that a detection probability of about 90% and a false alarm rate of less than 1% can be achieved for 2 equal uncorrelated Rayleigh channels with a total SNR of -3 dB using S ₁ = 22. Detection probability refers to the likelihood of an error-free declaration of the presence of PPDUs when the PPDU is sent. The false alarm rate refers to the likelihood of a false PPDU announcement when nothing is sent. A compromise between the probability of detection and the frequency of false alarms can be achieved by choosing the appropriate value for the scale factor S ₁ .

6 shows an embodiment of a second detection step and a frequency synchronization block 420 that performs signal detection using frequency domain processing. For this embodiment, block 420 includes R frequency drift estimation blocks 610a through 610r for R receive antennas. Each frequency drift estimation unit detects energies in different frequency resolution elements to determine frequency drift in the input samples from the associated antenna.

For receive antenna 1 ( m = 1), the symbol buffer 516a provides N narrowed symbols that are spaced by 11 chip periods (or one symbol period), starting with the initial tau synchronization provided by the time synchronization block 410. The first narrowed character is thus time aligned with the best timing assumption from the step of entering time synchronism. In general, N can be any integer that is a power of two and does not exceed 128, for example, N can be 32, 64, or 128. In block 610a of the frequency drift, a group of N multipliers 612 receives N narrowed characters from the character buffer 514a and N corresponding bits of the pilot signal in a 128-bit sequence. Each multiplier 612 multiplies the narrowed symbol by its pilot bit to remove modulation from this narrowed symbol. An N-point Fast Fourier Transform (FFT) unit 620 receives N output signals from N multipliers 612, performs an N-point FFT on these N output signals, and provides N frequency domain values for N frequency bins. A group of N blocks 622 receives N frequency domain values from an FFT block 620. Each block 622 calculates the squared value of its frequency domain value and provides the detected energy for the corresponding frequency resolution element k .

After modulation is removed using multipliers 612, the N output signals from these multipliers can have a periodic component. This periodic component is due to the frequency drift in the generator at the receiving station 150, which leads to the fact that the received signal is not converted with decreasing frequency exactly into DC. FFT unit 620 provides spectral sensitivity of N output signals from multipliers 612. The frequency resolution element k with the highest detected energy indicates a frequency drift for input samples from antenna m .

The frequency drift estimation unit for each remaining receiving antenna processes the narrowed symbols for this antenna in the manner described for antenna 1. A group of N adders 632 receives R sets of N detected energies from R frequency drift estimation blocks 610a-610r for R receiving antennas. Each adder 632 sums the detected energies from all R frequency drift estimation blocks 610a-610r for the associated frequency resolution element k and provides the total detected energy E ( k ) for this frequency resolution element. Selector 634 selects the largest total detected energy E _max ( k ) among N total detected energies for N frequency resolution elements. Signal detector 636 compares the largest total detected energy E _max ( k ) with a predetermined threshold value E _th , announces signal detection if E _max ( k ) is greater than the threshold value E _th , and provides a frequency resolution element with the highest total detected energy as estimated deviation k _os frequency. The threshold value E _th can be set, for example, to the received energy E _rx for the 128-bit SYNC field multiplied by the scale factor S ₂ , or E _m = E _rx · S ₂ .

The embodiment shown in FIG. 6 uses an N-point FFT, where N 12 128. If N = 64, which is the FFT size commonly used for 802.11b and 802.11g for OFDM, then the distance between adjacent frequency bins is 15.625 kHz for a symbol rate of 1 Msps and the inaccuracy in estimating frequency drift is half the distance between bins , or 7.812 kHz. This inaccuracy can be reduced by interpolating and / or using a larger 128-point FFT.

The gain from processing for coherent accumulation by FFT is approximately 18 dB for N = 64. The worst loss of coherent accumulation is about 4 dB, which occurs when the actual frequency drift is exactly between the two frequency resolution elements. A minimum total combined SNR of almost 14 dB can be achieved for N = 64. Most coherent storage losses can be recovered by summing the detected energies for pairs of neighboring frequency resolution elements (for example, similar to the summation performed by adders 536a and 536b in FIG. 5) before selecting the highest total detected energy. Summing the detected energies for adjacent pairs of frequency resolution elements increases the likelihood of detecting at the cost of a small increase in the frequency of false alarms. The detection probability is better than 90% with an SNR of -7 dB, and better than 99.9% with an SNR of -4 dB can be achieved using the threshold value S ₂ = 8. The probability of false alarms is less than 0.5% for the second stage of detection, resulting in a total frequency of false alarms of 5 · 10 ^-5 for the first and second stages of detection.

Multipath propagation can worsen the probability of detection, since all the energy is not used in the second stage of detection (due to the FFT operating at a distance between symbols instead of the distance between chips). In an embodiment, increased efficiency can be achieved for the second detection step by performing a 128-point FFT, and hence integration over the entire 128-bit sequence for the SYNC field. In another embodiment, one 64-point FFT may be performed for the first half of the 128-bit sequence, as described above, another 64-point FFT may be performed for the second half of the 128-bit sequence, and the detected energies for the two FFTs may be incoherently summed by adders 632.

In another embodiment, the frequency offset estimates of the input samples are correlated with a known 128-bit sequence for the various estimated frequency offsets. For each assumed frequency drift, the input samples are rotated by this frequency drift, rotated samples are correlated with a 128-bit sequence, the correlation result is compared again with the threshold value and signal detection is announced if the correlation result exceeds the threshold value. Correlation can be performed in the time domain using a finite impulse response (FIR) filter device or in the frequency domain using the FFT-IFFT operation. The estimate of the frequency drift is determined by the assumed frequency deviation, which leads to the greatest correlation result exceeding the threshold value.

In yet another embodiment, frequency drift estimates, the input samples are first coded to a narrowed spectrum to obtain narrowed symbols at a chip rate, as shown in FIG. 5. The narrowed symbols are then multiplied by the corresponding pilot bits to remove pilot modulation. The resulting symbols are used to form 1-character and 2-character delayed products using, for example, the delay multiplier 520a in FIG. 5. Artworks with a delay for each delay are processed to form a complex value for this delay. For each delay d, where d = {1, 2}, delayed d-symbolic products are provided to a group of 10 series-connected delay elements separated by elementary signals (for example, similar to delay elements 722 in FIG. 7) to obtain d-symbolic products with a delay at 11 different intervals of elementary signals. delayed d-character products for each chip interval are coherently summed over the SYNC field (for example, using switches 724 and drives 730 in FIG. 7). 11 summarized results for 11 elementary signal intervals can be combined (for example, using summation of the differential-weighted signals of each channel) to form a complex value V _d for delay d. The phase difference between the complex values of V ₁ and V ₂ for 1-character and 2-character delays can be calculated and used to derive the frequency drift. R receive antennas can be combined in various ways, for example, delayed products can be combined along antennas, as shown in FIG. 5, complex values for different antennas can be combined for each delay d, etc. More than two delays and / or a large delay can also be used for frequency analysis. A larger delay results in a larger phase difference, which provides better resolution for frequency drift. However, a large delay can lead to an error, for example, a phase shift greater than 180 ° can be interpreted as a negative shift less than 180 °. For a given number of delays and a given maximum frequency drift, a plurality of delays can be selected to optimize resolution without error.

Regardless of the technique used for frequency analysis, the estimated departure of k _os frequency from the frequency synchronization block 420 typically contains a residual frequency deviation. To estimate this residual frequency deviation, the first 11-tap channel estimate can be derived based on the first 64 bits of the SYNC field (for example, as described below), the second 11-tap channel estimate can be derived based on the last 64 bits of the SYNC field, with both channel estimates output with the excluded departure of k _os frequency. Based on the tap, the product of the second channel estimate and the complex conjugation of the first channel estimate can be calculated. 11 resulting products can be coherently summed to obtain the phase difference between the two channel estimates. Comparison with the threshold value can be performed on (1) each channel tap before calculating the product and / or (2) each product before summing the products. Comparison with a threshold value removes channel taps with low energy below a predetermined threshold value. The residual frequency deviation can be estimated based on the phase difference between the two channel estimates and can be provided to the filter 452 and / or the frequency correction unit 454 and used to correct the synchronization and / or frequency of the input samples (not shown in FIG. 4). This update of the k _os frequency _drift with an estimate of the residual frequency deviation can improve demodulation efficiency.

7 shows an embodiment of a third detection step and a channel estimator 430 that performs signal detection using time-domain processing. For this embodiment, block 430 includes R channel estimator blocks 710a through 710r for R receive antennas. Each channel estimator may derive a channel impulse response estimate containing channel taps that are spaced at sampling frequency intervals. For example, up to 11 channel taps can be received, separated by one chip, if the narrowed characters are obtained at the chip rate, up to 22 channel taps can be received, separated by half the chip, if the narrowed characters are received at twice the chip rate (or chip x 2), etc. For the embodiment shown in FIG. 7, each channel estimation unit derives an 11-tap channel impulse response estimate in the chip interval for the associated antenna.

для удаления отклонения k _os частоты, определенного блоком 420 вхождения в синхронизм по частоте. Умножитель 712 предоставляет символы с частотной коррекцией на скорости передачи элементарного сигнала группе из 10 последовательно соединенных элементов 722 задержки. Каждый элемент 722 задержки обеспечивает задержку в один период элементарного сигнала. Группа из 11 переключателей 724 соединяется с выходом умножителя 712 и выходами 10 элементов 722 задержки. Переключатели 724 задействуются для одного периода элементарного сигнала в каждом периоде символа и предоставляют 11 символов с частотной коррекцией для этого периода символа. Управляющий сигнал для переключателей 724 определяется начальной синхронизацией tau от блока 410 вхождения в синхронизм по времени и формируется из условия, чтобы символ с частотной коррекцией из пятого элемента 722 задержки (который предназначен для центрального отвода 11-отводной оценки импульсной характеристики канала) соответствовал наилучшему предположению синхронизации, предоставленному этапом вхождения в синхронизм по времени.At a channel estimator 710a for antenna 1 ( m = 1), a multiplier 712 multiplies the narrowed symbols for antenna m by a complex vector

to remove the frequency deviation k _{os of the} frequency determined by the frequency synchronization block 420. A multiplier 712 provides frequency corrected symbols for the elementary signal rate to a group of 10 delayed elements 722 connected in series. Each delay element 722 provides a delay of one chip period. A group of 11 switches 724 is connected to the output of the multiplier 712 and the outputs 10 of the delay elements 722. Switches 724 are activated for one chip period in each symbol period and provide 11 symbols with frequency correction for that symbol period. The control signal for the switches 724 is determined by the initial synchronization tau from the time synchronization block 410 and is formed from the condition that the frequency-corrected symbol from the fifth delay element 722 (which is intended for the central tap of the 11-tap channel impulse response estimate) corresponds to the best synchronization assumption provided by the step of entering synchronism in time.

Channel estimation is performed over a predetermined time interval W, which is selected to achieve adequate SNR or quality for channel estimates. The time interval W may be M symbol periods of length, where M may be, for example, M> 31. A group of 11 multipliers 726 receives a pilot bit d _i for each symbol period in which channel estimation is performed. Each multiplier 726 multiplies the output of the corresponding switch 724 by the pilot bit d _i , removes the modulation by the pilot bit and provides its output signal to the corresponding accumulator 730. A group of 11 accumulators 730 is reset to zero at the beginning of the channel estimation. Each drive 730 coherently sums the output of the corresponding multiplier 726 during the time interval W. A group of 11 switches 732 is connected to a group of 11 drives 730. The switches 732 are activated at the end of the time interval W and provide 11 channel taps h _{m, 0} - h _{m, 10} to estimate the channel impulse response for antenna m . This channel estimate may be used to demodulate data, as described below. A group of 11 blocks 734 receives 11 channel taps, and each block 734 calculates the squared value of its channel tap. An adder 736 summarizes the output from all 11 blocks 734 and provides total energy for all channel taps for antenna m . Alternatively, the output of each block 734 may be compared with a threshold value, and an adder 736 may only summarize output signals that exceed the threshold value. The threshold value can be set to a predetermined percentage of the total energy for all 11 channel taps.

The channel estimator for each remaining receiving antenna processes the narrowed symbols for that antenna in the manner described above for antenna 1. Adder 738 sums the total energies for all R channel estimators 710a-710r and provides the total energy H for all R antennas. The signal detector 740 compares the total energy H with a predetermined threshold value H _th and announces the detection of a signal if H exceeds the threshold value H _th . The threshold value H _th can be set, for example, to the received energy E _rx for the 128-bit SYNC field multiplied by the scale factor S ₃ , or H _th = E _rx · S ₃ .

A detection probability of greater than 99% and a false alarm rate of less than 10 ^-5 can be achieved with an SNR of -4 dB using a threshold value of S ₃ = 14. A total false alarm rate of less than 10 ^-9 can be achieved with all three stages of detection. This assumes that the three stages of detection are uncorrelated, since three types of signal processing are used for the three stages.

For the above embodiments, signal detection can be achieved based on time domain correlation (FIG. 5), frequency domain processing (FIG. 6) and time domain processing (FIG. 7). All three types of signal processing can be used to provide good detection efficiency (for example, high detection probability and low false alarm rate) for poor channel conditions (for example, low SNR). Any combination of signal processing for signal detection may also be used.

5, 6 and 7 show certain embodiments of signal detection, time synchronism, frequency synchronism, and channel estimation, which may be performed in other ways. For example, signal detection and time synchronization can only be performed using a 1-bit delayed differential correlator 530a. A combination of techniques may also be used. For example, input samples can be rotated by a small number (for example, two) of the estimated frequency drifts. The residual frequency deviation is smaller for one of the assumed frequency drifts, so that Barker narrowing (or coherent accumulation) coding can be performed over a longer duration (for example, 22 chips). Narrowed symbols from longer coherent accumulation may be provided to the delay multiplier and differential correlator shown in FIG. Signal detection can be achieved for a smaller effective SNR, since coherent accumulation is performed over a longer duration.

5, 6, and 7 show typical signal processing by blocks 410, 420, and 430, respectively. Processing may be implemented in various ways using hardware, software, and / or firmware. For example, blocks 410, 420, and 430 may be implemented using dedicated hardware or may share hardware. A digital signal processor (DSP) and / or some other type of processor may perform time division multiplexing processing for blocks 410, 420, and 430. A sample buffer 402, a character buffer 514, and / or some other buffer may be used to buffer data for processing.

Returning to FIG. 4, after the PPDU is detected, a determination is made whether the received PPDU is intended for 802.11b / g or range extension mode, for example, based on the PLCP preamble and / or PLCP header. A DSSS receive processor 440 processes the received PPDU if it is for 802.11b / g. A DSSS receive processor 450 processes the received PPDU if it is intended for range extension mode.

A DSSS receive processor 440 performs spectral narrowing spectral coding and demodulation for 802.11b / g. In processor 440, the multi-tap coherent receiver / corrector 442 encodes the constricted input samples using a Barker sequence, corrects the constricted symbols based on channel estimates, combines signal components over R receive antennas, and provides detected symbols. A demodulator (Demod) 444 converts the detected symbols based on a modulation scheme (eg, BPSK or QPSK) used for transmission, performs differential decoding, and provides output bits that are estimates of information bits sent by transmitting station 110.

A DSSS receive processor 450 performs spectral narrowing spectral coding, demodulation, and FEC decoding for the spreading mode. At processor 450, a filter 452 filters the input samples for each receive antenna to remove out-of-band noise and interference. Filter 452 can also re-sample input samples for each receive antenna (1) to convert the sampling frequency from the sampling frequency to the chip rate and / or (2) to compensate for the timing offset from the received PPDU. For 802.11g, input samples typically have speeds several times higher than the OFDM chip rate of 20 MHz. In this case, the filter 452 can re-sample from repeatedly 20 MHz to either 11 MHz for a multi-tap coherent receiver separated by chips, or 22 MHz for a multi-tap coherent receiver split by halves. The local oscillator (LO) signal used for down-conversion and the clock used to form input samples are usually obtained from the same reference frequency generator. In this case, the frequency deviation in the clock signal can be determined based on the frequency deviation k _os determined by the frequency synchronization block 420 for the LO signal. Then, the timing offset in the input samples can be determined based on the offset k _os frequency and carrier frequency. Filter 452 may periodically adjust ± T _adj based on the departure of k _os frequency, where T _adj may be part of the sampling period.

In an embodiment, filter 452 is implemented as a multiphase filter, consisting of a block of N base filters, where N> 1. Each base filter is associated with a specific set of coefficients for a specific time offset. In a typical design, filter 452 includes 11 FIR filters, where each FIR filter has four taps. A different base filter can be used to create each subsequent output sample. If the frequency drift is zero, then 11 basic filters can be cyclically traversed in the same order, where every 11th sample is formed from the same basic filter. To compensate for synchronization drift, a given base filter can be skipped and the next base filter can be used instead, or the same base filter can be used for two consecutive output samples. Thus, adjustment of synchronization can be achieved by selecting the appropriate base filter in use.

Frequency correction unit 454 removes frequency drift in time-adjusted samples for each receiving antenna. Block 454 may be implemented using a numerically controlled generator (NCO) and a complex multiplier similar to multiplier 712 in FIG. 7. The NCO generates a vector rotating at a frequency offset k _os provided by the frequency synchronization block 420. A multiplier multiplies time-adjusted samples for each receiving antenna by a vector and provides frequency-corrected samples for that antenna.

A multi-tap coherent receiver / spectral narrower 456 performs frequency-coherent coherent detection of the samples using channel estimates and combines the signal components from the receiving antennas and multipath. A multi-tap coherent receiver 456 multiplies the frequency-corrected samples for each receiving antenna by 11 channel taps provided by the channel estimator 430 for that antenna. The multi-tap coherent receiver / narrower 456 also performs narrowing coding using a Barker sequence, accumulates narrowed symbols for all R antennas, and provides detected symbols. In an embodiment, the channel estimates for the R receive antennas are derived once based on the SYNC field and possibly other fields of the received PPDU, and these channel estimates are used for the entire received PPDU. For this embodiment, the multi-tap coherent receiver 456 is not a radio channel snooping on the received PPDU. In another embodiment, the channel estimates are updated using hard decisions obtained from the detected symbols and / or decisions obtained by transcoding and reconverting the output of the FEC decoder 464.

The phase correction block 458 removes the phase error in the detected symbols. The phase error is due to a residual frequency deviation that occurs from the receiver 160 without phase synchronization.

FIG. 8 shows a block diagram of an embodiment of a phase correction block 458. At block 458, a multiplier 812 rotates each detected symbol from the multi-tap coherent receiver 456 to the reference phase θ _ref ( t ) and provides a corresponding phase corrected symbol. Block 814 generates a hard decision (e.g., +1 or -1) for each phase corrected symbol. A multiplier 816 multiplies each detected symbol by a corresponding hard decision and provides a product for that detected symbol. Block 818 calculates a moving average of the products from the multiplier 816 and provides an averaged product. For each symbol period, block 820 normalizes and matches the averaged product and provides the reference phase θ _ref ( t ) for the detected symbol for this symbol period t . The reference phase, thus, can be derived by determining the average values in the interval of detected characters. The determination of the mean values may be intended to explain the fact that the phase information from the known pilot symbols in the SYNC field is more reliable, but may not be relevant, while the phase information for the detected symbols may not be reliable, but is more relevant .

Returning to FIG. 4, a demodulator 460 performs phase-coherent symbol demodulation. For BPSK, demodulator 460 can provide the real part of each phase corrected symbol as a demodulated symbol, which is an estimate of the data symbol sent by transmitting station 110. For other modulation schemes, demodulator 460 can provide a modulation symbol that is most likely sent for each phase corrected symbol , as a demodulated symbol.

Reversed interleaver 462 interleaves demodulated symbols back in a manner complementary to the interleaving performed by interleaver 256 of FIG. 2. The FEC decoder 464 decodes the deinterleaved symbols in a manner complementary to the encoding performed by the FEC encoder 252 in FIG. 2 and provides output. A multiplexer 470 receives output from DSSS receive processors 440 and 450, provides output from a DSSS receive processor 440 if the received PPDU is for 802.11b / g, and provides output from the DSSS receive processor 450 if the received PPDU is for range extension mode .

FIG. 4 shows a specific embodiment of a receive processor 160 for 802.11b / g and range extension mode. The processor 160 may also be implemented using other designs, and this is within the scope of the invention. In general, the processing by the DSSS reception processor 440 is complementary to the processing by the DSSS transmission processor 240 at the transmitting station 110, and the processing by the DSSS reception processor 450 is complementary to the processing by the DSSS transmission processor 250. FIG. 4 shows typical designs of DSSS reception processors 440 and 450, which may include other and / or different processing units not shown in FIG. 4.

9 shows a process 900 for performing signal detection for a first step. The input samples are coded with a narrowing of the spectrum using a code sequence to generate narrowed characters, for example, at a bit rate (block 912). Products of narrowed characters are generated for at least two different delays (block 914). Each piece is formed on the basis of a narrowed symbol and complex conjugation of another narrowed symbol, which is at least one symbol period earlier. For example, 1-character delayed works and 2-character delayed works can be formed, as shown in FIG. 5, with each 1-character delayed work formed with two narrowed characters that are separated by one character period, and each 2- a symbolic product with a delay formed with two narrowed characters that are separated by two periods of the character.

A correlation is then made between the products for each delay and the known values for that delay (block 916). Known values may be products of pilot bits, as shown in FIG. The adjacent products for each delay can be summed before correlation is performed to calculate the delay spread in the radio channel, which is also shown in FIG. The correlation results for all delays are combined (block 918). The correlation results for the 2-character delay can be rotated through a plurality of estimated phases and combined with the corresponding correlation results for a 1-character delay, and the combined correlation results with the largest value among the many estimated phases can be selected, as shown in FIG. 5. Alternatively, the correlation results for different delays may incoherently combine.

Then, based on the combined correlation results, the presence of the signal / transmitted data is detected, for example, by comparing the combined correlation results with a self-tuning threshold value Z _th , which is a function of the received energy (step 920). The signal synchronization is also determined based on the combined correlation results, for example, by detecting a spike in the combined correlation results (step 922).

10 shows a process 1000 for performing signal detection with several (eg, three) steps using different types of signal processing. The self-adjusting thresholds used to detect the signal in steps are derived from the received energy for the symbol interval (step 1012). Signal detection for the first step is performed using correlation in the time domain and the first threshold value (step 1014). For the first stage, symbol products may be generated for at least one delay, correlation between the products for each delay and known values may be performed, and detection may be announced based on the correlation results for at least one delay and the first threshold value. Signal detection for the second step is performed using frequency domain processing and a second threshold value (step 1016). For the second stage, energies for a plurality of frequency resolution elements can be determined, and detection can be announced based on the energies for these frequency resolution elements and a second threshold value. Signal detection for the third step is performed using time-domain processing and a third threshold value (step 1018). A plurality of channel taps can be output to estimate the impulse response of the channel, and detection can be announced based on channel taps and a third threshold. The presence of a signal is announced based on the results of the first, second, and third stages (block 1020).

11 shows a process 1100 for receiving transmitted data or PPDUs. The timing of the input samples is adjusted to obtain time-adjusted samples (block 1112). The synchronization adjustment can be performed using a multiphase filter and / or based on the drift of the frequency determined at the time of entering the synchronism in frequency. The frequency drift in time-adjusted samples is deleted to obtain frequency-corrected samples (block 1114). Frequency-corrected samples are processed using channel estimation (eg, using a multi-tap coherent receiver) to obtain detected symbols (block 1116). The phases of the detected symbols are corrected to obtain phase corrected symbols (block 1118). For phase correction, a reference phase may be output based on the detected symbols, and phases of the detected symbols may be adjusted based on the reference phase. Phase corrected symbols are demodulated to obtain demodulated symbols (block 1120). The demodulated symbols are deinterleaved (block 1122), and the deinterleaved symbols are decoded to obtain decoded data (block 1124).

The processes depicted and described with respect to FIGS. 9-11 can be implemented as functions performed by the processor 160. The individual blocks may contain instructions that are executed by the processor 160.

The techniques described here can be implemented by various means. For example, these techniques may be implemented in hardware, firmware, software, or a combination thereof. For hardware implementations, the processing units used to perform signal detection, synchronization, and demodulation can be implemented in one or more specialized integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), and programmable logic devices ( PLD), Field Programmable Gate Arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, electronic devices, and other electronic components designed for perform the functions described here, or combinations thereof.

For software implementation, techniques can be implemented using modules (e.g., procedures, functions, and so on) that perform the functions described here. Software codes may be stored in a storage device (e.g., storage device 182 in FIG. 1) and executed by a processor (e.g., processor 160 and / or processor 180). The storage device may be implemented within the processor or may be external to the processor.

The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited by the embodiments shown in this document, but rather should correspond to the broadest possible scope consistent with the principles and new features disclosed in this document.

Claims (40)

1. A method for performing signal detection, comprising the steps of:
forming a first sequence of products of the first character with a delay for a sequence of characters, wherein each product of the first character with a delay is obtained as a result of at least the operation of the first product based on the first and second characters of a sequence of characters that are separated by a delay of the first character;
forming a second sequence of products of the second character with a delay for a sequence of characters, with each product of the second character with a delay obtained as a result of at least the second product based on the first and third characters of a sequence of characters that are separated by a delay of the second character;
performing a correlation between the first sequence and the first known values to obtain the results of the first correlation;
performing a correlation between the second sequence and the second known values to obtain the results of the second correlation; and
detect the presence of a signal based on the results of the first and second correlations. 2. The method according to claim 1, in which the operations of the first and second products comprise multiplying the first character by complex conjugations of the second and third characters, respectively. 3. The method according to claim 1, wherein the delays of the first and second symbols differ by more than one symbol period. 4. The method according to claim 1, wherein detecting the presence of a signal based on the results of the first and second correlations comprises the steps of performing a phase rotation of the results of the second correlation; combine the results of the second correlation with a phase rotation with the results of the first correlation; and detecting the presence of a signal based on the combined correlation results. 5. The method according to claim 1, wherein detecting the presence of a signal based on the results of the first and second correlations comprises the steps of combining the results of the first and second correlations; and comparing the combined correlation results with a threshold value derived from the calculated received energy of at least two symbols. 6. A method for performing signal detection comprising the steps of generating a plurality of first delayed product sequences of a first character for a plurality of character sequences, each product of a first delayed character for each first sequence being obtained as a result of a first product operation based on the first and second characters from one of a plurality of character sequences that are separated by a delay of the first character;
generating a plurality of second sequences of products of the second symbol with a delay for a plurality of symbol sequences, wherein each product of the second symbol with a delay for each second sequence is obtained as a result of the operation of the second product based on the first and third symbols from one of the plurality of symbol sequences that are separated by a delay of the second symbol;
combine many of the first sequences;
performing a correlation between the combined set of first sequences and the first known values to obtain the results of the first correlation;
combine many second sequences;
performing a correlation between the combined set of second sequences and second known values to obtain the results of the second correlation; and detecting the presence of a signal based on the results of the first and second correlations. 7. The method according to claim 6, in which the operations of the first and second products comprise multiplying the first character by complex conjugations of the second and third characters, respectively. 8. The method according to claim 6, in which the delays of the first and second symbols differ by more than one symbol period. 9. The method according to claim 6, in which detecting the presence of a signal based on the results of the first and second correlations comprises the steps of performing a phase rotation of the results of the second correlation; combine the results of the second correlation with a phase rotation with the results of the first correlation; and detecting the presence of a signal based on the combined correlation results. 10. The method according to claim 6, in which detecting the presence of a signal based on the results of the first and second correlations comprises the steps of combining the results of the first and second correlations; and comparing the combined correlation results with a threshold value derived from the calculated received energy of at least two symbols. 11. A device for performing signal detection, comprising logic for generating a first sequence of products of the first character with a delay for a sequence of characters, each product of the first character with a delay is obtained as a result of at least the operation of the first product based on the first and second characters of the sequence of characters that are separated delay of the first character;
logic for generating a second sequence of products of the second character with a delay for the sequence of characters, with each product of the second character with a delay resulting from at least the operation of the second product based on the first and third characters of the sequence of characters that are separated by a delay of the second character;
logic for performing a correlation between the first sequence and the first known values to obtain the results of the first correlation;
logic for performing correlation between the second sequence and second known values to obtain the results of the second correlation;
and logic for detecting the presence of a signal based on the results of the first and second correlations. 12. The device according to claim 11, in which the operations of the first and second products comprise multiplying the first character by complex conjugations of the second and third characters, respectively. 13. The device according to claim 11, in which the delays of the first and second symbols differ by more than one symbol period. 14. The device according to claim 11, in which the logic for detecting the presence of a signal based on the results of the first and second correlations comprises logic for performing a phase rotation of the results of the second correlation; logic for combining the results of the second correlation with a phase rotation with the results of the first correlation; and logic for detecting the presence of a signal based on the combined correlation results. 15. The device according to claim 11, in which the logic for detecting the presence of a signal based on the results of the first and second correlations comprises logic for combining the results of the first and second correlations; and logic for comparing the combined correlation results with a threshold value derived from the calculated received energy of at least two symbols. 16. A device for performing signal detection, comprising logic for generating a plurality of first sequences of products of the first character with a delay for a plurality of sequences of characters, each product of the first character with a delay for each first sequence is obtained as a result of the operation of the first product based on the first and second characters of one from a plurality of character sequences that are separated by a delay of the first character;
logic for generating a plurality of second sequences of products of the second symbol with a delay for a plurality of sequences of symbols, and each product of the second symbol with a delay for each second sequence is obtained as a result of the operation of the second product based on the first and third characters from one of the many sequences of characters that are separated by a delay of the second character;
logic for combining many of the first sequences;
logic for performing correlation between the combined set of first sequences and first known values to obtain the results of the first correlation;
logic for combining many second sequences;
logic for performing correlation between the combined set of second sequences and second known values to obtain the results of the second correlation;
logic for detecting the presence of a signal based on the results of the first and second correlations. 17. The device according to clause 16, in which the operations of the first and second products comprise multiplying the first character by complex conjugations of the second and third characters, respectively. 18. The device according to clause 16, in which the delays of the first and second symbols differ by more than one period of the symbol. 19. The device according to clause 16, in which the detection of the presence of a signal based on the results of the first and second correlations contains logic for performing a phase rotation of the results of the second correlation; logic for combining the results of the second correlation with a phase rotation with the results of the first correlation; and logic for detecting the presence of a signal based on the combined correlation results. 20. The device according to clause 16, in which the logic for detecting the presence of a signal based on the results of the first and second correlations contains logic for combining the results of the first and second correlations; and logic for comparing the combined correlation results with a threshold value derived from the calculated received energy of at least two symbols. 21. A device for performing signal detection, comprising
means for generating a first sequence of products of the first character with a delay for a sequence of characters, wherein each product of the first character with a delay is obtained as a result of at least an operation of the first product based on the first and second characters of a sequence of characters that are separated by a delay of the first character;
means for generating a second sequence of products of the second character with a delay for the sequence of characters, each product of the second character with a delay is obtained as a result of at least the operation of the second product based on the first and third characters of the sequence of characters that are separated by a delay of the second character;
means for performing a correlation between the first sequence and the first known values to obtain the results of the first correlation;
means for performing a correlation between the second sequence and the second known values to obtain the results of the second correlation;
and means for detecting the presence of a signal based on the results of the first and second correlations. 22. The device according to item 21, in which the operations of the first and second products comprise multiplying the first character by complex conjugations of the second and third characters, respectively. 23. The device according to item 21, in which the delays of the first and second symbols differ by more than one period of the symbol. 24. The device according to item 21, in which means for detecting the presence of a signal based on the results of the first and second correlations comprises means for performing a phase rotation of the results of the second correlation; means for combining the results of the second correlation with a phase rotation with the results of the first correlation; and means for detecting the presence of a signal based on the combined correlation results. 25. The device according to item 21, in which the means for detecting the presence of a signal based on the results of the first and second correlations comprises means for combining the results of the first and second correlations; and means for comparing the combined correlation results with a threshold value derived based on the calculated received energy of at least two symbols. 26. A device for performing signal detection, comprising means for generating a plurality of first sequences of products of the first character with a delay for a plurality of sequences of characters, each product of the first character with a delay for each first sequence resulting from the operation of the first product based on the first and second characters of one from a plurality of character sequences that are separated by a delay of the first character;
means for generating a plurality of second sequences of products of the second symbol with a delay for a plurality of symbol sequences, wherein each product of the second symbol with a delay for each second sequence is obtained as a result of the operation of the second product based on the first and third symbols from one of the many sequences of symbols that are separated by a delay of the second character;
means for combining many of the first sequences;
means for performing correlation between the combined plurality of first sequences and first known values to obtain results of a first correlation;
means for combining multiple second sequences;
means for performing a correlation between the combined plurality of second sequences and second known values to obtain second correlation results;
means for detecting the presence of a signal based on the results of the first and second correlations. 27. The device according to p. 26, in which the operations of the first and second products contain the multiplication of the first character by complex conjugation of the second and third characters, respectively. 28. The device according to p, in which the delays of the first and second characters differ by more than one period of the character. 29. The device according to p, in which the detection of the presence of a signal based on the results of the first and second correlations comprises means for performing a phase rotation of the results of the second correlation; means for combining the results of the second correlation with a phase rotation with the results of the first correlation; and means for detecting the presence of a signal based on the combined correlation results. 30. The device according to p, in which the means for detecting the presence of a signal based on the results of the first and second correlations includes means for combining the results of the first and second correlations; and means for comparing the combined correlation results with a threshold value derived based on the calculated received energy of at least two symbols. 31. A computer-readable storage medium containing software codes stored on it, which, when executed by a processor, instructs the processor to perform a method for performing signal detection, the software codes comprising software codes for generating a first sequence of products of the first character with a delay for the character sequence, wherein each product of the first character with a delay is obtained as a result of at least the operation of the first product and based on the first and second symbol sequence of symbols which are separated by a delay of the first symbol;
software codes for generating a second sequence of products of the second symbol with a delay for a sequence of symbols, wherein each product of the second symbol with a delay is obtained as a result of at least an operation of the second product based on the first and third symbols of a sequence of symbols that are separated by a delay of the second symbol;
software codes for performing correlation between the first sequence and the first known values to obtain the results of the first correlation;
software codes for performing correlation between the second sequence and second known values to obtain the results of the second correlation; and
software codes for detecting the presence of a signal based on the results of the first and second correlations. 32. The computer-readable storage medium of claim 31, wherein the operations of the first and second products comprise multiplying the first character by complex conjugations of the second and third characters, respectively. 33. The computer-readable storage medium of claim 31, wherein the delays of the first and second symbols differ by more than one symbol period. 34. The computer-readable storage medium of claim 31, wherein the software codes for detecting a signal based on the results of the first and second correlations comprise software codes for performing a phase rotation of the results of the second correlation;
software codes for combining the results of the second correlation with a phase rotation with the results of the first correlation; and software codes for detecting signal presence based on combined correlation results. 35. The computer-readable storage medium of claim 31, wherein the software codes for detecting a signal based on the results of the first and second correlations comprise software codes for combining the results of the first and second correlations; and software codes for comparing the combined correlation results with a threshold value derived from the calculated received energy of at least two symbols. 36. A computer-readable storage medium containing software codes stored on it, which, when executed by a processor, instructs the processor to perform a signal detection method, the software codes comprising software codes for generating a plurality of first sequences of products of the first character with a delay for a plurality of sequences of characters , and each product of the first character with a delay for each first sequence is obtained as a result of the operation of the first product based on the first and second characters from one of the many sequences of characters that are separated by a delay of the first character;
software codes for generating a plurality of second sequences of products of the second character with a delay for a plurality of sequences of characters, and each product of the second character with a delay for each second sequence is obtained as a result of the operation of the second product based on the first and third characters from one of the many sequences of characters that are separated delay of the second character;
software codes for combining a plurality of first sequences;
software codes for performing correlation between the combined set of first sequences and first known values to obtain the results of the first correlation;
software codes for combining multiple second sequences;
software codes for performing correlation between the combined plurality of second sequences and second known values to obtain second correlation results;
software codes for detecting the presence of a signal based on the results of the first and second correlations. 37. The computer-readable storage medium according to claim 36, wherein the operations of the first and second products comprise multiplying the first character by complex conjugations of the second and third characters, respectively. 38. The computer-readable storage medium of claim 36, wherein the delays of the first and second symbols differ by more than one symbol period. 39. The computer-readable storage medium according to claim 36, wherein the software codes for detecting a signal based on the results of the first and second correlations comprise software codes for performing a phase rotation of the results of the second correlation;
software codes for combining the results of the second correlation with a phase rotation with the results of the first correlation; and software codes for detecting signal presence based on combined correlation results. 40. A computer-readable storage medium according to claim 36, wherein the software codes for detecting a signal based on the results of the first and second correlations comprise software codes for combining the results of the first and second correlations; and software codes for comparing the combined correlation results with a threshold value derived from the calculated received energy of at least two symbols.

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