RU2405187C1 - Device for controlled rearrangement of information stored on personal computer - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: device for controlled rearrangement of information stored on a computer with n inputs and n outputs of control codes, n data inputs and n data outputs, includes a sorting network, each cell of which consists of a sorting network comparator with two inputs, two outputs and a control output which is connected to the control input of the transpositional element of the cell having two data inputs and two data outputs, wherein for a pair of cells whose comparators are connected to each other in accordance with the sorting network topology, a condition is met that if the output of the comparator of the first cell is connected to the input of the comparator of the second cell, then the input of the transpositional element of the first cell is connected to the output of the transpositional element of the second cell, inputs of control codes of the device are formed by inputs of comparators of input cells of the sorting network, and outputs of control codes of devices are formed by outputs of comparators of output cells of the sorting network, data inputs are formed by inputs of transpositional elements of output cells of the sorting network, and data outputs are formed by outputs of transpositional elements of input cells of the sorting network.

EFFECT: possibility of high-speed parallel conversion of formats of data blocks.

2 dwg

Description

The device relates to the field of information conversion and can be used in computer technology, communication systems and information protection from unauthorized access.

For tasks associated with the conversion of data formats by the permutation method, high-speed devices that rearrange input data under the control of external codes are required. Of greatest interest are single-cycle devices that perform a given permutation in one clock cycle of an external clock. In this case, a frequent change of control codes should not slow down the operation of the device.

, регистр управляющих кодов, сдвиговый регистр данных, двойной буферный регистр накопления и хранения форматированных данных, блок управления, генератор тактовых импульсов. Вход выборки дешифратора соединен с первыми входами первого и второго элементов первого уровня. Элемент первого уровня реализует логическую функцию

, остальные элементы реализуют логическую функцию

. Вход Х элемента первого уровня соединен с выходом первого бита регистра управляющих кодов, входы X₁ остальных элементов i-го уровня соединены с выходом i-ro бита регистра управляющих кодов, входы X₂ остальных элементов i-ro уровня соединены с выходами элементов i-1 уровня, причем вход двойного буферного регистра накопления и хранения форматированных данных соединен с выходом сдвигового регистра данных, а входы разрешения записи этого регистра соединены с выходами последнего уровня дешифрации. Генератор тактовых импульсов соединен с блоком управления, который своими входами и выходами соединен с буферным регистром накопления и хранения форматированных данных, входным сдвиговым регистром данных, регистром управляющих кодов.Known decoder controlled bitwise transposition of information stored in a personal computer (see RF patent No. 232320000, IPC G06F 7/76). The decoder contains K levels of decryption nodes, each level of decryption contains 2 ⁱ elements

, a register of control codes, a shift register of data, a double buffer register of accumulation and storage of formatted data, a control unit, a clock generator. The input of the decoder sample is connected to the first inputs of the first and second elements of the first level. The first level element implements a logical function

, the remaining elements implement a logical function

. The input X of the element of the first level is connected to the output of the first bit of the register of control codes, the inputs X _{1 of the} remaining elements of the i-th level are connected to the output of the i-ro bit of the register of control codes, the inputs X _{2 of the} remaining elements of the i-ro level are connected to the outputs of the elements i-1 level, and the input of the double buffer register of accumulation and storage of formatted data is connected to the output of the shift data register, and the recording permission inputs of this register are connected to the outputs of the last decryption level. The clock generator is connected to a control unit, which is connected with its inputs and outputs to a buffer register for storing and storing formatted data, an input shift data register, and a register of control codes.

The disadvantage of this decoder is the sequential conversion of data that occurs over N clock pulses of the generator, which at large values of N significantly reduces performance.

Betcher's sorting networks are known ("Sorting Networks and Their Applications", K. E. Batcher, Proceedings of 1968 Spring Joint Computer Conference, pp.307-314, 1968). These devices perform quick sorting of 2 ^p data elements in 1 / 2p (1 + p) steps, but do not provide data permutation controlled by external code.

Known modified Betcher network for sorting unsorted input signals for log ₂ N consecutive passes. A network is built recursively from size 4 to an arbitrary size. The modified Betcher network sorts N data elements for log ₂ N consecutive passes through the network, where N is the number of data elements for each pass. The network has a delay on log ₂ N comparators (see US patent No. 5319788, IPC G06F 7/36; G06F 7/22).

However, this network does not provide external code-driven permutation of input data.

A device for implementing controlled permutations is known, which consists of two networks of the Butterfly type of the same size, connected to one another (back-to-back). Management is carried out programmatically using a processor.

The disadvantage of this device is the software permutation control, which is performed by the processor and leads to a slowdown of the system (see US patent No. 6922472, IPC H04L 9/34).

The objective of this solution is to simplify and accelerate the process of managing permutations while minimizing the elements of the device.

The technical result is the possibility of high-speed parallel conversion of data block formats by permutation using control codes.

The problem is achieved in that a device for controlled permutation of information stored in a computer with n inputs and n outputs of control codes, n inputs and n outputs of data includes a sorting network, each cell of which consists of a comparator of the sorting network, with two inputs, two the outputs and the control output, which is connected to the control input of the transposition cell element having two inputs and two data outputs, moreover, for pairs of cells whose comparators are interconnected in accordance with the sorting topology network condition, if the comparator output of the first cell is connected to the input of the comparator of the second cell, then the input of the transposition element of the first cell is connected to the output of the transposition element of the second cell, the inputs of the control codes of the device are formed by the inputs of the comparators of the input cells of the sorting network, and the outputs of the control codes of the device are formed by the outputs comparators of the output cells of the sorting network, the data inputs are formed by the inputs of the transposition elements of the output cells of the sorting network, and the data outputs are ovany outputs transposition of elements of the input cell sorting network.

The invention is illustrated by drawings, where Fig. 1 is a block diagram of a device, Fig. 2 is a diagram for implementing a controlled permutation of a data vector of 4 elements based on a Betcher sorting network,

Where

1. a controlled swap device;

2. cells of the sorting network;

X1, X2, ..., Xn - n data inputs;

Y1, Y2, ..., Yn - n data outputs;

IC1, IC2, ..., ICn - n inputs of control codes;

OS1, OS2, ..., OSn-n outputs of control codes;

π (1,2, ..., n) - permutation of control codes;

(1,2, ..., n) - sorted control codes;

(x ₁ , x ₂ , ..., x _n ) - input data;

π (x ₁ , x ₂ , ..., x _n ) - output;

X ₁ , X ₂ - the first and second inputs of these transposition elements;

Y1, Y ₂ - the first and second outputs of these transposition elements;

IC ₁ , IC ₂ - the first and second inputs of the comparators;

OC ₁ , OC ₂ - the first and second outputs of the comparators;

IC1, IC2, IC3, IC4 - inputs of control codes;

OC1, OC2, OS3, OS4 - outputs of control codes;

X1, X2, X3, X4 - data inputs;

Y1, Y2, Y3, Y4 - data outputs.

The proposed device includes a sorting network 1, in the nodes of which are cells 2, consisting of a comparator of the sorting network and a transposition element of the controlled data permutation. The comparator of the sorting network has a control output (not shown in the drawings), two inputs IC ₁ , IC ₂ and two outputs OC ₁ , OC ₂ . The transposition element has a control input, inputs X ₁ , X ₂ and outputs Y ₁ , Y ₂ . In each cell, the control output of the comparator is connected to the control input of the transposition element.

The connections of the OC ₁ outputs and IC ₁ inputs, OS ₂ outputs and comparator IC ₂ inputs are determined by the topology of the sorting network used. The connections IC1, IC2, ..., ICn of the control code inputs to the comparator inputs of the input cells of the sorting network are determined by the topology of the sorting network used. The connections OS1, OS2, ..., OSn of the outputs of the control codes with the outputs of the comparators of the output cells of the sorting network are determined by the topology of the sorting network used.

If the output OS _{1 of the} comparator of one cell of the sorting network is connected to the input IC _{1 of the} comparator of another cell of the sorting network, then the input X _{1 of the} transposition element of one cell is connected to the output Y _{1 of the} other cell. If the output OS _{2 of the} comparator of one cell of the sorting network is connected to the input IC _{2 of the} comparator of another cell of the sorting network, then the input X _{2 of the} transposition element of one cell is connected to the output Y _{2 of the} other cell. If the outputs OC ₁ , OC _{2 of the} output cell of the sorting network are the outputs of the control codes of the device, then the inputs X ₁ , X _{2 of the} transposition element of this cell are data inputs. If the inputs IC ₁ , IC _{2 of the} input cell of the sorting network are the inputs of the control codes of the device, then the outputs Y ₁ , Y _{2 of the} transposition element of this cell are the data outputs.

The device operates as follows. The n inputs of control codes IC1, IC2, ..., ICn formed by the inputs of the comparators IC ₁ , IC _{2 of the} device are supplied with input control codes, which are a permutation of numbers of the natural series π (1,2, ..., n). The input data (x ₁ , x ₂ , ..., x _n ) are fed to the n data inputs X1, X2, ..., Xn formed by the inputs of the transposition elements X ₁ , X _{2 of the} device. After the delay time τ, at the n data outputs Y1, Y2, ..., Yn formed by the outputs of the transposition elements of the device, the output data appears, which is a permutation π (x ₁ , x ₂ , ..., x _n ). The delay time τ is determined by the number of elements on the propagation path of the control signals and data. If the value of the code at the input of the comparator IC _{1 is} greater than or equal to the value of the code at the input of the comparator IC ₂ , then the code value is supplied from the input of IC ₁ to the output OC ₁ , and the value of the code at the input of IC _{2 is} sent to the output of OS ₂ . At the same time, a signal appears on the control output of the comparator, which is fed to the control input of the transposition element. In this case, the resettable data at input X _{1 is} output Y ₁ ; and the reconstructed data at input X ₂ goes to output Y ₂ .

If the value of the code at the input of the comparator IC _{1 is} less than the value of the code at the input of the comparator IC ₂ , then the code value comes from the input IC ₁ to the output of OS ₂ , and the value of the code at the input of IC ₂ goes to the output OC ₁ . At the same time, a signal appears on the control output of the comparator, which is fed to the control input of the transposition element. In this case, the resettable data at input X _{1 is} output Y ₂ ; and the reconstructed data at input X ₂ goes to output Y ₁ .

Thus, the rearrangement of the input data vector (x ₁ , x ₂ , ..., x _n ) in accordance with the input control codes π (1,2, ..., n) is performed in parallel, which ensures high conversion speed. The number of device cells depends on the topology of the sorting network used, and for Betcher networks it is O (n · (log ₂ n) ² ). This number grows almost linearly with increasing n, which makes it technically possible to control the permutation of large data blocks.

Claims (1)

A device for controlled permutation of information stored in a computer with n inputs and n outputs of control codes, n inputs and n outputs of data includes a sorting network, each cell of which consists of a comparator of the sorting network, with two inputs, two outputs and a control output, which is connected to the control input of the transposition cell element having two inputs and two data outputs, and for pairs of cells whose comparators are interconnected in accordance with the topology of the sorting network, the condition is met if the output to the first cell is connected to the input of the comparator of the second cell, the input of the transposition element of the first cell is connected to the output of the transposition element of the second cell, the inputs of the control codes of the device are formed by the inputs of the comparators of the input cells of the sorting network, and the outputs of the control codes of the device are formed by the outputs of the comparators of the output cells of the sorting network, the inputs data are formed by the inputs of the transposition elements of the output cells of the sorting network, and the data outputs are formed by the outputs of the transposition elements s input cells sorting network.

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