RU2397611C1 - On/off bistable relay - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: device keeps its bistable state within several years. Electronic on/off bistable relay includes unit of nonvolatile memory holding the maintained state at the output in case there is no power supply voltage, shaper of delay, controlled pulse generators, pulse transformers, rectifier diodes, resistors of discharge, n-channel MOS transistors, control inputs of relay, power inputs of relay, relay outputs. Peculiar feature of nonvolatile memory unit is that nonvolatile preservation of the state of its outputs; at failure of power supply voltage U_power the state of its outputs Q₀ and Q₁ will not change even if power supply voltage U_power has not been supplied to nonvolatile memory unit within several years. Its second peculiar feature consists in easy data recoding to inputs D₀, D₁ and data readout from it outputs Q₀, Q₁. So, data for input D₀, which is recorded to input Q₀ as to CLK signal, will not change until control voltage Ucontrol enters the second control input.

EFFECT: improving technical characteristics of on/off bistable relay owing to increasing the number of commutation cycles at all current load modes, and improving reliability of bistable relay owing to excluding movable contacts, and reducing drain-source resistance of open n-channel MOS transistor in comparison to electromechanical relay.

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Description

The invention relates to the field of electronic technology and can be used in switching devices instead of polarized on-off two-position electromagnetic relay type RPS45, RPS20, RPS32, etc.

Known polarized on-off bi-directional electromagnetic relay type RPS 45, RPS 20, RPS 32 and others, the main disadvantages of which are: a limited number of switching cycles, contact bounce, high resistance of the contacts of the electrical circuit, which reduces their reliability.

The technical result of the invention is to improve the technical characteristics of a two-position bi-directional relay by increasing the number of switching cycles at all load current modes and increasing the reliability of a bi-directional relay by eliminating moving contacts.

To achieve this goal, an electronic two-position bi-stable relay is proposed, containing a non-volatile memory unit that saves inputs like normal CMOS logic and holds a stored state at the output in the absence of a supply voltage; delay driver; first and second controlled pulse generators; first and second pulse transformers, each of which contains one primary and first and second secondary windings; first, second, third and fourth rectifier diodes; first, second, third and fourth discharge resistors; first, second, third and fourth n-MOS transistors; first and second relay control inputs; first and second relay power inputs; relay outputs. Moreover, the first relay power input is connected to the inputs Vdd, EN of the non-volatile memory block, with the first inputs of the first and second controlled pulse generators, the second relay power input is connected to the Vss input of the non-volatile memory block and with the second inputs of the first and second controlled pulse generators, the first control input the relay is connected to the input D ₀ of the non-volatile memory block and the first input of the delay driver block, and the second relay control input is connected to the input D ₁ of the non-volatile memory block and the second input of the a delay generator whose output is connected to the CLK input of a non-volatile memory block, the first output of which Q _{0 is} connected to the control input of the first controlled pulse generator, the outputs of which are connected to the primary winding of the first pulse transformer, the first output of the first secondary winding of which is connected to the anode of the first rectifier diode, the cathode of which is connected to the first terminal of the first discharge resistor and the gate of the first n-MOS transistor, the drain of which is the first relay output, the second terminal is the second the first winding of the first pulse transformer is connected to the second terminal of the first discharge resistor, the source of the first n-MOS transistor and the second relay terminal, the first terminal of the second secondary winding of the first pulse transformer is connected to the anode of the second rectifier diode, the cathode of which is connected to the first terminal of the second discharge resistor and the gate the second n-MOS transistor, the drain of which is connected to the third output of the relay, and the second terminal of the secondary winding of the first pulse transformer is connected to the second terminal of the second res ora discharge source of the second n-MOS transistor and the fourth output of the relay, the second output Q ₁ a non-volatile memory unit connected to the control input of the second control pulse generator, to the output of which is connected the primary winding of the second pulse transformer, a first terminal of the first secondary windings of which are connected to the anode of the third rectifier diode, the cathode of which is connected to the first output of the third discharge resistor and the gate of the third n-MOS transistor, the drain of which is connected to the fifth relay output, the second the output of the first secondary winding of the second pulse transformer is connected to the second output of the third discharge resistor, the source of the third n-MOS transistor and the sixth relay output, the first output of the second secondary winding of the second pulse transformer is connected to the anode of the fourth rectifier diode, the cathode of which is connected to the first output of the fourth discharge resistor , the gate of the fourth n-MOS transistor, the drain of which is connected to the seventh relay output, the second output of the second secondary winding of the second pulse transformer soy dinen with the second output of the fourth discharge resistor, the source of the fourth n-MOS transistor and the eighth relay output.

Figure 1 presents a block diagram of an electronic bi-stable relay. However, the elements of the device may have unprincipled differences; figure 2 is a timing diagram explaining the operation of the claimed relay.

The electronic two-position two-stable relay contains:

1 - non-volatile memory block;

2 - delay driver;

3 - the first controlled pulse generator;

4 - the second controlled pulse generator;

5 - the first pulse transformer;

6 - primary winding of the first pulse transformer;

7 - the first secondary winding of the first pulse transformer;

8 - the second secondary winding of the first pulse transformer;

9 - second pulse transformer;

10 - primary winding of the second pulse transformer;

11 - the first secondary winding of the second pulse transformer;

12 - the second secondary winding of the second pulse transformer;

13 - the first rectifying diode;

14 - second rectifying diode;

15 - the third rectifying diode;

16 - fourth rectifying diode;

17 - the first discharge resistor;

18 - second discharge resistor;

19 - third discharge resistor;

20 - fourth discharge resistor;

21 - the first n-MOS transistor;

22 - second n-MOS transistor;

23 - the third n-MOS transistor;

24th-fourth n-MOS transistor;

25 - the first input of the relay power;

26 - the second input of the relay power;

27 - the first input of the relay control;

28 - the second input of the relay control;

29, 30, 31, 32, 33, 34, 35, 36 - respectively, the first, second, third, fourth, fifth, sixth, seventh and eighth relay outputs.

Uз - voltage at the gate of n-MOS transistors;

± Ucom - switching voltage;

± Upit - relay supply voltage;

± Uadr - relay control voltage;

D ₀ , D ₁ - inputs of a non-volatile memory block;

Vdd - input voltage - Upit block non-volatile memory;

Q ₀ , Q ₁ - outputs of the non-volatile memory block;

CLK - clock pulse of a non-volatile memory block;

Vss, EN - inputs of the independent memory block.

Electronic two-position bi-stable relay is as follows.

The non-volatile memory block 1 by the input D _{0 is} connected to the first control input of the relay 27 and the first input of the delay driver 2. The input D ₁ of the non-volatile memory block 1 is connected to the second control input 28 and the second input of the delay driver 2, the output of which is connected to the CLK input of the non-volatile memory 1. The first power input of the relay 25 is connected to the input Vdd and EN of the non-volatile memory unit 1 and to the first inputs of the first 3 and second 4 controlled generators.

The second power input of the relay 26 is connected to the input Vss of the non-volatile memory unit 1 and the second inputs of the first 3 and second 4 controlled generators.

The output Q ₀ of the non-volatile memory block 1 is connected to the control input of the first controlled generator 3, the output Q ₁ of the non-volatile memory block 1 is connected to the control input of the second controlled generator 4.

The primary winding 6 of the first pulse transformer 5 is connected to the output of the first controlled generator 3. The first output of the first secondary winding 7 of the first pulse transformer 5 is connected to the anode of the first rectifier diode 13, the cathode of which is connected to the first output of the first discharge resistor 17 and the gate of the first n-MOS transistor 21. The drain of the first n-MOS transistor 21 is the first relay output 29. The second terminal of the first secondary winding 7 of the first pulse transformer 5 is connected to the second terminal of the first discharge resistor 17, the source of the first n-MOS transistor 21 and the second relay terminal 30.

The first terminal of the second secondary winding 8 of the first pulse transformer 5 is connected to the anode of the second rectifier diode 14, the cathode of which is connected to the first terminal of the second discharge resistor 18 and the gate of the second n-MOS transistor 22, the drain of which is the third relay output 31. The second terminal of the second secondary winding 8 of the first pulse transformer 5 is connected to the second terminal of the second discharge resistor 18, the source of the second n-MOS transistor 22 and the fourth output of the relay 32.

The primary winding 10 of the second pulse transformer 9 is connected to the output of the second controlled generator 4.

The first output of the first secondary winding 11 of the second pulse transformer 9 is connected to the anode of the third rectifier diode 15, the cathode of which is connected to the first output of the third discharge resistor 19 and the gate of the third n-MOS transistor 23, the drain of which is the fifth output 33 of the relay. The second terminal of the first secondary winding 11 of the second pulse transformer 9 is connected to the second terminal of the second discharge resistor 19, the source of the third n-MOS transistor 23 and the sixth relay output 34.

The first terminal of the second secondary winding 12 of the second pulse transformer 9 is connected to the anode of the fourth rectifier diode 16, the cathode of which is connected to the first terminal of the fourth discharge resistor 20 and the gate of the fourth n-MOS transistor 24, the drain of which is the seventh relay output.

The second terminal of the second secondary winding 12 of the second pulse transformer 9 is connected to the second terminal of the fourth discharge resistor 20, the source of the fourth n-MOS transistor 24, and the eighth relay terminal 36.

Electronic two-position bi-stable relay operates as follows. In the initial state, when the first 25 and second 26 power inputs of the relay and the EN input of the non-volatile memory unit 1 are supplied with the supply voltage Upit, and the first 27 and second 28 control inputs do not have control pulses, the first 21, second 22, third 23 and fourth 24 n-MOS transistors are closed (Fig. 2 Uc-u (21,22), Uc-u (23,24)). When applying to the first control input 27 a positive pulse received at the input D ₀ of the non-volatile memory unit 1 and at the first input of the delay driver 2 (FIG. 2 D ₀ ), the latter generates a clock pulse CLK1 (FIG. 2 CLK), arriving at the non-volatile block memory 1. Delay driver 2 is designed to generate a clock pulse with a delay time t back to eliminate the chatter of the pulse received at the first control input of the relay 27. On the leading edge of the pulse CLK1 from the delay driver 2 block non-volatile memory 1 ne writes information from the first 27 and second 28 control inputs to the output Q ₀ , Q ₁ of the non-volatile memory block 1 (Fig. 2 Q ₀ , Q ₁ ,). Since at the moment of formation of the pulse CLK1 at the input D ₀ there is a relay voltage Uadr, and at the input D ₁ the control voltage Uadr = 0, a positive voltage is also formed at the output Q ₀ (Fig. 2 Q ₀ ), which goes to the control input of the first controlled generator 3, which generates rectangular pulses of the order of 200 kHz. These pulses are fed to the primary winding 6 of the first pulse transformer 5. At the first 7 and second 8 secondary windings of the first pulse transformer 5, rectangular pulses of the same frequency are also formed. These pulses are rectified by the first 13 and second 14 rectifier diodes and respectively fed to the first output of the first 17 and second 18 discharge resistors and the gate of the first 21 and second 22 n-MOS transistors, charging their input capacitance (its value is on the order of a thousand picofarads). At the gate of the first 21 and second 22 n-MOS transistors, a constant voltage Uz = 10B is formed (Fig.2 Uz-u (21, 22)), which opens the first 21 of the second 22 n-MOS transistors (Fig.2 Uc-u (21 , 22)). In addition, the first pulse transformer 5 provides galvanic isolation between the power inputs 25, 26, the control inputs 27, 28 and the first 29, second 30, third 31, fourth 32 relay inputs.

Since at the moment of formation of the first clock pulse CLK by the delay driver 2 at the second control input 28 Uupr = 0 (Fig. 2 D ₁ ), then the output Q ₁ of the non-volatile memory 1 is equal to zero voltage (Fig. 2 Q ₁ ), the voltage on the gate of the third 23 and fourth 24 n-MOS transistors Uз = 0, therefore, the third 23 and fourth 24 n-MOS transistors are closed.

A feature of the non-volatile memory unit 1 is the non-volatile preservation of the state of its outputs when the supply voltage Upit is disconnected, the state of its outputs Q ₀ and Q ₁ does not change even if the supply voltage Upit has not been supplied to the non-volatile memory unit for several years. Its second advantage is the simplicity of writing to the inputs D ₀ , D ₁ and reading data from its outputs Q ₀ , Q ₁ . Therefore, the data on the input D ₀ , rewritten on the input Q ₀ , according to the signal CLK will not change until the control voltage Uadr arrives at the second control input 28 (Fig. 2 D ₁ ).

When applying to the second control input 28 a positive pulse (FIG. 2 D ₁ ) received at the input D ₁ of the non-volatile memory block 1, the second input of the delay driver 2, the latter generates a clock pulse CLK2 (FIG. 2 CLK2), which is received at the non-volatile memory block 1. On the leading edge of the pulse CLK2, the non-volatile memory unit 1 overwrites the information from the first 27 and second 28 inputs of the relay control.

So at the moment of formation of the pulse CLK2 at the input D ₀ of the non-volatile memory block 1 Uupr = 0 (Fig.2 D ₀ ), then the output "Q ₀ of the non-volatile memory block 1 also sets the signal" log 0 ", which will turn off the first controlled generator 3. Input the capacitance of the first n-MOS transistor 21 is discharged through the first resistor 17 and when the voltage Uz becomes less than the threshold voltage for the first n-MOS transistor 21, it closes.

The input capacitance of the second n-MOS transistor 22 is discharged through the second discharge resistor 18, and when the voltage Uz becomes less than the threshold voltage of the second n-MOS transistor 22, it closes.

Since at the time of formation of the pulse CLK2 at the input D ₁ of the non-volatile memory block 1 there is a positive pulse (Fig. 2 D ₁ ), then a positive voltage is also formed at the output Q _{1 of the} block of non-volatile memory 1 along the edge of the signal CLK2 (Fig. 2 Q ₁ ) which is fed to the control input of the second controlled generator 4. It generates rectangular pulses with a frequency of about 200 kHz, which are fed to the primary winding 10 of the second pulse transformer 9. On the first 11 and second 12 secondary windings of the second pulse transformer 9 also rectangular pulses are rectified, which are rectified by the third 15 and fourth 16 rectifier diodes and respectively fed to the first output of the third 19 and fourth 20 resistors of the discharge and the gates of the third 23 and fourth 24 n-MOS transistors. Since the input capacitance of the third 23 and fourth 24 n-MOS transistors is thousands of picofarads, their input capacitance is a filtering capacitance. At the gate of the third 23 and fourth 24 n-MOS transistors, a constant voltage Uz = 10 V is generated (Fig.2 Uz-u (23, 24)), which opens the third 23 and fourth n-MOS transistors (Fig.2 Uc-u ( 23, 24)). This state of the third 23 and fourth 24 n-MOS transistors will remain indefinitely (several years) when the supply voltage of the relay Upit is removed, the pulse arrives at the input D ₁ until a control voltage pulse Uupr arrives at the other input D ₀ . At the same time, the second pulse transformer 9 carries out galvanic isolation between the first 25, second 26 power inputs, the first 27, second 28 relay control inputs and the fifth 33, sixth 34, seventh 35 and eighth 36 relay outputs.

Thus, the electromechanical relays of the type RPS45, RPS20, RPS32 and others maintain their bistable state due to the permanent magnets integrated in the contact system of the relay, and the proposed device maintains its bistable state through the use of an integrated circuit of non-volatile memory (non-volatile memory block).

The proposed device is a fully electronic relay having the number

switching cycles up to 10 ¹² for all modes of load current, does not have moving contacts, which increases the reliability of the electronic relay, has less drain-source resistance of an open n-MOS transistor compared to electromechanical relays.

As a non-volatile memory unit 1, a volatile microchip based on FRAM memory is used, which holds the stored state at its outputs with the power supply disconnected for 45 years, such as RAMTRON type FM1110.

An integrating RC circuit can be used as a delay driver 2 if the delay in generating the CLK signal is units of ms or is performed according to the circuit shown in Fig. 2868 at http://www.gelezo.com./ttl-kmop/630000/ formirovateli i generator ... if it is necessary to form a delay in the range of 30 to 40 ms or more.

As controlled generators, the device shown in Fig. 314-316 on the above site can be used, transformers of the TII-4 type can be used as pulse transformers, transistors of the type 2P7169, 2P7161, 2P7169 and others can be used as n-MOS transistors . The choice of n-MOS transistors is determined by the load current and switching voltage Ucom of the electronic relay.

Claims (1)

A two-position, unstable relay, characterized in that the relay contains a non-volatile memory unit that preserves inputs and holds a stored state at the output when there is no supply voltage, a delay shaper, the first and second controlled pulse generators, the first and second pulse transformers, each of which contains one primary and first and second secondary windings, first, second, third and fourth rectifier diodes, first, second, third and fourth discharge resistors, first, second, third and h the fourth n-MOS transistors, the first and second relay control inputs, the first and second relay power inputs, relay outputs, the first relay power input connected to the Vdd, EN inputs of the non-volatile memory block, with the first inputs of the first and second controlled pulse generators, the second input power relay connected to the input Vss nonvolatile storage unit and to second inputs of the first and second driven pulse generators, the first relay control input connected to the input D ₀ nonvolatile storage unit and the first input of the generator of Derzhko and the second input control relay connected to the input D _one volatile memory and the second input of the delay generator unit, whose output is connected to the input CLK the non-volatile memory block, the first output of which Q ₀ is connected to the control input of the first control pulse generator to whose output is connected primary winding of the first pulse transformer, the first terminal of the first secondary winding of which is connected to the anode of the first rectifier diode, the cathode of which is connected to the first terminal of the first resistor the poison and the gate of the first n-MOS transistor, the drain of which is the first relay output, the second output of the first secondary winding of the first pulse transformer is connected to the second output of the first discharge resistor, the source of the first n-MOS transistor and the second relay output, the first output of the second secondary winding of the first pulse the transformer is connected to the anode of the second rectifier diode, the cathode of which is connected to the first output of the second discharge resistor and the gate of the second n-MOS transistor, the drain of which is connected to the third output e, and an end of the second secondary winding of the first pulse transformer connected to the second terminal of the second discharge resistor, the source of the second n-MOS transistor and the fourth output of the relay, the second output Q ₁ a non-volatile memory unit connected to the control input of the second control pulse generator, to which the output the primary winding of the second pulse transformer is connected, the first output of the first secondary winding of which is connected to the anode of the third rectifier diode, the cathode of which is connected to the first output of the tre a discharge resistor and a gate of a third n-MOS transistor, the drain of which is connected to the fifth output of the relay, the second output of the first secondary winding of the second pulse transformer is connected to the second output of the third discharge resistor, the source of the third n-MOS transistor and the sixth relay output, the first output of the second secondary the windings of the second pulse transformer is connected to the anode of the fourth rectifier diode, the cathode of which is connected to the first output of the fourth discharge resistor, the gate of the fourth n-MOS transistor, the drain of which connected to the seventh relay output, the second terminal of the second secondary winding of the second pulse transformer is connected to the second terminal of the fourth discharge resistor, the source of the fourth n-MOS transistor and the eighth relay output.

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