RU2389065C1 - Multiplication-division unit - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: multiplication-division unit relates to automation and computer engineering and can be used in processing signals presented in code and pulse-duration form and outputting calculation results in code and pulse-frequency form. The device has a bidirectional counter, three AND elements, two binary rate multipliers and two OR elements.

EFFECT: broader functionalities of the device.

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Description

The present invention relates to automation and computer technology and may find application in the processing of signals presented in code and pulse-width forms in the issuance of calculation results in code and pulse-frequency forms.

A device of the frequency multiplier is described in the USSR copyright certificate No. 525969, class. G06G 7/16, 1974, which implements a multiplier-division function with the representation of the result in a frequency-pulse form

,

,

where F _o and F _I - output and input frequencies;

Θ ₁ and Θ ₂ are input relative durations of rectangular pulses.

This device contains a reversible counter, summing and subtracting, the inputs of which are connected to the outputs of the first and second elements And, and the code output of the counter through a series-connected register and a code-voltage converter to the input of a controlled frequency generator, the output of which is connected to the output of the device and to the first the input of the second element And, the second input of which and the first input of the first element And are connected to the outputs of the divider and the dividend sensor of the time intervals, the third output of the sensor is connected to the control input istra and input devices are connected to slots sensor and to the second input of the first element I.

The disadvantages of this device are reduced reliability, the lack of presentation of the result in code form, the heterogeneity of the element base and the associated low-tech, as well as reduced accuracy of calculations due to the presence of analog elements.

Closest to the technical nature of the claimed device is a multiplier dividing device described in the author's certificate of the USSR No. 788128, cl. G06G 7/161, G06G 3/00, 1977, which is accepted as a prototype.

The prototype performs operations on operands presented in pulse-width form, the result of which is formed in the form of a pulse-frequency sequence. The prototype is characterized by the uniformity of the element base, ease of implementation, as well as noise immunity and higher accuracy of the device. In addition, in the prototype, the result is presented not only in the frequency-pulse, but also in code form.

The prototype contains a reversible counter, two AND elements, two binary frequency multipliers, an input of the first and an input of a second reference frequency, the first of these inputs being connected to the frequency input of the first binary frequency multiplier, the code input of which is connected to the code input of the device and the output is connected to the first the input of the first element And, the second input of which is connected to the input of the first pulse-width signal, and the output is connected to the summing input of the reverse counter, the output of which is connected to the code output of the device and to the code the input of the second binary frequency multiplier, and the output of this multiplier is connected to the frequency output of the device and to the first input of the second element And, the second input of which is connected to the input of the second pulse-width signal. In addition, the frequency input of the second binary frequency multiplier is connected to the input of the second reference frequency, and the output of the second element And is connected to the subtracting input of the reversible counter.

Due to the presence of negative feedback, a dynamic equilibrium mode is established in the device, characterized (by neglecting changes in the output code of the N _output counter having sufficient bit capacity) by the equality of the number of pulses arriving at the summing N ₊ and subtracting N _- inputs of the reverse counter during one period of the pulse-width modulation, i.e.

или

,

or

,

и

- средние значения частот импульсных последовательностей на суммирующем и вычитающем входах реверсивного счетчика.Where

and

- the average frequency values of the pulse sequences on the summing and subtracting inputs of the reversible counter.

The last relation, taking into account the bit depth of binary multipliers, is written as

,

,

where Θ ₁ = τ ₂ / T and Θ ₂ = τ ₁ / T are the relative durations of the input pulse-width signals with durations τ ₁ and τ ₂ and period T;

F ₀₁ and F ₀₂ - the frequency of the first and second reference pulse sequences;

N is the input code supplied to the input of the device;

N _o - output code;

n is the bit depth of binary multipliers.

Thus, for the steady state, the functional characteristic of the device for the code output has the form

,

,

and on the frequency output

,

,

- среднее значение выходной частоты устройства.Where

- the average value of the output frequency of the device.

The disadvantage of the prototype is the low functionality due to the limitation of the number of arguments by two pulse-width signals.

The technical result of the invention is the expansion of functionality.

The technical result achieved is achieved by the fact that the multiplier dividing device, which includes a reversible counter, two AND elements, two binary frequency multipliers, the input of the first and the input of the second reference frequencies, the first of these inputs being connected to the frequency input of the first binary frequency multiplier whose code input is connected to the code input of the device, and the output is connected to the first input of the first element And, the second input of which is connected to the input of the first pulse-width signal, and the output is connected to the sum the input of the reversible counter, the output of which is connected to the code output of the device and to the code input of the second binary frequency multiplier, and the output of this multiplier is connected to the frequency output of the device and to the first input of the second element And, the second input of which is connected to the input of the second pulse-width signal, two OR elements are introduced and a third AND element, the first input of which is combined with the first input of the second AND element, the second input is connected to the input of the third pulse-width signal, and the outputs of the second and third elements in AND are connected respectively to the first and second inputs of the first OR element, the output of which is connected to the subtracting input of the reverse counter, the input of the second reference frequency being connected to the third input of the second AND element and to the first input of the second OR element, and the input of the third reference frequency to the third the input of the third AND element and with the second input of the second OR element, the output of which is connected to the frequency input of the second binary frequency multiplier.

The essence of the invention consists in creating a functional converter of three pulse-width signals arriving periodically using the iterative method of implementing the averaging operator by functional generalization of the binary frequency multiplier by combining the phasing and modulation of pulse sequences and obtaining the ability to calculate the function of three variables.

The essence of the invention is illustrated by drawings, where figure 1 shows a functional diagram of a multiplier dividing device, and figure 2 is a timing diagram of the input pulse sequences.

The proposed device (figure 1) contains a reversible counter 1, two elements And 2, 3, two binary frequency multipliers 4, 5, input 6 of the first and input 7 of the second reference frequencies, the first of these inputs 6 being connected to the frequency input of the first binary multiplier frequency 4, the code input of which is connected to the code input 8 of the device, and the output is connected to the first input of the And 2 element, the second input of which is connected to the input 9 of the first pulse-width signal, and the output is connected to the summing input of the reverse counter 1, the output of which is connected to coded in and move the device 10 to the code entry binary frequency multiplier 5 and the output of the multiplier 5 is connected to the frequency output device 11 and to a first input of AND gate 3, the second input of which is connected to the input 12 of the second PWM signal. In addition, the device contains two elements OR 13, 14 and a third element And 15, the first input of which is combined with the first input of the element And 3, the second input - with the input 16 of the third pulse-width signal, and the outputs of the element And 3 and the element And 15 are connected respectively, with the first and second inputs of the OR element 13, the output of which is connected to the subtracting input of the reverse counter 1, the input 7 of the second reference frequency being connected to the third input of the And 3 element and the first input of the OR element 14, and the input 17 of the third reference frequency to the third input element And 15 and with watts the next input of the OR element 14, the output of which is connected to the frequency input of the binary frequency multiplier 5.

The device operates as follows. Suppose that at the initial moment of time the reverse counter 1 is reset, binary N is supplied to input 8 of the device, pulse-width signals with one repetition period T and relative durations Θ ₁ , Θ ₂ , Θ ₃ are received at inputs 9, 12, 16, and inputs 6, 7, 17 - reference pulse sequences with frequencies F ₀₁ , F ₀₂ , F ₀₃ . These impulse sequences are related by

At the same time, to ensure the normal functioning of the device, the following phase relations are set with respect to the first pulse sequence with a period of T ₀ : the second reference pulse sequence is shifted by 0.5T ₀ , and the third by 1.5T ₀ (FIG. 2).

Under the influence of the N code, pulses are generated at the output of the frequency 4 frequency multiplier, which during the time interval τ _{1 of} unlocking the element And 2 pass through this element to the summing input of the reverse counter 1, changing its state. After the first pulse, the binary frequency multiplier 5 starts to generate pulses, because the counter code 1 controlling it becomes nonzero, and its pulse input receives a pulse sequence through the OR element 14 with the total frequency (F ₀₂ + F ₀₃ ), due to the time diversity of the signals arriving at its inputs. The pulses from the output of the binary frequency multiplier 5 are fed to the first input of the element And 3. At the output of this element, the pulses appear in accordance with the phase of the reference pulse sequence F ₀₂ coming from input 7 to the third input of the element And 3, and only during the time interval τ ₂ unlocking the element And 3. Then, through the element OR 13, this pulse sequence is fed to the subtracting input of the reverse counter 1. In addition, pulses from the output of the element And 15 pass through the element OR 13 to this input during the time interval e on unlocking τ ₃ in accordance with the phase of the reference pulse sequence coming from input 17. These pulses are also generated by a binary frequency multiplier 5 and fed to the first input of element 15. The output code N _o is generated on the reverse counter 1 and fed to the code output 10 of the device and the output pulse sequence with an average frequency F _{o is} generated by a binary frequency multiplier 5 and is supplied to the frequency output 11 of the device. In the following periods, the operation of the device is repeated.

Thus, in a direct circuit, a pulse sequence is generated from the output of the binary multiplier 4 and is modulated by a pulse-width signal with a relative duration of Θ ₁ . The pulse stream, in the feedback circuit of the device, from the output of the binary frequency multiplier 5 is divided by elements And 3, 15 into two sequences of pulses in accordance with the phase of the signals coming from inputs 7, 17, respectively. In this case, at the same time, the selected pulse sequences are modulated by pulse-width signals with a relative duration of Θ ₂ , Θ ₃ , followed by summing using the OR element 13.

The device is based on the principle of latitudinal modulation of frequency-pulse sequences and their automatic compensation using negative feedback when averaging the generated pulse sequences and the presence of a pulse stream that is shared and combined during the creation of the feedback signal, as a result of which the fractional rational function of three variables. The condition for the dynamic equilibrium of the device is the equality of the increments of the codes of the summing and subtracting circuits of the reverse counter during the repetition period of the pulse-width signals, i.e. equality of the average frequencies of the pulse sequences received at its summing and subtracting inputs. The presence of negative feedback in the device provides access to the steady-state dynamic equilibrium mode, characterized by the equality of the number of pulses arriving at the summing N ₊ and subtracting N _- inputs of the reverse counter 1 during the period T of pulse-width modulation, i.e.

или

,

or

,

и

- средние значения частот импульсных последовательностей на суммирующем и вычитающем входах реверсивного счетчика 1 соответственно.Where

and

- the average frequency values of the pulse sequences on the summing and subtracting inputs of the reversible counter 1, respectively.

The number of pulses received at the summing and subtracting inputs of the reverse counter 1 during one period of pulse-width modulation is determined by the relations

,

,

.

.

Given the ratio of the frequencies of the reference pulse sequences (1), (2) and (3), we will have

,

,

.

.

, получимMarking

we get

,

,

.

.

After the first period of operation of the device, the reverse counter 1 will generate a code

where N _o0 is the initial value of the output code.

After the second period of operation of the device, the reverse counter 1 will generate a code

Substituting expression (4) for N _output1 , we obtain

After the third period of operation of the device, the reverse counter 1 will generate a code

After the i-th period of operation of the device, the reverse counter 1 will generate a code

и может быть представлено суммойThe second term of this expression is characterized by a geometric progression with a base

and can be represented by the sum

находится в том же диапазоне, т.е.Since the quantities Θ ₂ and Θ ₃ are in the range 0 <Θ ₂ <1 and 0 <Θ ₃ <1, then the result

is in the same range, i.e.

.

.

Given that k is also in the range from 0 to 1, i.e.

0 <k <1,

и, следовательно,we get

and therefore

.

.

In the limit, the geometric progression of the second term of expression (5) is transformed to

,

,

and the first term of expression (5) will be zero, because

.

.

Thus, in the steady state, the transfer characteristic of the device will have the form

In this case, a pulse sequence with an average frequency will arrive at the frequency output 11 of the device

Thus, the introduction of the third argument Θ ₃ into the denominators of dependencies (6), (7) is a factor proving the expansion of the functionality of the prototype. The lack of input of the third pulse-width signal with a relative duration of Θ ₃ preserves the appearance of the functions reproduced by the prototype.

Claims (1)

A multiplier dividing device comprising a reversible counter, two AND elements, two binary frequency multipliers, an input of the first and an input of a second reference frequency, the first of these inputs being connected to the frequency input of the first binary frequency multiplier, the code input of which is connected to the code input of the device, and the output is connected to the first input of the first AND element, the second input of which is connected to the input of the first pulse-width signal, and the output is connected to the summing input of the reverse counter, the output of which is connected to the code the output of the device and the code input of the second binary frequency multiplier, and the output of this multiplier is connected to the frequency output of the device and to the first input of the second AND element, the second input of which is connected to the input of the second pulse-width signal, characterized in that two OR elements are introduced into the device and the third element And, the first input of which is combined with the first input of the second element And, the second input is connected to the input of the third pulse-width signal, and the outputs of the second and third elements And are connected respectively to the first and the second inputs of the first OR element, the output of which is connected to the subtracting input of the reverse counter, the input of the second reference frequency being connected to the third input of the second AND element and to the first input of the second OR element, and the input of the third reference frequency to the third input of the third AND element and the second input of the second OR element, the output of which is connected to the frequency input of the second binary frequency multiplier.

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