RU2374684C1 - Parallel-conveyor device for vectorisation of aerospace images of earth surface - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: invention may be used to build vector description of urban development elements on the basis of aerospace images of Earth surface in creation of electronic maps for geoinformation systems. Device comprises processor module, comprising control processor and unit of vectorisation, information interface, main memory controller, main memory, the first graphical module, comprising the first graphical processor and the first buffer memory, the second graphical module, comprising the second graphical processor and the second buffer memory, the third graphical module, comprising the third graphical processor and the third buffer memory, controller of image input-output, external memory.

EFFECT: reduction of time expenses.

3 dwg

Description

The invention relates to computer technology and can be used to build a vector description of urban development elements from aerospace images of the earth's surface when creating electronic maps for geographic information systems.

A device for isolating image contours (SU 1253337 A1), comprising a sequentially arranged matrix of photosensitive elements, a matrix of threshold discriminators, a signal processing unit and an information display unit, is known.

The disadvantage of this device is the low accuracy of the contour selection, due to the independent processing when selecting the contours of each pixel individually, without taking into account the location of neighboring pixels of the analyzed circuit, as well as the inability to form a vector description of the contours of elements (objects) in the image.

The closest device is a multiprocessor vector computer (RU 2113010 C1) containing a vector main internal memory connected via a multiply connected wide format information interface with a central control processor, an input input subsystem and at least one central processor part including a vector arithmetic device containing 2m (m = 0.1 ...) multi-format pipelined arithmetic processors, each of which contains a control node, register memory and pipelined arith metic device.

The disadvantage of this device is the low speed of image processing in the case of using a device for vectorization of the image, which is caused by the inefficient use of computing resources of the same structure arithmetic processors when performing this task.

The technical task of the device is to reduce the time spent on constructing a vector description of the elements of urban development from aerospace images of the earth's surface.

The problem is solved in that a vectorization unit, a RAM controller, RAM, a first graphic module consisting of a first graphic processor and a first buffer memory, a second graphic module consisting of a second graphic processor are additionally introduced into a multiprocessor vector computer containing a control processor and an information interface and a second buffer memory, a third graphics module consisting of a third graphics processor and a third buffer memory, an image input-output controller, an external memory, the first the input-output CI of the control processor is connected to the control input-output CI of the vectorization unit, the output of address A and the data input-output D of which are connected to the first input of the address AR and the first data input-output DP of the RAM controller, respectively; the output of the address AM and the second data input-output DM of the RAM controller are connected to the input of the address A and the data input-output D of the RAM, respectively; the second input of the address A of the RAM controller via the information interface is connected to the first output of the address A of the first GPU, to the first output of the address A of the second GPU, to the first output of the address A of the third GPU and to the first output of the address A of the image input-output controller; the third input-output data D of the RAM controller through the information interface is connected to the first input-output data D of the first GPU, to the first input-output data D of the second GPU, to the first input-output data D of the third GPU and to the first input-output data D of an image input-output controller; the second output of the address AM and the second data input-output DM of the first GPU are connected to the input of the address A and the data input-output D of the first buffer memory, respectively; the second output of the address AM and the second data input-output DM of the second GPU are connected to the input of the address A and the data input-output D of the second buffer memory, respectively; the second output of the address AM and the second data input-output DM of the third GPU are connected to the input of the address A and the data input-output D of the third buffer memory, respectively; the second output of the address AE and the second data input-output DE of the image input-output controller are connected to the input of the address A and the data input-output D of the external memory, respectively; the second input-output C of the control processor using the information interface is connected to the control input-output C of the first graphic processor, with the control input-output C of the second graphic processor, with the control input-output C of the third graphic processor and the control input-output C of the input controller - image output.

The invention is illustrated by drawings, where Fig. 1 shows a block diagram of a device for vectorizing aerospace images of the earth's surface, Fig. 2 shows an algorithm for operating the device in serial mode, and Fig. 3 shows an algorithm for operating the device in a conveyor mode.

A device for vectorizing aerospace images of the earth's surface contains a processor module 1, consisting of a control processor 1.1 and a vectorization block 1.2, a RAM controller 2, RAM 3, a first graphic module 4, consisting of a first graphic processor 4.1 and a first buffer memory 4.2, a second graphic module 5 consisting of a second graphics processor 5.1 and a second buffer memory 5.2, a third graphics module 6, consisting of a third graphics processor 6.1 and a third buffer memory 6.2, an image input-output controller 7, external memory 8, information interface 9, and the first input-output CI of the control processor 1.1 is connected to the input-output of the control CI of the vectorization block 1.2, the output of address A and data input-output D of which are connected to the first input of the address AP and the first input - data output of the DP controller RAM 2, respectively; the output of the address AM and the second data input-output DM of the RAM controller 2 are connected to the input of the address A and the data input-output D of the RAM 3, respectively; the second input of address A of the RAM controller 2 through the information interface 9 is connected to the first output of address A of the first GPU 4.1, to the first output of address A of the second GPU 5.1, to the first output of address A of the third GPU 6.1 and to the first output of address A of the input controller- image output 7; the third data input-output D of the RAM controller 2 is connected via an information interface 9 to the first data input-output D of the first GPU 4.1, to the first data input-output D of the second GPU 5.1, to the first data input-output D of the third GPU 6.1 and to the first input-output data D of the controller input-output image 7; the second output of the address AM and the second data input-output DM of the first GPU 4.1 are connected to the input of the address A and the data input-output D of the first buffer memory 4.2, respectively; the second output of the address AM and the second data input-output DM of the second GPU 5.1 are connected to the input of the address A and the data input-output D of the second buffer memory 5.2, respectively; the second output of the address AM and the second data input-output DM of the third GPU 6.1 are connected to the input of the address A and the data input-output D of the third buffer memory 6.2, respectively; the second output of the address AE and the second data input-output DE of the image input-output controller 7 are connected to the input of the address A and the data input-output D of the external memory 8, respectively; the second input-output C of the control processor 1.1 using the information interface 9 is connected to the input-output of the control From the first GPU 4.1, with the input-output of the control From the second GPU 5.1, with the input-output of the control From the third GPU 6.1 and with the input- control output From the image I / O controller 7.

The device operates as follows.

When the device starts up, the first image is processed in sequential mode. For this, the control processor 1.1 sets the image input command code at the second input-output C, the incoming information interface 9 to the control input-output C of the image input-output controller 7. Upon receipt of the image input command code, the image input-output controller 7 performs line-by-line image reading from the external memory 8 (block 1 of the algorithm in figure 2), setting the address of the image line at the second output of the address AE, which is input to the address A of the external memory 8. Upon receipt of the address, the external memory 8 gives the corresponding image line through the data input-output D to the second data input-output DE of the image input-output controller 7. The input-output controller 7 transfers the received image line-by-bit through the RAM controller 2 to RAM 3, for which the address A forms the address at the first output image lines coming through the information interface 9 to the second input of the address A of the RAM controller 2, and to the first data input-output D sends an image line element, which through the information interface 9 goes to the third data input-output D RAM controller 2. The RAM controller 2 transfers the received address to the input of the address A of RAM 3 and the image line elements to the data input / output D of RAM 3, which writes the received image line to the specified address. Upon completion of the image reading operation, the image input / output controller 7 through the control input-output C gives a confirmation code for receiving data to the second input-output C of the control processor 1.1, by which the control processor 1.1 sets the image copy command code to the first graphic on the second input-output C the processor arriving through the information interface 9 to the input-output control From the first graphic processor 4.1.

The first GPU 4.1 using the RAM controller 2 in direct access to memory (DAP) mode reads the image from RAM 3 line by line and writes it to the first buffer memory 4.2 (algorithm block 2 in FIG. 2), for which the first GPU 4.1 the first output of address A generates the address of the image line coming through the information interface 9 and the RAM controller 2 to the input of the address A of the RAM 3. After receiving the address of the RAM 3, it element-wise outputs the indicated image line to the data input-output D, from where the line goes to the second th input-output data DM controller RAM 2, which feeds the received data through the third input-output data D to the first input-output data D of the first GPU 4.1. The first graphics processor 4.1 transfers the image line by element to the input / output of data D of the first buffer memory 4.2, forming the address of the line to be copied at the input of the address A of the first buffer memory 4.2, after which the first buffer memory 4.2 writes the image line to the specified address. At the end of the image copy operation, the first graphic processor 4.1 submits a data copy confirmation code to the second input-output C of the control processor 1.1 through the information interface 9. Similarly, the image is copied from RAM 3 to the second buffer memory 5.2 (block 3 of the algorithm in FIG. 2) and the third buffer memory 6.2 (block 4 of the algorithm in FIG. 2). Upon completion of the copying of the image by all the GPUs, the control processor 1.1 issues a processing command code at the second input-input C, which through the information interface 9 is fed to the control input-output C of the first graphic processor 4.1, control input-output C of the second graphic processor 5.1, input- control output From the third GPU 6.1. Upon receipt of the processing command code, each of the GPUs processes a copy of the image stored in the buffer memory of the corresponding graphics module.

The first graphic processor 4.1 differentiates the aerospace image (block 5 of the algorithm in FIG. 2) by convolution with masks representing discrete approximations of partial derivatives of the Gauss function [Elder J.H. Local Scale Control for Edge Detection and Blur Estimation [Text] / James. H. Elder, Steven W. Zuckler // IEEE Transactions on Pattern Analysis and Machine Intelligence. - Vol.20, No7. - 1998. - pp. 699-716]. The second graphic processor 5.1 performs the creation of a cluster representation of the aerospace image (block 6 of the algorithm in figure 2) in a space containing brightness and geometric features [R. Gonzalez Digital image processing [Text] / R. Gonzalez, R. Woods // M .: Technosphere, 2006, 1072 pp.]. The third graphics processor 6.1 performs the calculation of the coefficients of the discrete Fourier transform of the aerospace image (block 7 of the algorithm in figure 2) [Soifer VA Methods of computer image processing / Ed. V.A.Soyfera - 2nd ed., Rev. - M .: FIZMATLIT, 2003. - 784 p.]. At the end of the processing, each graphic processor through the information interface 9 supplies to the second input-output C of the control processor 1.1 a processing completion code.

Having received the processing completion codes from all the GPUs, the control processor 1.1 at the second input-output C sets the command code for copying the processing results of the first GPU, which through the information interface 9 is fed to the control input-output C of the first GPU 4.1. Upon receipt of this code, the first graphics processor 4.1 using the RAM controller 2 in the PDL mode performs line-by-line recording of the resulting contour image in RAM 3 from the buffer memory 4.2 (block 8 of the algorithm in FIG. 2). To do this, the first graphics processor 4.1 sets the second address of the address AM to the line address of the contour image, which is fed to the input of address A of the first buffer memory 4.2. Upon receipt of the address of the line, the buffer memory 4.2 element-by-element outputs the corresponding image line D to the second input-output DM of the first GPU 4.1, which transfers the image line-by-element through the information interface 9 to the third data input-output D of the RAM controller 2 and sets the corresponding address on the second input of the address A of the RAM controller 2. The RAM controller 2 transfers the received address to the input of the address A and the image line elements to the data input-output D of the RAM 3, which records the received The specified line of the contour image at the specified address. At the end of copying the contour image in RAM 3, the first graphics processor 4.1 through the information interface 9 provides the second input-output C of the control processor 1.1 with a confirmation code for copying the results. Similarly, the cluster image is recorded from the second buffer memory 5.2 in RAM 3 (block 9 of the algorithm in FIG. 2) and the frequency representation of the image from the third buffer memory 6.2 in RAM 3 (block 10 of the algorithm in FIG. 2).

After receiving confirmation codes for copying the results from all the GPUs, the control processor 1.1 sends the result processing code to the CI control input vector output 1.2 through the first CI input / output, upon receipt of which the vectorization block 1.2 creates a vector representation of objects based on the contour, cluster and frequency descriptions of the aerospace image stored in RAM 3 (block 11 of the algorithm in figure 2). Vector representation of objects [Miroshnichenko S.Yu. Recognizing hardware-software diagnostic complex [Text] / S.Yu. Miroshnichenko, V.N. Mishustin, S.V. Degtyarev // Izv. Universities. Instrument making. - T. 48, No. 2. - 2005. - P.22-27] is constructed as a set of closed vector sequences, each of which represents the contour of the object, the boundary of the cluster or image area with close values of the Fourier transform coefficients. The vector representation of objects formed in this way on an aerospace image using the RAM 2 controller is written to RAM 3. Upon completion of the construction of the vector description, vectorization block 1.2 provides the vectorization completion code to the first input-output CI of the control processor 1.1, upon receipt of which the control processor 1.1 sets the second input-output C code of the command for the issuance of results coming through the information interface to the input-output of the control From the image input-output controller 7. Input-output controller image water 7 using the RAM controller 2 reads a vector representation of the image from RAM 3 in the DAP mode and writes it to the external memory 8 (block 12 of the algorithm in figure 2) in the same way as the image is read from the external memory 8.

The device performs the processing of the second and subsequent images in the pipelined mode, which allows to increase the loading of computing units. After copying the image from RAM 3 to the buffer memory of each of the three graphic modules (blocks 1, 2, 3 of the algorithm in FIG. 3), in addition to differentiating the current image with the first GPU 4.1 (block 4 of the algorithm in FIG. 3), clustering the current image with the second graphic the processor 5.1 (block 5 of the algorithm in FIG. 3), the Fourier transform of the current image by the third graphics processor 6.1 (block 6 of the algorithm in FIG. 3) also reads the next image from the external memory 8 into RAM 3 (block 8 of the algorithm in FIG. 3) and creating a block m vectorization 1.2 of the vector representation of the previous image (block 7 of the algorithm in figure 3), the results of differentiation, clustering and Fourier transforms of which are stored in RAM 3. At the end of all these operations, the contour, cluster and frequency representations of the current image are sequentially copied from the buffer memory of each graphic module in RAM 3 using the controller RAM 2 (blocks 9, 10, 11 of the algorithm in figure 3), after which the vector representation of the previous image is written from RAM 3 to external memory 8 (block 12 a goritma in Figure 3).

The processor module 1 can be implemented on dual-core Intel Core 2 Duo or AMD Athlon x2 processors, with the first processor core serving as the control processor 1.1, the second core as a vectorization block 1.2. To implement the processor module, AMD Phenom x3 tri-core processors and Intel Core 2 Quad or AMD Phenom quad-core processors can also be used, where the first core functions as a control processor 1.1 and the other two or three core function as a vectorization block 1.2.

Graphics modules 4, 5, 6 are implemented on three nVidia GeForce 8800/9600/9800 graphics accelerators combined using nVidia SLI technology, or on three AMD ATI HD 3850/3870 graphics accelerators combined using ATI CrossFire technology.

Thus, the proposed solution allows to reduce the time spent on building a vector description of urban development elements from aerospace images of the earth’s surface by introducing into the device the first GPU 4.1, the second GPU 5.1, the third GPU 6.1 and the vectorization block 1.2, which parallelly execute in the conveyor mode differentiation, clustering, Fourier transform of the current image and vector encoding of objects in the previous image.

Claims (1)

A device for vectorizing aerospace images of the earth's surface, containing a control processor and an information interface, characterized in that a vectorization unit, a RAM controller, RAM, a first graphic module consisting of a first graphic processor and a first buffer memory, a second graphic module consisting of a second graphics processor and a second buffer memory, a third graphics module consisting of a third graphics processor and a third buffer memory, an input-output controller yes, external memory, and the first input-output of the control processor is connected to the input-output of the control unit of the vectorization, the output of the address and the input-output of the data of which are connected to the first input of the address and the first data input-output of the RAM controller, respectively; the output of the address and the second data input / output of the RAM controller are connected to the address input and the input / output of the RAM data, respectively; the second input of the address of the RAM controller through the information interface is connected to the first output of the address of the first graphic processor, to the first output of the address of the second graphic processor, to the first output of the address of the third graphic processor and to the first output of the address of the image input-output controller; the third input-output of data of the RAM controller through the information interface is connected to the first input-output of data of the first graphic processor, to the first input-output of data of the second graphic processor, to the first input-output of data of the third graphic processor and to the first input-output of data of the input- image output; the second address output and the second data input-output of the first GPU are connected to the address input and data input-output of the first buffer memory, respectively; the second address output and the second data input-output of the second GPU are connected to the address input and data input-output of the second buffer memory, respectively; the second address output and the second data input-output of the third GPU are connected to the address input and data input-output of the third buffer memory, respectively; the second address output and the second data input-output controller of the image input-output controller are connected to the address input and data input-output of the external memory, respectively; the second input-output of the control processor using the information interface is connected to the control input-output of the first graphic processor, to the control input-output of the second graphic processor, to the control input-output of the third graphic processor and to the control input-output of the image input-output controller.

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