RU2369032C1 - Method of iterative signal processing for serial modem and device to that effect (versions) - Google Patents

Abstract

FIELD: communication means.

SUBSTANCE: invention is intended for use in communication systems employed for data transport through transmission links with inter-symbol interference when high confidence of data transmission is required. According to the method of iterative processing of the signal for the serial modem (version one) in the receiving portion LLR bit strings are detected after de-interlacer and SISO decoder, sequences of preliminary bit estimates are formed, wherein CRC is checked. Series-connected second detector and second CRC evaluation block are introduced into the receiving equipment of the device (version one), along with the second and the third switches. Second version of the method, presupposes adding of the CRC code in transmitting part after the interlacer, and in the receiving part - detecting of LLR bit sequence after the SISO equaliser and interlacer, formation of the sequence of preliminary bit estimates and CRC check therein. As per the second version of the device into the transmitting part there is a specially introduced CRC - adding block, and into the receiving part - the second and the third detectors, the first and the second CRC evaluation blocks, the second and the third switches.

EFFECT: enhanced probability of correct data reception, improved noise-immunity of the communication equipment, lowered signal processing time by turbo equaliser of the serial modem through reduced number of iterations and reduced desired amount of computational resources.

4 cl, 8 dwg

Description

The present invention is intended for use in communication systems used to transmit information over communication channels with intersymbol interference (MSI), for example, multi-beam short-wave (KB) channels, in cases where high reliability of data transmission is required.

As a rule, in existing communication systems this goal (high reliability of data transmission) is achieved:

1) using an error-correcting code and methods to combat ISI in a data transmission modem;

2) using a channel protocol working "on top" of the error-correcting code.

The work of the channel protocol consists in breaking the transmitted information into fragments and adding a checksum (CRC code) to each of them, i.e. the channel protocol uses proprietary code with low redundancy - a CRC code that can detect but not correct errors. On the receiving side, fragments with incorrect checksums are rejected (in particular, they can be re-flashed via the feedback channel in the current or subsequent messaging sessions).

Currently, the most effective way to combat ISI is to use turbo-equalizers, which are devices consisting of: 1) an equalizer with a “soft” input and output — an SISO equalizer; 2) SISO decoder with “soft” input and output. The turboequalizer performs iterative processing of a signal implementation corresponding to one codeword. The output information about the bits (or symbols) received from the channel, obtained at each processing stage (at the output of the SISO decoder or SISO equalizer) in the form of the likelihood logarithm ratio (LLR), is the input information at each subsequent processing stage.

This principle is based on many signal processing methods and devices that implement them, for example, those given in [1-3].

A disadvantage of the known technical solutions is that the processing at both levels of the hierarchy occurs completely independently: the information embedded in the redundancy of the CRC code at the channel protocol level is not used at all at the signal processing stage by the modem equalizer, which eliminates distortions caused by the MCI, as well as the noise-resistant decoder code. In addition, in the absence of a channel protocol of the upper level, it is not possible to evaluate the reliability of the received information, as well as speed up its processing with high reliability.

The closest in technical essence to the proposed method (the first option) is the method presented in article [4], adopted as a prototype.

The prototype method is as follows.

. Далее последовательность бит

кодируется помехоустойчивым кодом, формируется последовательность бит

, которая перемешивается по определенному закону, формируется последовательность бит

. Последовательность бит

модулируется, формируется выходная последовательность комплексных чисел x_n, соответствующих точкам в сигнальном созвездии (символам).In the transmitting part of the communication system, the initial sequence of bits s _k (input information) is divided into fragments, a CRC code is added to each of them, a sequence of bits is formed

. Next bit sequence

encoded by error-correcting code, a sequence of bits is formed

, which is mixed according to a certain law, a sequence of bits is formed

. Bit sequence

modulated, the output sequence of complex numbers x _n corresponding to the points in the signal constellation (symbols) is formed.

(на первой итерации равны нулю), формируется последовательность LLR бит

. Последовательность LLR бит

деперемешивается, формируется последовательность LLR бит

. Последовательность LLR бит

декодируется, формируется последовательность LLR бит

. Если заданное количество итераций еще не закончилось, последовательность LLR бит

перемешивается, формируется последовательность LLR бит

, которая является априорной информацией для SISO эквалайзера. Если заданное количество итераций закончилось, последовательность LLR бит

детектируется, формируется последовательность предварительных оценок бит

. Последовательность предварительных оценок бит

разбивается на фрагменты, в которых проверяется CRC, формируется выходная последовательность бит

. Причем благодаря CRC коду известно, какие фрагменты

приняты с ошибками, а какие - без.In the receiving part of the communication system, the signal y (t) received from the communication channel (input information) is demodulated, a sequence of complex numbers at _n corresponding to the points in the signal constellation (received symbols) is formed. The demodulated signal at _n is equalized taking into account a priori LLR bits

(equal to zero at the first iteration), a sequence of LLR bits is formed

. LLR bit sequence

de-shuffled, a sequence of LLR bits is formed

. LLR bit sequence

decoded, a sequence of LLR bits is formed

. If the specified number of iterations has not yet ended, the LLR bit sequence

shuffled, a sequence of LLR bits is formed

, which is a priori information for the SISO equalizer. If the set number of iterations has ended, the LLR bit sequence

detected, formed a sequence of preliminary estimates of bits

. Bit prediction sequence

broken into fragments in which CRC is checked, the output bit sequence is formed

. Moreover, thanks to the CRC code, it is known which fragments

accepted with errors, and which without.

The disadvantage of the prototype method is that the information contained in the redundancy of the CRC code of the channel protocol is not used in any way at the signal processing stage by the modem equalizer, which eliminates distortions caused by the MCI, as well as the error-correcting code decoder.

, которая кодируется помехоустойчивым кодом, формируется последовательность бит

, которая перемешивается по определенному закону, формируется последовательность бит

, которая модулируется, формируется выходная последовательность комплексных чисел х_n, соответствующих точкам в сигнальном созвездии, в приемной части системы связи принимаемый из канала связи сигнал y(t) демодулируется, формируется последовательность комплексных чисел у_n, соответствующих точкам в сигнальном созвездии, далее демодулированный сигнал у_n подвергается эквалайзингу с учетом априорных значений LLR бит

, которые на первой итерации равны нулю, формируется последовательность LLR бит

, которая деперемешивается, формируется последовательность LLR бит

которая декодируется, формируется последовательность LLR бит

, если заданное количество итераций еще не закончилось, то последовательность LLR бит

перемешивается, формируется последовательность LLR бит

, которая является априорной информацией для SISO эквалайзера, согласно изобретению, в приемной части детектируют последовательность LLR бит

, формируют последовательность предварительных оценок бит

, разбивают на фрагменты последовательность предварительных оценок бит

, в которых проверяют CRC, фрагменты последовательности LLR бит

, для которых CRC совпала, заменяют значениями ∞, детектируют последовательность LLR бит

, формируют последовательность предварительных оценок бит

, далее ее разбивают на фрагменты, в которых проверяют CRC, формируют последовательность оценок бит

, фрагменты последовательности LLR бит

, для которых CRC совпала, заменяют значениями ∞, после окончания заданного количества итераций полученная после проверки CRC последовательность оценок бит

становится выходной, причем благодаря CRC коду выявляют фрагменты, принятые с ошибками.To eliminate this drawback in the method, namely, in the transmitting part of the communication system, the initial sequence of bits s _{k is} divided into fragments, to each of which a CRC code is added, a sequence of bits is formed

, which is encoded by an error-correcting code, a sequence of bits is formed

, which is mixed according to a certain law, a sequence of bits is formed

Which is modulated, generates an output sequence of complex numbers x _n, corresponding to the points in the signal constellation in the receiver portion of the communication system received from the channel signal y (t) demodulated, forming a sequence of complex numbers y _n, corresponding to the points in the signal constellation, then the demodulated signal _n is equalized taking into account a priori LLR bits

which are equal to zero at the first iteration, an LLR bit sequence is formed

which is de-mixed, an LLR bit sequence is formed

which is decoded, a sequence of LLR bits is formed

if the specified number of iterations has not yet ended, then the sequence of LLR bits

shuffled, a sequence of LLR bits is formed

, which is a priori information for the SISO equalizer according to the invention, the LLR bit sequence is detected in the receiving part

form a sequence of preliminary estimates of bits

fragment into a sequence of preliminary estimates of bits

in which the CRC is checked, fragments of the LLR bit sequence

for which the CRC is the same, replace with the values ∞, detect the sequence of LLR bits

form a sequence of preliminary estimates of bits

, then it is divided into fragments in which the CRC is checked, a sequence of bit estimates is formed

, fragments of the LLR bit sequence

, for which the CRC is the same, is replaced by the values ∞, after the end of the specified number of iterations, the sequence of bit estimates obtained after the CRC check

becomes output, and thanks to the CRC code, fragments received with errors are detected.

The proposed method for iterative signal processing for a serial modem is as follows.

. Далее последовательность бит

кодируется помехоустойчивым кодом, формируется последовательность бит

, которая перемешивается по определенному закону, формируется последовательность бит

. Последовательность бит

модулируется, формируется выходная последовательность комплексных чисел х_n, соответствующих точкам в сигнальном созвездии (символам). То есть в передающей части предлагаемый способ совпадает со способом-прототипом.In the transmitting part of the communication system, the initial sequence of bits s _k (input information) is divided into fragments, a CRC code is added to each of them, a sequence of bits is formed

. Next bit sequence

encoded by error-correcting code, a sequence of bits is formed

, which is mixed according to a certain law, a sequence of bits is formed

. Bit sequence

modulated, the output sequence of complex numbers x _n corresponding to the points in the signal constellation (symbols) is formed. That is, in the transmitting part, the proposed method coincides with the prototype method.

(на первой итерации равны нулю), формируется последовательность LLR бит

. Последовательность LLR бит

деперемешивается, формируется последовательность LLR бит

. Последовательность LLR бит

детектируется, формируется последовательность предварительных оценок бит

. Последовательность предварительных оценок бит

разбивается на фрагменты, в которых проверяется CRC. Фрагменты последовательности LLR бит

, для которых CRC совпала, заменяются значениями LLR, соответствующими надежности решений на выходе устройства проверки контрольных сумм CRC кода, т.е.

где p_err - вероятность ошибки в бите фрагмента с правильной контрольной суммой CRC кода. Т.е., практически, можно считать решения о принятых битах, принадлежащих фрагментам с правильными контрольными суммами, абсолютно надежными и полагать их равными ∞. Последовательность LLR бит

декодируется, формируется последовательность LLR бит

. Последовательность LLR бит

детектируется, формируется последовательность предварительных оценок бит

. Последовательность предварительных оценок бит

разбивается на фрагменты, в которых проверяется CRC, формируется последовательность оценок бит

. Фрагменты последовательности LLR бит

, для которых CRC совпала, заменяются значениями ∞ (LLR для известных бит). Если заданное количество итераций еще не закончилось, последовательность LLR бит

перемешивается. Формируется последовательность LLR бит

, которая является априорной информацией для SISO эквалайзера. Если заданное количество итераций закончилось, полученная после проверки CRC последовательность оценок бит

становится выходной. Причем благодаря CRC коду известно, какие фрагменты

приняты с ошибками, а какие - без. В случае, если на какой-либо итерации турбо эквалайзера все биты окажутся декодированы правильно, итерации можно прекратить досрочно.In the receiving part of the communication system, the signal y (t) received from the communication channel (input information) is demodulated, a sequence of complex numbers at _n corresponding to the points in the signal constellation (received symbols) is formed. Next, the demodulated signal at _n is equalized taking into account a priori LLR bits

(equal to zero at the first iteration), a sequence of LLR bits is formed

. LLR bit sequence

de-shuffled, a sequence of LLR bits is formed

. LLR bit sequence

detected, formed a sequence of preliminary estimates of bits

. Bit prediction sequence

breaks into fragments in which CRC is checked. Fragments of the LLR bit sequence

, for which the CRC is the same, are replaced by LLR values corresponding to the reliability of the solutions at the output of the CRC code checksum verification device, i.e.

where p _err is the probability of error in the bit of the fragment with the correct CRC checksum. That is, in practice, we can consider the decisions about the received bits belonging to the fragments with the correct checksums to be absolutely reliable and set them equal to ∞. LLR bit sequence

decoded, a sequence of LLR bits is formed

. LLR bit sequence

detected, formed a sequence of preliminary estimates of bits

. Bit prediction sequence

broken into fragments in which CRC is checked, a sequence of bit estimates is formed

. Fragments of the LLR bit sequence

, for which the CRC matches, are replaced by ∞ (LLR for known bits). If the specified number of iterations has not yet ended, the LLR bit sequence

mixes up. A sequence of LLR bits is formed

, which is a priori information for the SISO equalizer. If the specified number of iterations has ended, the sequence of bit estimates obtained after checking the CRC

It becomes a day off. Moreover, thanks to the CRC code, it is known which fragments

accepted with errors, and which without. If at any iteration of the turbo equalizer all the bits are decoded correctly, iterations can be terminated early.

Thus, the proposed method (the first option) allows you to use the information embedded in the redundancy of the CRC code at the level of the channel protocol, both when processing the signal with the equalizer of the modem, and in the process of decoding the error-correcting code, and can be used to process signals in communication systems, initially not designed for its use. As a result, compatibility of receiving equipment using the proposed method with the previous fleet of transmitting devices is achieved, but with the achievement of higher characteristics of communication quality and speed in the new receiving equipment.

The closest in technical essence to the proposed device (the first option) is the device described in [4], taken as a prototype.

The prototype device consists of two parts: transmitting and receiving, its block diagram is shown in figa, b.

A block diagram of the transmitting part of the prototype device is presented in figa, where it is indicated:

1 - block add CRC;

2 - encoder;

3 - interleaver;

4 - modulator;

s _k is the initial sequence of bits;

- последовательность бит с добавлением CRC;

- a sequence of bits with the addition of CRC;

- закодированная последовательность бит;

- encoded sequence of bits;

- перемешанная последовательность бит;

- mixed sequence of bits;

x _n is a sequence of complex numbers corresponding to points in the signal constellation (symbols).

The transmitting part of the prototype device contains a series-connected unit for adding CRC 1, encoder 2, interleaver 3 and modulator 4, the output of which is the output of the device. The input of the adding block CRC 1 is the input of the transmitting part.

The transmitting part of the prototype device works as follows.

поступает на кодер 2, который производит кодирование этой последовательности помехоустойчивым кодом, в результате чего образуется новая последовательность бит

, которая поступает на перемежитель 3, где происходит ее перемешивание по определенному закону. Перемешанная последовательность бит

поступает на модулятор 4, формирующий последовательность символов в виде комплексных чисел x_n, соответствующих точкам в выбранном сигнальном созвездии. В дальнейшем эта последовательность символов преобразуется передающей аппаратурой в сигнал, передаваемый по какому-либо каналу связи с МСИ, например по KB каналу с многолучевым распространением.At the input of the device receives a sequence of bits s _k from any source of information. The CRC add block 1 divides it into fragments, adding CRC to them. The resulting bit sequence

enters encoder 2, which encodes this sequence with an error-correcting code, resulting in a new sequence of bits

, which enters the interleaver 3, where it is mixed according to a certain law. Mixed bit sequence

arrives at modulator 4, forming a sequence of characters in the form of complex numbers x _n corresponding to points in the selected signal constellation. In the future, this sequence of characters is converted by the transmitting equipment into a signal transmitted via any communication channel with the ISI, for example, on a KB channel with multipath propagation.

The block diagram of the receiving part of the prototype device is presented in figb, where it is indicated:

3 - interleaver;

5 - matched demodulator filter;

6 - SISO equalizer;

7 - deinterleaver;

8 - SISO decoder;

9 - switch;

10 - detector;

11 - block check CRC;

y (t) is the signal received from the communication channel;

y _n is a sequence of complex numbers at the output of the demodulator;

- последовательность LLR бит на выходе SISO эквалайзера;

- LLR bit sequence at the output of the SISO equalizer;

- то же после деперемежителя;

- the same after de-interleaver;

- то же после SISO декодера;

- the same after the SISO decoder;

- то же после перемежителя;

- the same after the interleaver;

- последовательность оценок бит после детектора;

- a sequence of bit estimates after the detector;

- последовательность окончательных оценок принятых информационных бит.

- a sequence of final evaluations of the received information bits.

The receiving part of the prototype device contains a serially connected matched filter of the demodulator 5, SISO equalizer 6, de-interleaver 7 and SISO decoder 8, the output of which is connected to the input of the switch 9, the first output of which is connected through the detector 10 to the input of the CRC 11 verification unit, the output of which is the output receiving part. The second output of the switch 9 through the interleaver 3 is connected to the second input of the SISO equalizer 6. The input of the matched filter demodulator 5 is the input of the receiving part.

The receiving part of the prototype device works as follows.

. Деперемежитель 7 восстанавливает исходный порядок следования LLR бит

, соответствующий исходной закодированной последовательности бит

. SISO декодер 8 декодирует последовательность LLR бит

, формируя на своем выходе новую последовательность LLR бит

, более правдоподобную, благодаря исправляющим свойствам используемого помехоустойчивого кода. Последовательность LLR бит

через переключатель 9 подается на перемежитель 3, который формирует перемешанную последовательность LLR бит

, которая подается на второй вход SISO эквалайзера 6 в качестве априорных LLR бит. SISO эквалайзер 6 вновь формирует (уже уточненные) LLR бит

и т.д. Данная итеративная процедура (турбоэквалайзинг) повторяется заданное количество раз, после чего переключатель 9 переводится в другое положение, и выход SISO декодера 8 подается на детектор 10, который формирует последовательность оценок бит

, подаваемую на блок проверки CRC 11. Последовательность окончательных оценок принятых информационных бит

с выхода блока проверки CRC 11 затем передается в какой-либо приемник информации. Фрагменты информации, для которых CRC не совпала, будут перезапрошены у приемной стороны канальным протоколом верхнего уровня.The signal y (t) received from the communication channel, distorted by the MSI, is mixed with noise and fed to the matched filter of demodulator 5, where it is converted into a sequence of input samples in the form of complex numbers y _n . Then SISO equalizer 6 forms an LLR bit sequence from them

. The deinterleaver 7 restores the original order of LLR bits

corresponding to the original encoded bit sequence

. SISO decoder 8 decodes LLR bit sequence

forming at its output a new sequence of LLR bits

more plausible due to the corrective properties of the error-correcting code used. LLR bit sequence

through the switch 9 is fed to the interleaver 3, which forms a mixed sequence of LLR bits

which is applied to the second input of the SISO equalizer 6 as a priori LLR bits. SISO Equalizer 6 re-generates (already specified) LLR bits

etc. This iterative procedure (turbo equalization) is repeated a predetermined number of times, after which the switch 9 is moved to another position, and the output of the SISO decoder 8 is supplied to the detector 10, which forms a sequence of bit estimates

supplied to the CRC 11. The sequence of final evaluations of the received information bits

from the output of the verification unit CRC 11 is then transmitted to any information receiver. Fragments of information for which the CRC did not match will be re-requested at the receiving side by the upper layer channel protocol.

At each stage of the signal processing by the turboequalizer (evaluating SISO symbols by EQ 6 or decoding the SISO symbol bits by decoder 8), the so-called “soft” symbol or bit estimation is performed, which is transmitted to the next processing stage as an input (for SISO decoder 8) or a priori (for SISO equalizer 6) information. At the same time, the information contained in the test bits of the CRC code is not taken into account in any way, but is used only after the end of the turboequalizer’s operation, exclusively to detect the errors made, but not to correct them.

Thus, the disadvantage of the prototype device is that the information contained in the redundancy of the CRC code of the channel protocol is not used in any way at the signal processing stage by the modem equalizer, which eliminates distortions caused by the MCI, as well as the error-correcting code decoder.

To eliminate this drawback, an iterative signal processing device for a serial modem, consisting of a transmitting and receiving part, the transmitting part contains serially connected CRC adding unit, an encoder, an interleaver and a modulator, the output of which is the output of the transmitting part, and its input is the input of the CRC adding unit , the receiving part contains a serially connected matched demodulator filter, SISO equalizer and deinterleaver, as well as a SISO decoder, the output of which is connected to the first input of the first of the switch, the output of which through the interleaver is connected to the second input of the SISO equalizer, the first detector and the first CRC check unit are connected in series, the input of the matched demodulator filter is the input of the receiving part, according to the invention, are introduced into the receiving part - the second detector and the second CRC check unit connected in series as well as second and third switches, the output of the second CRC check unit being connected to the first input of the second switch, the second input of which is an input for LLR values bit, and the output is connected to the input of the SISO decoder, the second input of the first switch is an input for LLR values of known bits, in addition, the output of the deinterleaver is connected to the third input of the second switch, the output of the SISO decoder is connected to the input of the first detector, the first output of the first CRC check unit is connected to the input of the third switch, the output of which is the output of the receiving part of the device, the second output of the first CRC check unit is connected to the third input of the first switch, the output of the deinterleaver is connected to the input of the second th detector.

The proposed device consists of two parts: transmitting and receiving, its block diagram is shown in figa, b.

The transmitting part of the proposed device completely coincides with the transmitting part of the prototype device (figa), its work is also similar to the transmitting part of the prototype device.

The block diagram of the receiving part of the proposed device (turboequalizer) is presented in figb, where it is indicated:

3,5 - 8 - as in the prototype diagram;

9.1, 9.2, 9.3 - the first, second and third switches;

10.1, 10.2 - the first and second detectors;

11.1,11.2 - the first and second blocks of the CRC check;

- последовательность предварительных оценок бит;

- a sequence of preliminary estimates of bits;

other sequences and signals - as in the prototype diagram;

∞ - LLR value for known bits.

The receiving part of the proposed device contains a serially connected matched filter of a demodulator 5, SISO equalizer 6, a de-interleaver 7, a second detector 10.2, a second CRC verification unit 11.2, the output of which is connected to the first input of the second switch 9.2, the output of which is through a series-connected SISO decoder 8, the first detector 10.1 and the first CRC verification unit 11.1 is connected to the input of the third switch 9.3, the output of which is the output of the receiving part of the proposed device. In addition, the output of the SISO decoder 8 is connected to the first input of the first switch 9.1, the output of which through the interleaver 3 is connected to the second input of the SISO equalizer 6, and the second input of the first switch 9.1 is an input for LLR values of known bits. The output of the de-interleaver 7 is connected to the third input of the second switch 9.2, the second input of which is an input for LLR values of known bits. The second output of the first CRC test block 11.1 is connected to the third input of the first switch 9.1. The input of the matched filter demodulator 5 is the input of the receiving part of the proposed device.

The receiving part of the proposed device works similarly to the receiving part of the prototype device, with the exception of two points.

, сформированная в деперемежителе 7, поступает на вход второго детектора 10.2, где преобразуется в последовательность предварительных оценок бит

. Второй блок проверки CRC 11.2 проверяет CRC отдельных фрагментов бит данной последовательности и, если CRC не совпала (т.е. фрагмент принят с ошибками), передает через второй переключатель 9.2 на SISO декодер 8 последовательность LLR бит

(т.е. в точности, как в прототипе). Если же CRC совпала, то на SISO декодер 8 подаются значения LLR, соответствующие, практически, точно известным битам информации, т.е. ∞. Во-вторых, последовательность LLR

, сформированная в SISO декодере 8, в отличие от прототипа, поступает на вход первого детектора 10.1, где преобразуется в последовательность предварительных оценок бит

. Первый блок проверки CRC 11.1 проверяет CRC отдельных фрагментов бит и, если CRC не совпала (т.е. фрагмент принят с ошибками), передает через первый переключатель 9.1 на перемежитель 3 последовательность LLR

(в точности, как в прототипе). Если же CRC совпала, то на перемежитель 3 подаются LLR, соответствующие, практически, точно известным битам информации, т.е. ∞. В случае, если на какой-либо итерации турбоэквалайзера все биты окажутся декодированы правильно, итерации можно прекратить досрочно и перевести третий переключатель 9.3 в положение, при котором на выход устройства будет подана последовательность окончательных оценок принятых информационных бит

.First, the LLR bit sequence

, formed in the deinterleaver 7, is fed to the input of the second detector 10.2, where it is converted into a sequence of preliminary estimates of bits

. The second CRC verification block 11.2 checks the CRC of individual bit fragments of a given sequence and, if the CRC does not match (i.e., the fragment was received with errors), passes the LLR bit sequence through the second switch 9.2 to SISO decoder 8

(i.e., exactly as in the prototype). If the CRC coincides, then LLR values corresponding to, practically, exactly known bits of information, are sent to SISO decoder 8, i.e. ∞. Secondly, the LLR sequence

, formed in SISO decoder 8, in contrast to the prototype, is fed to the input of the first detector 10.1, where it is converted into a sequence of preliminary estimates of bits

. The first CRC verification block 11.1 checks the CRC of individual bit fragments and, if the CRC does not match (i.e., the fragment was received with errors), passes the LLR sequence through the first switch 9.1 to interleaver 3

(exactly as in the prototype). If the CRC is the same, then LLR corresponding to practically known information bits, i.e. ∞. If at any iteration of the turbo equalizer all the bits are decoded correctly, iterations can be stopped ahead of time and put the third switch 9.3 in the position at which the sequence of final evaluations of the received information bits will be sent to the output of the device

.

Thus, the proposed device (the first option) allows you to use the information embedded in the redundancy of the CRC code at the channel protocol level, both when processing the signal with the equalizer of the modem, and in the process of decoding the error-correcting code, and can be used to process signals in communication systems, initially not designed for its use. As a result, compatibility of receiving equipment using the proposed method with the previous fleet of transmitting devices is achieved, but with the achievement of higher characteristics of communication quality and speed in the new receiving equipment.

When developing new equipment and in other cases when the compatibility of the new receiving equipment with the old fleet of transmitting devices is not required, as well as in situations where it is necessary to preserve the independence of information processing at various levels of the hierarchy (channel protocol, error-correcting code), for example, when providing communication equipment “Pass-through” channel for any other equipment, another variant of the proposed method and device construction is possible, in which the CRC code is added at the noise-immunity code level and SISO equalizer.

The closest in technical essence to the proposed method (second option) is the method described in article [5], adopted as a prototype.

The prototype method is as follows.

, которая перемешивается по определенному закону, формируется последовательность бит

. Последовательность бит

модулируется, формируется выходная последовательность комплексных чисел x_n, соответствующих точкам в сигнальном созвездии (символам).In the transmitting part of the communication system, the initial sequence of bits s _k (input information) is encoded by an error-correcting code, a sequence of bits is formed

, which is mixed according to a certain law, a sequence of bits is formed

. Bit sequence

modulated, the output sequence of complex numbers x _n corresponding to the points in the signal constellation (symbols) is formed.

(на первой итерации равны нулю), формируется последовательность LLR бит

. Последовательность LLR бит

деперемешивается, формируется последовательность LLR бит

. Последовательность LLR бит

декодируется, формируется последовательность LLR бит М_к. Если заданное количество итераций еще не закончилось, последовательность LLR бит М_к перемешивается, формируется последовательность LLR бит

, которая является априорной информацией для SISO эквалайзера. Если заданное количество итераций закончилось, последовательность LLR бит М_к детектируется, формируется выходная последовательность бит

.In the receiving part of the communication system, the signal y (t) received from the communication channel (input information) is demodulated, a sequence of complex numbers at _n corresponding to the points in the signal constellation (received symbols) is formed. The demodulated signal at _n is equalized taking into account a priori LLR bits

(equal to zero at the first iteration), a sequence of LLR bits is formed

. LLR bit sequence

de-shuffled, a sequence of LLR bits is formed

. LLR bit sequence

decoded, the sequence of LLR bits M _to . If the specified number of iterations has not yet ended, the LLR bit sequence M _{to is} mixed, the LLR bit sequence is formed

, which is a priori information for the SISO equalizer. If the specified number of iterations has ended, the LLR sequence of the bit M _{to is} detected, the output sequence of bits

.

The disadvantage of the prototype method is the inability to assess the reliability of the received information, as well as speeding up its processing, if this reliability is high.

, которая перемешивается по определенному закону, формируется последовательность бит

, в приемной части системы связи принимаемый из канала связи сигнал y(t) демодулируется, формируется последовательность комплексных чисел у_n, соответствующих точкам в сигнальном созвездии, последовательность LLR бит

деперемешивается, формируется последовательность LLR бит

, которая декодируется, формируется последовательность LLR бит М_к, если заданное количество итераций закончилось, то полученная после декодирования последовательность LLR бит М_к детектируется, формируется последовательность окончательных оценок бит

, являющаяся выходной, согласно изобретению, в передающей части последовательность бит

разбивают на фрагменты, к каждому из которых добавляют CRC код, формируют последовательность бит

, которую модулируют, формируют выходную последовательность комплексных чисел x_n, соответствующих точкам в сигнальном созвездии, в приемной части демодулированный сигнал у_n подвергают эквалайзингу с учетом априорных значений LLR бит

, которые на первой итерации равны нулю, формируют последовательность LLR бит

, детектируют последовательность LLR бит

, формируют последовательность предварительных оценок бит

, ее разбивают на фрагменты, в которых проверяют CRC, фрагменты последовательности LLR бит

, для которых CRC совпала, заменяют значениями ∞, если заданное количество итераций еще не закончилось, то последовательность LLR бит М_к перемешивают, формируют последовательность LLR бит

, которую детектируют, формируют последовательность предварительных оценок бит

, ее разбивают на фрагменты, в которых проверяют CRC, фрагменты последовательности LLR бит

, для которых CRC совпала, заменяют значениями ∞, последовательность LLR бит

является априорной информацией для SISO эквалайзера.To eliminate this drawback in the method, which consists in the fact that in the transmitting part of the communication system, the initial sequence of bits s _k is encoded by a noise-resistant code, a sequence of bits is formed

, which is mixed according to a certain law, a sequence of bits is formed

, in the receiving part of the communication system, the signal y (t) received from the communication channel is demodulated, a sequence of complex numbers at _n corresponding to points in the signal constellation is formed, a sequence of LLR bits

de-shuffled, a sequence of LLR bits is formed

which is decoded, the LLR bit M _k sequence is formed, if the specified number of iterations has ended, the LLR bit M _k received after decoding is detected, a sequence of final bit estimates is formed

, which is the output, according to the invention, in the transmitting part, a sequence of bits

broken into fragments, to each of which add a CRC code, form a sequence of bits

which is modulated, the output sequence of complex numbers x _n corresponding to the points in the signal constellation is formed, in the receiving part, the demodulated signal at _n is equalized taking into account a priori LLR bits

, which are equal to zero at the first iteration, form a sequence of LLR bits

detect LLR bit sequence

form a sequence of preliminary estimates of bits

, it is divided into fragments in which CRC is checked, fragments of the LLR bit sequence

, for which the CRC is the same, replace with the values ∞, if the specified number of iterations has not yet ended, then the sequence of LLR bits M _to mix, form a sequence of LLR bits

, which are detected, form a sequence of preliminary estimates of bits

, it is divided into fragments in which CRC is checked, fragments of the LLR bit sequence

, for which the CRC matches, are replaced by the values ∞, the sequence of LLR bits

is a priori information for the SISO equalizer.

The proposed method for iterative signal processing for a serial modem is as follows.

, которая перемешивается по определенному закону, формируется последовательность бит

. Последовательность бит

разбивается на фрагменты, к каждому из которых добавляется CRC код, формируется последовательность бит

. Последовательность бит

модулируется, формируется выходная последовательность комплексных чисел x_n, соответствующих точкам в сигнальном созвездии (символам).In the transmitting part of the communication system, the initial sequence of bits s _k (input information) is encoded by an error-correcting code, a sequence of bits is formed

, which is mixed according to a certain law, a sequence of bits is formed

. Bit sequence

broken into fragments, to each of which a CRC code is added, a sequence of bits is formed

. Bit sequence

modulated, the output sequence of complex numbers x _n corresponding to the points in the signal constellation (symbols) is formed.

(на первой итерации равны нулю), формируется последовательность LLR бит

. Последовательность LLR бит

детектируется, формируется последовательность предварительных оценок бит

. Она разбивается на фрагменты, в которых проверяется CRC. Фрагменты последовательности LLR бит

(

за вычетом LLR, соответствующих битам CRC), для которых CRC совпала, заменяются значениями ∞ (LLR для известных бит). Последовательность LLR бит

деперемешивается, формируется последовательность LLR бит

, которая декодируется. Формируется последовательность LLR бит Мк. Если заданное количество итераций еще не закончилось, последовательность LLR бит М_к перемешивается, формируется последовательность LLR бит

(с вновь добавленными LLR, соответствующими битам CRC кода). Последовательность LLR бит

детектируется, формируется последовательность предварительных оценок бит

, она разбивается на фрагменты, в которых проверяется CRC. Фрагменты последовательности LLR бит

, для которых CRC совпала, заменяются значениями ∞ (LLR для известных бит). Последовательность

является априорной информацией для SISO эквалайзера. Если заданное количество итераций закончилось, полученная после декодирования последовательность LLR бит М_к детектируется, формируется последовательность окончательных оценок принятых информационных бит

, являющаяся выходной.In the receiving part of the communication system, the signal y (t) received from the communication channel (input information) is demodulated, a sequence of complex numbers at _n corresponding to the points in the signal constellation (received symbols) is formed. Then the demodulated signal at _n is equalized taking into account a priori LLR bits

(equal to zero at the first iteration), a sequence of LLR bits is formed

. LLR bit sequence

detected, formed a sequence of preliminary estimates of bits

. It is broken down into fragments in which CRC is checked. Fragments of the LLR bit sequence

(

minus LLRs corresponding to CRC bits), for which the CRC matches, are replaced by ∞ (LLR for known bits). LLR bit sequence

de-shuffled, a sequence of LLR bits is formed

which is decoded. An LLR bit MK sequence is formed. If the specified number of iterations has not yet ended, the LLR bit sequence M _{to is} mixed, the LLR bit sequence is formed

(with newly added LLRs corresponding to CRC code bits). LLR bit sequence

detected, formed a sequence of preliminary estimates of bits

, it is broken down into fragments in which CRC is checked. Fragments of the LLR bit sequence

, for which the CRC matches, are replaced by ∞ (LLR for known bits). Sequence

is a priori information for the SISO equalizer. If a predetermined number of iterations has ended, the sequence obtained after decoding LLR bits M _to be detected, is formed by a sequence of final estimates the received information bits

being a day off.

Thus, the proposed method (second option) allows you to evaluate the accuracy of the received information in the process of turboequalization, increasing the speed of its processing and improving the characteristics of the quality of communication. At the same time, the independence of information processing levels is maintained.

The closest in technical essence to the proposed device (second option) is the device described in article [5], adopted as a prototype.

The prototype device consists of two parts: transmitting and receiving, its block diagram is shown in figa, b.

A block diagram of the transmitting part of the prototype device is shown in figa, where it is indicated:

2 - encoder;

3 - interleaver;

4 - modulator;

s _k is the initial sequence of bits;

- закодированная последовательность бит;

- encoded sequence of bits;

- перемешанная последовательность бит;

- mixed sequence of bits;

x _n is a sequence of complex numbers corresponding to points in the signal constellation (symbols).

The transmitting part of the prototype device contains a series-connected encoder 2, an interleaver 3 and a modulator 4, the output of which is the output of the transmitting part of the prototype device, the input of which is the input of the encoder 2.

The transmitting part of the prototype device works as follows.

, которая поступает на перемежитель 3, где происходит ее перемешивание по определенному закону. Перемешанная последовательность бит

поступает на модулятор 4, формирующий последовательность символов в виде комплексных чисел x_n, соответствующих точкам в выбранном сигнальном созвездии (символам). В дальнейшем эта последовательность символов преобразуется передающей аппаратурой в сигнал, передаваемый по какому-либо каналу связи с МСИ, например по KB каналу с многолучевым распространением.At the input of the transmitting part of the device receives a sequence of bits s _k from any source of information. Encoder 2 encodes this sequence with an error-correcting code, resulting in a new bit sequence

, which enters the interleaver 3, where it is mixed according to a certain law. Mixed bit sequence

arrives at modulator 4, forming a sequence of characters in the form of complex numbers x _n corresponding to the points in the selected signal constellation (characters). In the future, this sequence of characters is converted by the transmitting equipment into a signal transmitted via any communication channel with the ISI, for example, on a KB channel with multipath propagation.

The block diagram of the receiving part of the prototype device is presented in figb, where it is indicated:

3 - interleaver;

5 - matched demodulator filter;

6 - SISO equalizer;

7 - deinterleaver;

8 - SISO decoder;

9 - switch;

10 - detector;

y (t) is the signal received from the communication channel;

y _n is a sequence of complex numbers at the output of the demodulator;

- последовательность LLR бит на выходе SISO эквалайзера;

- LLR bit sequence at the output of the SISO equalizer;

- то же после деперемежителя;

- the same after de-interleaver;

M _to - the same after the SISO decoder;

- то же после перемежителя;

- the same after the interleaver;

- последовательность окончательных оценок принятых информационных бит.

- a sequence of final evaluations of the received information bits.

The receiving part of the prototype device contains a matched filter of the demodulator 5, SISO equalizer 6, deinterleaver 7 and SISO decoder 8, the output of which is connected to the input of the switch 9, the first output of which is connected to the input of the detector 10, the output of which is the output of the receiving part. The second output of the switch 9 through the interleaver 3 is connected to the second input of the SISO equalizer 6. The input of the matched filter demodulator 5 is the input of the receiving part.

The receiving part of the prototype device works as follows.

. Деперемежитель 7 восстанавливает исходный порядок следования LLR бит

, соответствующий исходной закодированной последовательности бит

. SISO декодер 8 декодирует последовательность LLR бит

, формируя на своем выходе новую последовательность LLR бит М_к, более правдоподобную, благодаря исправляющим свойствам используемого помехоустойчивого кода. Последовательность LLR бит М_к через переключатель 9 подается на перемежитель 3, который формирует перемешанную последовательность LLR бит

, которая подается на второй вход SISO эквалайзера 6 в качестве априорных LLR бит. SISO эквалайзер 6 вновь формирует (уже уточненные) LLR бит

и т.д. Данная итеративная процедура (турбоэквалайзинг) повторяется заданное количество раз, после чего переключатель 9 переводится в другое положение, и выход SISO декодера 8 подается на детектор 10, который формирует последовательность окончательных оценок принятых информационных бит

, которая затем передается в какой-либо приемник информации, например на уровень канального протокола.The signal y (t) received from the communication channel, distorted by the MSI, is mixed with noise and fed to the matched filter of demodulator 5, where it is converted into a sequence of input samples in the form of complex numbers y _n . Then SISO equalizer 6 forms an LLR bit sequence from them

. The deinterleaver 7 restores the original order of LLR bits

corresponding to the original encoded bit sequence

. SISO decoder 8 decodes LLR bit sequence

, forming at its output a new sequence of LLR bit M _k , more believable, due to the correcting properties of the error-correcting code used. The sequence of LLR bits M _to through the switch 9 is fed to the interleaver 3, which forms a mixed sequence of LLR bits

which is applied to the second input of the SISO equalizer 6 as a priori LLR bits. SISO Equalizer 6 re-generates (already specified) LLR bits

etc. This iterative procedure (turbo equalization) is repeated a predetermined number of times, after which the switch 9 is moved to another position, and the output of the SISO decoder 8 is supplied to the detector 10, which forms a sequence of final estimates of the received information bits

, which is then transmitted to some information receiver, for example, to the channel protocol layer.

The disadvantage of the prototype device is the inability to assess the reliability of the received information, as well as speeding up its processing, if this reliability is high.

To eliminate this drawback, an iterative signal processing device for a serial modem, consisting of a transmitting and receiving part, the transmitting part contains a serially connected encoder, an interleaver, and also a modulator, the output of which is the output of the transmitting part, and its input is the input of the encoder, the receiving part is serially connected matched demodulator filter and SISO equalizer, serially connected deinterleaver, SISO decoder and first switch, the first output of which is connected to the input of the first detector, the second output of the first switch is connected to the input of the interleaver, and the input of the matched filter of the demodulator is the input of the receiving part, and its output is the output of the first detector, according to the invention, is introduced into the transmitting part - the CRC add-on unit, the output of which is connected to the input of the modulator, and the interleaver output is connected to the input of the CRC add-on unit, to the receiving part are the second and third detectors, the first and second CRC test blocks, the second and third switches, and the SISO output of the equalizer is the third detector and the first CRC test unit are connected to the first input of the second switch, the second input of which is the input for LLR values of known bits, the output is connected to the input of the deinterleaver, and the third input of the second switch is connected to the SISO output of the equalizer, the interleaver output is connected through the second the detector and the second CRC check unit are connected to the first input of the third switch, the second input of which is the input for LLR values of the known bits, and the output is connected to the second input of SISO eq Alizer, the interleaver output is connected to the third input of the third switch.

The proposed device consists of two parts: transmitting and receiving, its block diagram is shown in figa, b.

A block diagram of the transmitting part of the proposed device is presented in figa, where it is indicated:

1 - block add CRC;

2 - 4 - as in the prototype diagram;

- последовательность закодированных и перемешанных бит с добавлением CRC;

- a sequence of encoded and mixed bits with the addition of CRC;

other sequences and signals - as in the prototype diagram.

The transmitting part of the proposed device contains a series-connected encoder 2, an interleaver 3, an addition unit CRC 1 and a modulator 4, the output of which is the output of the transmitting part, and its input is the input of the encoder 2.

The transmitting part of the proposed device works similarly to the prototype, with the exception of one point.

поступает на блок добавления CRC 1, который делит ее на фрагменты, добавляя к ним CRC. Полученная при этом последовательность бит

поступает на модулятор 4, формирующий последовательность символов в виде комплексных чисел x_n, соответствующих точкам в выбранном сигнальном созвездии.Interleaved 3 bit sequence

arrives at the block adding CRC 1, which divides it into fragments, adding CRC to them. The resulting bit sequence

arrives at modulator 4, forming a sequence of characters in the form of complex numbers x _n corresponding to points in the selected signal constellation.

The block diagram of the receiving part of the proposed device is presented in figb, where it is indicated:

3,5 - 8 - as in the prototype diagram;

9.1, 9.2, 9.3 - the first, second and third switches;

10.1, 10.2, 10.3 - the first, second and third detectors;

11.1, 11.2 - the first and second blocks of the CRC check;

- последовательность LLR бит на выходе SISO эквалайзера;

- LLR bit sequence at the output of the SISO equalizer;

- то же, за вычетом LLR, соответствующих битам CRC;

- the same, minus the LLR corresponding to the CRC bits;

- то же, после SISO декодера и перемежителя;

- the same after the SISO decoder and interleaver;

- последовательность предварительных оценок бит;

- a sequence of preliminary estimates of bits;

other sequences and signals - as in the prototype diagram.

The receiving part of the proposed device contains a serially connected matched filter of the demodulator 5, SISO equalizer 6, a third detector 10.3, a first CRC verification unit 11.1, the output of which is connected to the first input of the second switch 9.2, the output of which through a series-connected deinterleaver 7 and SISO decoder 8 is connected to the input the first switch 9.1, the first output of which is connected to the input of the first detector 10.1, the output of which is the output of the receiving part. The second output of the first switch 9.1 through a series-connected interleaver 3, the second detector 10.2 and the second CRC verification unit 11.2 is connected to the first input of the third switch 9.3, the output of which is connected to the second input of the SISO equalizer 6, the output of which is connected to the third input of the second switch 9.2, the second input which is the input for the LLR values of the known bits. The output of the interleaver 3 is connected to the third input of the third switch 9.3, the second input of which is an input for LLR values of known bits. The input of the matched filter demodulator 5 is the input of the receiving part of the proposed device.

The receiving part of the proposed device works similarly to the prototype, with the exception of two points.

, которая поступает на вход третьего детектора 10.3, где преобразуется в последовательность предварительных оценок бит

. Первый блок проверки CRC 11.1 проверяет CRC отдельных порций бит (фрагментов) и, если CRC не совпала (т.е. фрагмент принят с ошибками), передает через второй переключатель 9.2 на деперемежитель 7 последовательность LLR бит

(

за вычетом LLR, соответствующих битам CRC, т.е. в точности, как в прототипе). Если же CRC совпала, то на деперемежитель 7 подаются LLR, соответствующие известным битам информации, т.е. ∞, что существенно повысит качество декодирования остальных бит на текущей итерации турбоэквалайзера. Во-вторых, последовательность LLR бит

, сформированная в перемежителе 3, подается на вход второго детектора 10.2, где преобразуется в последовательность предварительных оценок бит

. Второй блок проверки CRC 11.2 проверяет CRC отдельных порций бит (фрагментов) и, если CRC не совпала (т.е. фрагмент принят с ошибками), передает через переключатель 9.3 на SISO эквалайзер 6 последовательность LLR бит

. Если же CRC совпала, то на SISO эквалайзер 6 подаются LLR, соответствующие известным битам информации, т.е. ∞, что также повысит качество декодирования остальных бит на следующей итерации турбоэквалайзера. SISO эквалайзер 6 вновь формирует (уже уточненные) LLR

для каждого бита и т.д. В случае, если на какой-либо итерации турбоэквалайзера все биты окажутся декодированы правильно, итерации можно прекратить досрочно и перевести первый переключатель 9.1 в соответствующее положение. Очевидно, что для фрагментов информации, для которых данная итеративная процедура не была завершена досрочно, CRC не совпала. Это значит, что они будут приняты с ошибками, либо, при наличии протокола верхнего уровня (со своим CRC), - перезапрошены.First, SISO Equalizer 6 forms a sequence of LLR bits from complex numbers of _n

, which is fed to the input of the third detector 10.3, where it is converted into a sequence of preliminary estimates of bits

. The first CRC verification block 11.1 checks the CRC of individual portions of bits (fragments) and, if the CRC does not match (i.e., the fragment was received with errors), transfers the sequence of LLR bits through the second switch 9.2 to deinterleaver 7

(

minus LLRs corresponding to CRC bits, i.e. exactly as in the prototype). If the CRC is the same, then LLRs corresponding to the known information bits, i.e. ∞, which will significantly increase the quality of decoding the remaining bits at the current iteration of the turbo equalizer. Second, the LLR bit sequence

, formed in the interleaver 3, is fed to the input of the second detector 10.2, where it is converted into a sequence of preliminary estimates of bits

. The second CRC verification block 11.2 checks the CRC of individual portions of bits (fragments) and, if the CRC does not match (i.e., the fragment was received with errors), transfers the LLR bit sequence through switch 9.3 to SISO equalizer 6

. If the CRC is the same, then LLRs corresponding to the known information bits are fed to SISO equalizer 6, i.e. ∞, which will also improve the decoding quality of the remaining bits at the next iteration of the turbo equalizer. SISO Equalizer 6 re-forms (already specified) LLR

for each bit, etc. If at any iteration of the turbo equalizer all the bits are decoded correctly, iterations can be terminated early and the first switch 9.1 can be moved to the corresponding position. Obviously, for pieces of information for which this iterative procedure was not completed ahead of schedule, the CRC did not match. This means that they will be accepted with errors, or, in the presence of a top-level protocol (with its CRC), will be re-requested.

Thus, the proposed device (second option) allows you to evaluate the accuracy of the received information in the process of turboequalizing, increasing the speed of its processing and improving the characteristics of the quality of communication. At the same time, the independence of information processing levels is maintained.

It should be borne in mind that the CRC code used in the first version of the proposed technical solution is part of the channel protocol of the upper level, while the CRC code used in the second version of the proposed technical solution is an additional (new) signal processing unit at the noise-immunity code level and not related to the channel protocol.

Thus, the proposed technical solution (second option) can also be used with a channel protocol that includes its own CRC code. In this case, CRC codes of two different levels will act in parallel and independently.

The proposed method and device increase the likelihood of correct reception of information, improving the noise immunity of communication equipment, and also reduce the processing time of the signal by the turbo equalizer of the serial modem by reducing the number of iterations, thereby reducing the required amount of computing resources.

The first version of the proposed technical solution is more preferable from the point of view of compatibility with the communication equipment currently in operation.

The second option is more preferable in terms of the degree of improvement in the quality of communication and maintaining the independence of the levels of information processing.

Information sources

1. Douillard, C, Jézéquel, M., Verrou, C, Picart, A., Didier, P. and Glavieux, A .: 1995, Iterative correction of intersymbol interference: Turbo-equalization, Eur. Trans. Telecommunications 6 (5), 507-511.

2. Glavieux, A., Laot, C. and Labat, J .: 1997, Turbo equalization over a frequency selective channel, Proc. Int. Symp on Turbo Codes & Related Topics, ENST Bretagne, Brest, France, pp. 96-102.

3. Nieto, J.W .: 2005, Iterative equalization and decoding of STANAG 4539 9600 bps HF waveforms.

4. Otnes, R. and Tüchler, M .: 2001, Block SISO linear equalizers for turbo equalization in serial-tone HF modems.

5. Tüchler, M., Koetter, R. and Singer, A. C: 2002, Turbo equalization: Principles and new results, IEEE Trans. Communications 50 (5), 754-767.

Claims (4)

1. A method of iterative signal processing for a serial modem, which consists in the fact that in the transmitting part of the communication system, the initial sequence of bits s _{k is} divided into fragments, each of which is added with a CRC code, a sequence of bits is formed

, which is encoded by an error-correcting code, a sequence of bits is formed

, which is mixed according to a certain law, a sequence of bits is formed

Which modulated generated output sequence of complex numbers x _n, corresponding to the points in the signal constellation in the receiver portion of the communication system received from the channel signal y (t) demodulated, forming a sequence of complex numbers y _n, corresponding to the points in the signal constellation, then the demodulated signal y _n is equalized with a priori LLR bits

which are equal to zero at the first iteration, an LLR bit sequence is formed

which is de-mixed, an LLR bit sequence is formed

which is decoded, an LLR bit sequence is formed

if the specified number of iterations has not yet ended, then the sequence of LLR bits

shuffled, a sequence of LLR bits is formed

, which is a priori information for the SISO equalizer, characterized in that the LLR bit sequence is detected in the receiving part

form a sequence of preliminary estimates of bits

fragment into a sequence of preliminary estimates of bits

in which the CRC is checked, fragments of the LLR bit sequence

for which the CRC is the same, replace with the values ∞, detect the sequence of LLR bits

form a sequence of preliminary estimates of bits

, then it is divided into fragments in which the CRC is checked, a sequence of bit estimates is formed

, fragments of the LLR bit sequence

, for which the CRC is the same, is replaced by the values ∞, after the end of the specified number of iterations, the sequence of bit estimates obtained after the CRC check

becomes output, and thanks to the CRC code, fragments received with errors are detected. 2. An iterative signal processing device for a serial modem, consisting of a transmitting and receiving part, wherein: the transmitting part contains serially connected CRC adding unit, an encoder, an interleaver and a modulator, the output of which is the output of the transmitting part, and its input is the input of the CRC adding unit , the receiving part contains a serially connected matched demodulator filter, SISO equalizer and deinterleaver, as well as a SISO decoder, the output of which is connected to the first input of the first switch, the output of which through the interleaver is connected to the second input of the SISO equalizer, the first detector and the first CRC checker are connected in series, the input of the matched filter of the demodulator is the input of the receiving part, characterized in that the second detector and the second CRC checker are connected in series to the receiving part, as well as the second and the third switch, and the output of the second CRC check block is connected to the first input of the second switch, the second input of which is an input for LLR values of known bits, and the output is connected to the input SISO decoder, the second input of the first switch is an input for LLR values of known bits, in addition, the deinterleaver output is connected to the third input of the second switch, the SISO decoder output is connected to the input of the first detector, the first output of the first CRC check unit is connected to the input of the third switch, the output of which is the output of the receiving part of the device, the second output of the first CRC check unit is connected to the third input of the first switch, the output of the deinterleaver is connected to the input of the second detector. 3. The method of iterative signal processing for the serial modem, comprising the steps that a portion of a communication system transmitting original bit sequence encoded error correcting code generated bit sequence s' _k, which is stirred by a certain law, forming the bit sequence

, in the receiving part of the communication system, the signal y (t) received from the communication channel is demodulated, a sequence of complex numbers y _n corresponding to the points in the signal constellation is formed, LLR bit sequence

de-shuffled, a sequence of LLR bits is formed

which is decoded, the LLR bit M _k sequence is formed, if the specified number of iterations has ended, the LLR bit M _k obtained after decoding is detected, a sequence of final bit estimates is formed

, which is the output, characterized in that in the transmitting part a sequence of bits

broken into fragments, to each of which add a CRC code, form a sequence of bits

, which is modulated, the output sequence of complex numbers x _n corresponding to the points in the signal constellation is formed, in the receiving part, the demodulated signal y _n is equalized taking into account a priori LLR bits

, which are equal to zero at the first iteration, form a sequence of LLR bits

detect LLR bit sequence

form a sequence of preliminary estimates of bits

, it is divided into fragments in which CRC is checked, fragments of the LLR bit sequence

, for which the CRC is the same, replace with the values ∞, if the specified number of iterations has not yet ended, then the LLR bit sequence M _{k is} mixed, the LLR bit sequence is formed

, which are detected, form a sequence of preliminary estimates of bits

, it is divided into fragments in which CRC is checked, fragments of the LLR bit sequence

, for which the CRC matches, are replaced by the values ∞, the sequence of LLR bits

is a priori information for the SISO equalizer. 4. An iterative signal processing device for a serial modem, consisting of a transmitting and receiving part, wherein: the transmitting part contains a serial encoder, an interleaver, and also a modulator, the output of which is the output of the transmitting part, and its input is the input of the encoder, the receiving part is serially connected matched demodulator filter and SISO equalizer, serially connected deinterleaver, SISO decoder and first switch, the first output of which is connected to the input of the first detector, w The output of the first switch is connected to the input of the interleaver, the input of the matched filter of the demodulator being the input of the receiving part, and its output being the output of the first detector, characterized in that they are inserted into the transmitting part - the CRC add-on unit, the output of which is connected to the modulator input, and the interleaver output connected to the input of the CRC add-on block, to the receiving part - the second and third detectors, the first and second CRC check blocks, the second and third switches, and the SISO equalizer output through the third the tector and the first CRC checker are connected to the first input of the second switch, the second input of which is the input for LLR values of known bits, the output is connected to the input of the deinterleaver, and the third input of the second switch is connected to the SISO output of the equalizer, the interleaver output is connected through the second detector and the second a CRC checker is connected to the first input of the third switch, the second input of which is an input for LLR values of known bits, and the output is connected to the second input of the SISO equalizer, the interleaver output connected to the third input of the third switch.

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