RU2348993C1 - Digitiser of signals with nonuniform architecture of file of sample - Google Patents

Abstract

FIELD: physics, radio.

SUBSTANCE: invention concerns electronics for measuring of performances of high-speed signals which are applied in digital registrars of high-speed processes and radar-tracking receivers. The digitiser of signals (SD) with the nonuniform architecture of a file of sample contains joined parallelly with a line of an input signal sample and storage amplifiers (SHA), a set of the integrators joined to SHA outputs, a set of analog-to-digital converters (ADC), the integrators joined to exits and the generator of an adjustable delay executed with possibility of maintenance of functioning each SHA, the integrator and ADC in corresponding time intervals. For productivity increase in SD the generator of an adjustable delay, contains the block of definition of number of the cycles, executed with possibility of definition of number of cycles of integration in each point of a temporary scale of an input signal depending on a standing of a handled point of a signal on a temporary scale.

EFFECT: productivity increase.

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Description

The invention relates to the field of electronics, in particular to digital signal converters with a heterogeneous sample array architecture used to measure the characteristics of high-speed signals, which are used in digital recorders of fast processes and radar receivers.

To register a high-speed signal, digital converters are widely used on the basis of sample-and-hold amplifiers (SHA), SHA output signal integrator, programmable delayed pulse generator, analog-to-digital converter (ADC - analog-to-digital converter ) and an interface for transferring data to a computer or microcontroller. In this architecture, the SHA output integrator is needed to increase the signal-to-noise ratio. To increase this ratio, it is necessary to periodically repeat the input signal and integrate the SHA output signal, which reduces the system throughput in proportion to the number of repeating cycles.

Currently, digital converters are widely used (Figs. 1-3) based on the SHA sampling and storage amplifier 1, which, in addition, contain an SHA output signal integrator 2, a programmable delay generator 3, and an analog to digital converter 4 - ADC and personal computer interface.

A well-known digital signal converter (see. Meleshko EA. Nanosecond electronics in experimental physics. - M.: Energoatomizdat, 1987, p. 174 [1]), in which they use one SHA, an integrator and a delay generator, operating over the entire length of the signal (Figure 1). For the operation of this device, it is important that the fixed signal is repeated N times, where N is the number of samples (ticks) of the signal.

Another design of the digital converter is also known (see Meleshko EA. Nanosecond electronics in experimental physics. - M.: Energoatomizdat, 1987, p. 174 [2]) with several (K) SHA and delay generators operating at separate time intervals . For the functioning of this converter, it is important that the input signal is repeated N / K times, where N is the number of signal samples, and K is the number SHA (Figure 2). Such a design provides an increase in productivity by a factor of K compared with [1]. In this design, the number of integration cycles is fixed for all points of the timeline, which is redundant.

Closest to the claimed invention is a digital converter described in US patent No. 5,519,342 [3]), in which the number of SHA and integrators corresponds to the number of digitization points. This Converter is selected as a prototype of the claimed invention. It is made with the possibility of registering the shape of even a single pulse. The disadvantage of the prototype can be attributed to the fact that in the case of a large number of digitization points, it requires the presence of a separate SHA and generator for each point, therefore this solution (Figure 3) requires very high manufacturing costs.

In all the analogues and prototype of the claimed invention described above, the SHA output signal integrator is designed to increase the signal-to-noise ratio. To increase this ratio, it is necessary to periodically and repeatedly repeat the input signal in them, which entails a decrease in system performance.

The objective of the claimed invention is the creation of a digital signal converter with a heterogeneous architecture of the sample array, which would have increased performance and lower cost.

In general, the number of samples and integrations in the claimed digital converter varies over the time interval according to a certain rule, for example, according to the quadratic law to compensate for the decrease in the signal due to spherical divergence, according to the exponential law for signals propagating in absorption media, and so on .

The problem is solved by creating a digital signal converter with a heterogeneous architecture of the sample array, which contains sample and storage amplifiers connected in parallel with the input signal line, a set of integrators connected to the outputs of the sample and storage amplifiers, a set of analog-to-digital converters connected to the outputs of the integrators, and adjustable delay generator, configured to ensure the operation of each SHA, integrator and ADC at appropriate time intervals, in which The rum adjustable delay generator contains a block for determining the number of cycles, configured to determine the number of integration cycles at each point in the time scale of the input signal, depending on the position of the processed signal point on the time scale.

In other words, the problem is solved by creating in the generator an adjustable delay a block for determining the number of cycles, made with the possibility of more efficient integration of the output signal SHA based on the difference in the signal-to-noise level in the intervals of the full time scale of the signal. Signals received during the initial time interval, i.e. relatively short time, correspond to small ranges, i.e. distances to the target, and, accordingly, a high signal level, therefore, in the initial time interval there is no need for a large number of integration cycles. Therefore, the SHA operating in a given time interval can process more points during the same number of cycles performed than the SHA operating in time intervals corresponding to large ranges (Figure 4). Thus, in the unit for determining the number of cycles of the claimed digital converter, in order to obtain the required signal-to-noise ratio, the required number of integration cycles is provided only for the end of the timeline; for other time intervals, the number of cycles is reduced with an increase in the processed time interval.

The technical result of the claimed invention is to increase productivity and reduce the cost of a digital converter.

For a better understanding of the claimed invention the following is a detailed description with the corresponding drawings.

Figure 1 - Scheme and timing diagram of the digital converter analogue [1] of the claimed invention in the strobe mode, in which the SHA sequentially samples the signal from one point in the timeline to another, the time position is changed by a delay generator, and the full cycle of the digital signal conversion contains N input signal periods.

Figure 2 - Diagram and timing diagram of the operation of a digital converter analogue [2] of the claimed invention using several SHA and delay generators operating in separate time intervals.

Figure 3 - Scheme and timing diagram of the digital Converter of the prototype [3] of the claimed invention with a large number of SHA and integrators, corresponding to the number of points on the timeline.

Figure 4 - Diagram and timing diagram of the operation of the digital Converter made according to the invention.

As shown in FIG. 3, the signal-to-noise ratio varies in different time intervals, for example, in a radar system, the signals are usually weaker the later they arrived, and vice versa.

The claimed digital Converter contains a set of 1 SHA, a set of 2 integrators, an adjustable delay generator 3, ADC 4 and a unit 6 for determining the number of cycles built into the adjustable delay generator 3. Moreover, SHA set 1 (Figure 4), connected to the input signal line, integrators 2, connected to the outputs of set 1 SHA, ADC 4 connected to the outputs of integrators, adjustable delay generator 3, ensures the operation of each SHA, integrator and ADC in the corresponding time interval . Block 6 determining the number of cycles is made with the possibility of determining the number of integration cycles at each point in the time scale of the input signal depending on the position of the processed signal point on the time scale.

Thus, to increase the signal-to-noise ratio, integration of the SHA output signal is used for several cycles of the input signal, while all SHAs and integrators function in each cycle of the input signal, but within the time interval corresponding to the worst signal-to-noise ratio moreover, several cycles of the input signal must be repeated at each point in the timeline, and the output signal SHA must be integrated to increase the signal-to-noise ratio. For example, in FIG. 4, in the last time interval, six cycles of the input signal must be integrated to obtain the desired signal-to-noise ratio. This time interval contains four time points, so the total number of cycles of the input signal is 6 × 4 = 24. At the same time, the previous time interval, which has the best signal-to-noise ratio, requires fewer integration cycles of the input signal. As shown in FIG. 4, this number is three, and within twenty-four cycles of the input signal, the corresponding SHA can process eight points on the timeline. The first time interval has an even higher signal-to-noise ratio; it requires fewer integration cycles of the input signal. As shown in FIG. 4, this number is two, and within twenty-four cycles of the input signal, the corresponding SHA must process twelve points on the timeline. In this case, the total number of cycles of the input signal is twenty-four, and the total number of points on the timeline is also twenty-four. If the integration of six cycles of the input signal is applied to all points of the timeline, the total required number of cycles of the input signal will be forty-eight. Thus, we have a twofold advantage over a circuit using a constant number of integration cycles. In the case of a radar scanner, this means a twofold increase in scanner performance.

The claimed digital signal converter with a heterogeneous architecture of the sample array can be used to sample and process fast electrical signals in particular in UWB radar systems, radar scanners, and local positioning systems.

Although the above embodiment of the invention has been set forth to illustrate the present invention, it is clear to those skilled in the art that various modifications, additions and substitutions are possible without departing from the scope and meaning of the present invention disclosed in the attached claims.

Claims (1)

A digital signal converter with a heterogeneous architecture of the sample array, comprising sampling and storage amplifiers connected in parallel with the input signal line, a set of integrators connected to the outputs of the sampling and storage amplifiers, a set of analog-to-digital converters connected to the outputs of the integrators and an adjustable delay generator, configured to ensure the functioning of each SHA, integrator and ADC at appropriate time intervals, characterized in that the adjustable delay generator with determination unit holds the number of cycles, capable of determining the number of cycles of integration in each point of the time scale of the input signal depending on the position of the processed signal point on the timeline.

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