RU2344543C1 - Device for reception and synchronization of coded signal - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: device receives any two-level or three-level differential coded signal of sequential binary self-synchronizing code (SBSC) with transformation into two-digit asynchronous coded signal IX(1:0) and further noise-immune performance of full function of this signal synchronization with the help of input continuous sequence of clock pulses IC due to noise-immune formation of output synchronized coded signal OX(1:0), output clock signal OCX of coded signal OX(1:0) and output clock signals of beginning of pause OPC and pause OPX, and may be used as synchronous noise-immune shaper of synchronized coded signal OX(1:0) and clock signals OCX, OPC, OPX for any two-level or three-level SBSC. Result is achieved with the help of continuous sequence of input clock pulses 1C due to noise-immune formation of output synchronized coded signal OX(1:0), output clock signal OCX of coded signal OX(1:0) and output clock signals of beginning of pause OPC and pause OPX for any two-level or three-level SBSC with the help of barrage filtration of asynchronous coded signal 1X(1:0) as noise, while duration of every change of this signal does not exceed threshold duration P·Tic, where P≥1 - threshold integer number, Tic - duration of clock pulses 1C period. Device contains triggers, synchronous counter, detector-transducer, register, elements OR-NOT, delay element, element AND, elements AND-NOT, elements OR, comparators, inlets of differential coded signal, clock pulse inlet, code outlet of synchronized coded signal, outlets of clock signals of coded signal, beginning of pause and pause, code inlet of pause detection threshold and code inlet of coded signal clock signal detection threshold.

EFFECT: higher noise-immunity of device.

1 dwg

Description

The invention relates to the field of computer engineering, is intended for receiving any two-level or three-level differential encoded signal IX of a sequential binary self-synchronizing code (PDSK) with conversion to a two-bit asynchronous encoded signal IX (1: 0) and subsequent noise-tolerant performance of the full synchronization function of this signal using the input continuous IC clock sequence due to noise-resistant generation of output synchronized code The specified OX signal (1: 0), the output synchronization signal (OCX clock signal), the OX signal (1: 0) and the output clock signals of the start of the OPC pause and the OPC pause and can be used as a synchronous noise-immunity driver of the synchronized encoded OX signal (1: 0 ) and OCX, OPC, ORX clock signals for any two-level PDSK, for example, class 1В2В (Manchester according to GOST 26765.52-87, bi-pulse or Miller according to GOST 27232-87, etc.) or any three-level PDSK, for example, RZ code with return to zero according to GOST 18977-79.

Two-level codes 1B2B are widespread due to the high noise immunity and ease of conversion and separation of the bit synchronization signal [1, p. 152]. Any two-level code 1В2В is redundant and is obtained in the process of converting a two-level sequential binary code (MAC) without returning to zero so that in each bit interval T of information transmission each bit “0” (or “1”) of a two-level MAC is converted according to the corresponding algorithm into two 1B2B code bits, each of which has a T / 2 duration - see, for example, [1, p.149-153: 6.7. Digital Modulation Methods].

The three-level RZ code has also been widely used, since in modern information-measuring radio-electronic systems for exchanging information using a three-level encoded signal, it is most rational to use the RZ code, since other known MPCSs have no advantages compared to them and can sometimes be used in connection with with a lack of information from developers about the advantages and disadvantages of various coding (modulation) methods of the original two-level MPC - see, for example [2, p. 48]. It is known [3, p. 260] that a three-level code RZ, like any two-level code of class 1B2B, requires double bandwidth compared to a two-level MPC, the standard form of which is the English language abbreviation NRZ - Non Return to Zero [3, p.30 , fig. 1.15]. In this regard, to increase the exchange rate, this device can be used to receive and synchronize the encoded signal of any other two-level code or three-level code with a narrow bandwidth, for example, a high-speed three-level code (VTK) having the same bandwidth as NRZ. This VTK is self-synchronizing [3, p.260-263], since there is a level difference of the input three-level encoded signal IX at each boundary between the bits, and the logical “0” is transmitted by the minimum signal level IX or the next zero (average) signal level, and the logical “1” transmission - the maximum signal level IX or the next zero level after it.

Thus, the proposed device can be used as an interface receiving base component in the construction of various digital devices (decoders, repeaters, interface converters with time compression / decompression for matching low-frequency interfaces through one high-performance local area network - see [1, p. 83- 84: 3.8. Interface Converters]) for the exchange of information in wired communication systems using a digital differential (differential) signal

any two-level or three-level code in a complex interference environment with significant common-mode interference

distorting both components

signal IX (1), i.e. at high values of noise immunity

Where

| Z | max - the operator of extracting the maximum value of the module of magnitude Z = Xc / Xg;

IXa and IXb, respectively, the first and second components of the signal IX (1), measured relative to the common bus (housing) of the device;

Xg = | IX | min - the module of the minimum information value of signal IX (1).

It is known [2, p. 41] that practically no screening and spacing methods for digital communication wires from energy wires can guarantee the absence of interference (interference) in the communication line (LAN). This means that the useful signal IX (1) always exists together with interference, and the task is guaranteed, i.e. with a certain margin of stability, the allocation of the signal against the background of interference. Taking into account the real natural noise environment, in [2, p. 41] it is believed that the condition for the smooth operation of the equipment is an interference signal in the LAN that does not exceed | Xc | ≈10 ÷ 20 V. However, in the general case, this common-mode noise value for many applications can to be clearly underestimated [4, p. 283]. For example, a measuring amplifier with an admissible common-mode noise level of up to 50 V is known [4, p.279, Fig.7.7g]. Based on [2, p.41; 4, p. 283] we determine that for signal IX (1) of the code RZ described by relations (1) - (5), to calculate K (5), the value | Xc | max should be chosen from the condition

In the RZ code according to GOST 18977-79 and RTM 1495-75 (see, for example, [5, p. 57-63]) each bit is transmitted by signal IX (1) during the bit period T = T1 + T2 so that in information half-period T1 = T / 2 of period T at the inputs of the receiver-converter, the signal value (1) is determined by the relations

and during the half-period T2 = T / 2 return to zero or during a pause

the value of signal (1) is determined by the relation IX = (0 ± 1) B, where T is the period of bit synchronization of information transmission by signal (1) of the RZ code.

Based on (5) - (8), the indicator K (5) is estimated by

In the process of entering information, the digital differential signal IX (1) is initially uniquely converted by the receiver-converter into a digital signal, which in direct code IX (1: 0) = | X1 | X0 means the following:

a pause in any 1V2V and a return to zero level or a pause in the RZ or VTK code,

Reception of a binary “0” bit in any DPSK,

Reception of binary “1” bit in any DPSK,

a forbidden combination in any DPSK, but possible, except for the RZ code, as transitional for approximately the period of the IC clock pulses due to the hysteresis characteristic of the signal receiver-converter IX (1) when switching from reception (12) or (13) to reception ( 13) or (12).

Next, the signal IX (1: 0) is input into a digital system (asynchronous or synchronous automaton with memory), which usually operates on a continuous sequence of clock pulses IC of a single system clock generator, with respect to the frequency of which the signal IX (1: 0) is asynchronous and distorted by interference. In the general case, it should also be taken into account [6] that in the proposed device (like any microelectronic device), communication channels for signal transmission can be distinguished, each of which contains a signal source, a LAN, and a signal receiver. Any communication channel can be either a source or a receiver of interference. In real conditions, several sources of external industrial or natural interference and internal interference with various types of spurious connections can influence communication channels: capacitive, inductive, resistive, complex.

Thus, the synchronized encoded signal IX (1: 0) is masked by noise, and in the general case, the task of its full synchronization should be solved taking into account possible distortion by various noise, in particular, phase noise - jitter (jitter - jitter) and wander (wander - wandering), caused, for example, by crosstalk from other drugs, ripple of the supply voltage of the transmitter and signal converter IX (1), unfavorable code combinations during signal formation IX (1) by a linear transmitter, day-night and temperature differences (Vander ELF) - see, for example, [7, p.103]..

In the process of inputting information using IC clock pulses, the full function of clock synchronization of signal IX (1: 0) of any PDSK, which consists in the noise-immune generation of the synchronized signal OX (1: 0) for receiving the encoded signal (1) and the output synchronization signals OCX receiving the OX code (1: 0), the start of the OPC pause, and the OPC pause. It should be noted [8; 9, p.251, p.252] that during the input of information, for example, in any 1B2B code, the correct synchronization of the synchronized signal IX (1: 0), using the input clock pulses IC, with respect to which this signal is asynchronous, is possible when determining the frequency 1 / Tic clock pulses IC based on the condition

when choosing K≥4, taking into account the speed of the element base of the device and the real tolerances on the jitter of signal IX (1: 0),

Where

Ti - variable period of undistorted synchronized signal IX (1: 0) within certain limits;

T1i and T2i are the duration of the zero and first phases of the synchronized signal IX (1: 0) with IX (1: 0) = 01 and IX (1: 0) = 10, respectively;

Tic is the duration of the period of the input clock signal IC;

T0ic and T1ic are the duration of the zero and single phases of the clock signal IC at IC = 0 and IC = 1, respectively.

It is also known [2, p. 32-35; 10] that when signal IX (1) is transmitted in a coordinated (at R = Ri) or inconsistent (at R <Ri to reduce the energy level of information exchange) form IX (1) transforming in the duration of switching from reception ( 12) (or (13)) to receive (13) (or (12)), where R and Ri are the wave impedance of the drug and the input impedance of the signal receiver-converter IXa or IXb. In practice, with the rectangular waveform of signal IX (1), even at R = Ri, for each change in signal IX (1) in the drug, there is a transient process of the duration of the TPP [10, p. 117], for example, with a length of the drug 15 m, the duration of the TPP is ≤75 ns. In this regard, to ensure the most noise-free input of information by the encoded signal IX (1), it is necessary to use a receiver-converter with a high input impedance, a small input capacitance, and preferably with a hysteretic transfer characteristic [10, p.118], and it is advisable to form the signal IX (1) trapezoidal with a front or slice duration of 174, which ensures maximum drug throughput - see [2, p. 34, Fig. 2.3. Trapezoidal pulse shape].

Taking into account (11) - (15) for the further description, the full function of the clock synchronization of the asynchronous signal IX (1: 0) is performed using the IC clock pulses, in the general case, we define it as the formation of the output synchronized digital encoded reception signal OX (1: 0) (11) or (12) or (13) of duration

when switching OX (1: 0) along the edge of the OCX output clock signal during the formation of OCX duration

at each threshold detection of the transition of the synchronized signal IX (1: 0) from any state to another state, the formation of the output clock signal of the start of the OPC pause of duration Topc = Tic with the threshold detection of the transition of the signal IX (1: 0) from the state “01” or “10” to the state “00” and after the end of the OPC clock signal, the formation of the output clock signal of the OPC pause with a duration of Torx that is a multiple of an integer number of Tic periods,

Where

Т0о or Т1о or Т2о - the duration of the return or zero or single phase of the OX signal (1: 0) with OX (1: 0) = 00 or OX (1: 0) = 01 or OX (1: 0) = 10, respectively;

k is an integer not less than "2".

Taking into account (15) - (17), the duration of each change in signal IX (1: 0) is denoted by Ti, and during synchronization, the change in signal IX (1: 0), depending on the duration of Ti, is defined as interference with

as a correct information signal when

or as a signal with an indeterminate (distorted) time parameter

which during processing can be attributed to interference (18) or to the correct signal (19),

Where

i is the decimal number “0”, “1”, “2” and “3”, respectively, defining the value “00”, “01”, “10” and “11” of signal IX (1: 0);

P is a threshold integer not less than “1”, chosen taking into account (15).

Obviously, if signal IX (1: 0) is distorted by all kinds of interference, the presence of an uncertainty interval of type (20) of duration Tic is fundamentally unavoidable, since it is caused by the asynchronous nature of any changes in signal IX (1: 0) with respect to IC clock pulses.

It should also be said that to satisfy the indicator K (5) of the device, conditions (6) and (10) at the inputs of its receiver-converter, it is advisable to install high-resistance dividers [2, p. 67, Fig. 4.13]. Obviously, this will lead to a decrease in the threshold of the receiver-converter, i.e. to reduce the noise immunity of signal formation IX (1: 0) when exposed to external and internal interference on the receiver-converter.

Based on the foregoing, it can be said that when constructing modern digital information processing and control systems and their components, the problem of accounting for interference is almost always relevant due to the presence of various external and internal interference, lowering the energy level of information signals, complicating the systems and their components and increasing the length and the number of external relations.

Thus, when entering information into a digital system, it becomes necessary to synchronize the IX (1: 0) signal of any two-level or three-level MPCS taking into account (10) - (20) and possible distortion of this signal by various noise.

It should be noted here that in an asynchronous system, synchronization (changing the state of an asynchronous automaton with memory when the input information signals are set) is performed using the corresponding clock pulses (when generating with the help of clock pulses IC, the duration of the clock pulse coincides with the duration T0ic zero at IC = 0 or the duration T1ic unit phase with IC = 1 of the period Tic = T0ic + T1ic of IC clock pulses), and synchronization in a synchronous system (state change of a synchronous automaton with memory when inputs are installed GOVERNMENTAL information signals) is carried out by logically "AND" function, ie, along the edges (transitions from “0” to “1”) or slices (transitions from “1” to “0”) of the IC clock pulses and the corresponding clock signals installed before the edge or IC cutoff arrives, and the duration of each clock signal is usually a multiple of an integer number of periods clock pulses IC.

At present, and for the long term, the main method of processing information in digital systems is the synchronous method of clocking along the edges or slices of a single clock generator using clock signals - see, for example, [11, p.121-123: 3.5. Introduction to the problems and design techniques of automata with memory].

Based on the foregoing, we can say that the creation of a device for receiving and synchronizing the encoded signal IX (1) of any two-level or three-level PDSK for inputting information into a synchronous digital system with the required characteristics and taking into account conditions like (10) and definitions (11) - (20 ) at reasonable hardware costs, it represents an urgent technical problem, the solution of which will generally improve the quality of the developed synchronous digital systems for input and processing of information, which are components of time information-measuring systems.

A device [12] is known, which is part of a technical solution [12] and contains a linear block (receiver-converter), a pulse shaper, an input of signal IX (1) of code 1В2В (in particular, Manchester), which is an input of a linear block, outputs of signals IX1 and IX0 of code IX (1: 0), which are the outputs of the linear block and connected to the first and second inputs of the pulse shaper, respectively, and the pulse output of a short pulse CXb of bit synchronization code 1B2B, which is the output of the pulse shaper containing the trigger, three I-H elements , the first input of signal IX1 connected to the information input of the trigger and the first input of the first AND-NOT element, the second input of which is connected to the inverse output of the NTX trigger signal, the direct output of the TX signal of which is connected to the first input of the second AND-NOT element with NTX =! ТХ (where “N =!” is the operator of the operation “NOT” in the ABEL language), the second input of signal IX0, which is the second input of the second AND-NOT element, and the pulse output of the pulse CXb connected to the clock input of the trigger and the output of the third AND-NOT element whose inputs are connected to the outputs of the first and second lementov AND-NOT.

The functioning of the device [12] as an asynchronous automaton with memory can be described as a sequence of its transitions from the pause state (SP)

in a single state (EU)

from the EU (22) to the zero state (NA)

from NS (23) to the EU (22) and from the EU (22) or NS (23) to the SP (21) when the trigger is reset to TX = 0 by the reset signal NR = (IX1 # IX0) = 0, where "#" - the operator of the “OR” operation in the ABEL language, and each transition of the device [12] from the joint venture (21) to the EU (22) and from the EU (22) (or NS (23)) to NS (23) (or EU (22 )) is carried out along the edge of the pulse CXb, which is generated by the pulse shaper according to the logical formula CXb = (IX1 & NTX) # (IX0 & TX), where "&" is the operator of the "AND" operation in the ABEL language. The pulse duration CXb can be estimated by the value Тсх = 3 · Тз, which is determined by the delay of the pulse front CXb through the trigger, the first (or second) AND-NOT element and the third AND-NOT element, where Тz is the average signal propagation delay through any shaper element.

In case of noise-tolerant signal formation IX (1: 0) in the EU (22) or NS (23), the trigger functions correctly and is in the state TX = IX1, and the signal CXb is formed noise-immune. If during the formation of signal IX (1: 0) a short-term interference occurs with a duration of more than Tx, consisting, for example, at TX = 0 (or 1) in the transition of signal IX (1: 0) from state “01” (or “10”) to the transition state "11", the device will generate a jamming pulse CXb.

The main disadvantage of the device [12] is the low noise immunity, since it is intended for the formation of short pulses CXb of the bit synchronization of the 1B2B code only when the noise-tolerant information signal IX (1: 0) changes the 1B2B code.

A device [8] is known, which is part of a technical solution [8] and contains a pulse generator, first and second triggers, the clock inputs of which are connected to the clock pulse output of the IC pulse generator, an exclusive-OR element, signal input IX1 of a one-bit code 1В2В (in particular, Manchester ), which is the information input of the first trigger, the output of the synchronized signal OX1 of the 1B2B code bit connected to the output of the first trigger, the information input of the second trigger and the first input of the Exclusive OR element, and the output inhrosignala synchronization bit OCXb, which is the output of the exclusive OR gate, a second input coupled to an output signal X2 of the second flip-flop.

Taking into account (15) - (20) at P = 1, depending on the values of the durations T0i at IX1 = 0 and T1i at IX1 = 1, the operation of the device [8] can be described as a sequence of transitions from zero state (NS)

or single state (EU)

in transition state (PS)

and from the PS (26) to the EU (25) or the NS (24) in the process of generating the clock synchronization signal OCXb according to the formula

where Q is a generalized sign of the transition state of the device, defined by the formula

where “$” and “#” are the operators of the operations “Exclusive OR” and “OR” in the language ABEL.

If the input signal IX1 is formed correctly according to (19) (i.e., T0i≥2 · Tic or T1i≥2 · Tic), then the device will switch from HC (24) (or EU (25)) to EU (25) (or NS (24)) is carried out regularly so that when the IX1 signal is switched to “1” (or “0”), the device switches to PS (26), and on the nearest edge of the clock signal, the first trigger switches to “1” (or “0” ), the Exclusive OR element sets the signal OCXb = 1, and along the edge of the next IC pulse, the second trigger switches to “1” (or “0”), the Exclusive OR element generates the signal OCXb = 0, and the device moves from the PS (26) to the EU (25) (silt HC (24)).

If the input signal IX1 is masked by interference (i.e., it is sometimes formed according to (18) at T0i≤Tic (or T1i≤Tic), then the device will switch from HC (24) (or EC (25)) to PS (26) and from The PS (26) back to the NS (24) (or the EU (25)) can be carried out with the formation of a jamming clock signal OCXb = 1 for 2 · Tic. In this case, when the signal IX1 is switched to “1” (or “0”), the device goes to PS (26), and if this transition falls into the clock zone of the IC signal, then the first trigger switches to “1” (or “0”) on the nearest edge of this signal, the Exclusive OR element sets the signal OCXb = 1. m signal IX1 returns to the initial state “0” (or “1”). Then, along the edge of the next pulse IC, the first trigger returns to its initial state “0” (or “1”), and the second trigger switches to “1” (or “ 0 ”), the Exclusive OR element generates the signal OCXb = 1, and along the edge of the next IC pulse, the second trigger returns to“ 0 ”(or“ 1 ”), the Exclusive OR element generates the OCXb = 0 signal, and the device returns to the initial state of the SC ( 24) (or the EU (25)).

The main disadvantage of the device [8] is low noise immunity, since it is designed to generate a synchronized signal OX1 and a clock synchronization signal OCXb only when a noise-tolerant change in signal IX1 or TX = IX1 is made according to (19), where TX is a signal generated, for example, by a shaper of a technical solution [12].

Of the known technical solutions, the closest in technical essence to the proposed device is [13], comprising a receiver-converter, a synchronous counter equipped with a clock input, an account resolution input and a recording resolution input, priority over the account resolution input, three AND elements, an element AND NOT, two NOT elements, four triggers, the pause detection threshold code input, which is the counter information input, the encoded differential signal inputs (1), which are the inputs of the receiver-transform the outputs of bits IX1 and IX0 of the encoded signal IX (1: 0) which are connected respectively to the clock inputs of the first and second triggers, the information inputs of which are connected to the logic bus “0” of the device, the input of clock pulses IC, connected to the clock inputs of the counter and the third the trigger, the output of the pause signal OPX, connected to the inverse of the counter resolution enable input and the output of the first AND element, the first input of which is connected to the output of the second AND element and the first input of the third AND element, the bit output of the clock synchronization OCXb connected to the output of the third trigger, which is NOT connected through the first element to the inputs of the installation of the first and second triggers, an inverse of the counter recording enable input and one of the inputs of the second AND element, the remaining inputs of which are connected to the outputs of the highest bits of the counter, the low-order output which is connected to the second input of the first element And and through the second element is NOT connected to the second input of the third element And, the logical input "1" connected to the reset inputs of the first and second triggers and reset inputs CA and installation of the third trigger, the information input of which is connected to the output of the AND-HE element, the first input of which is connected to the output of the first trigger and the installation input of the fourth trigger, the reset input of which is connected to the second input of the AND-NOT element and the output of the second trigger, and the signal output The OX of receiving a code bit, which is the output of the fourth trigger, and the inputs of setting and resetting all triggers of the device are inverse and asynchronous.

The functioning of the device [13] is carried out according to the input encoded signal (1), clock pulses IC and the input code Y (5: 0) of the pause detection threshold so that during operation the counter generates discharge signals of code C (5: 0) at the code output, the receiver-converter converts the encoded signal (1) into bit signals IX1, IX0 of code IX (1: 0), the output of the third trigger generates a bit synchronization signal OCXb, the output signal of the fourth trigger produces the signal OX of receiving a bit of the code, and the outputs of the first and third elements And with respectively, the clock signals of the ORX pause and the start of the OPC pause are generated in accordance with the expressions

where “!” and “&” are the operators of the operations “NOT” and “AND” in the ABEL language, respectively.

If the signals of code IX (1: 0) are formed correctly, then on each edge of signal IX1 (or IX0), the first (or second) trigger is reset and sets (or resets) the fourth trigger in OX = 1 (or OX = 0) and calls the output element AND NOT setting the asynchronous signal bit synchronization ICXb = 1. With ICXb = 1 on the next edge of IC, the third trigger is set to OCXb = 1. Based on the signal OCXb = 1, the first element DOES NOT generate a signal NOCXb = 0, which allows the edge of the IC to write to the Y code counter (5: 0) and directly installs the first and second triggers and reset the asynchronous bit synchronization signal to ICXb = 0. In this regard, with NOCXb = 0 and ICXb = 0, the code C (5: 0) = Y (5: 0) is written to the counter on the next edge of IC, and the third trigger is reset to OCXb = 0. Further, with ORX = 0 and OCXb = 0 along the edge of each IC, the counter content increases by “1” until the next ICXb = 1 and OCXb = 1, and when a pause occurs after the last output clock signal OCXb = 1 bit synchronization, the counter is in the initial state C (5: 0) = Y (5: 0) pause detection, and after the pause detection time (TOP) defined by the formula

the third element And, according to (30), generates a pause start signal OPC = 1, after which the first element And sets the pause signal OPX = 1 and stores code C (5: 0) = 111111 in the counter until device [13] generates the next OCXb = 1 .

If during the formation of the encoded signal IX (1: 0) a short-term interference appears, consisting, for example, with OCXb = 0, in the transition of the signal IX (1: 0) from state “00” to state “01” or “10”, then the device will generate a jamming output clock OCXb = 1.

The main disadvantage of the device [13] is the low noise immunity, since it is designed to generate the OCXb, OCP, and OPX clock signals and the OX signal of receiving a 1B2B code bit or RZ code only when the noise-resistant informational change of the encoded signal IX (1: 0) changes.

The present invention solves the problem of increasing the noise immunity of the device using a continuous sequence of input clock pulses IC due to the noise-immune generation of the output synchronized encoded signal OX (1: 0), the output clock signal OCX of the signal OX (1: 0) and the output clock signals of the start of the OPC pause and the OPC pause for any two-level or three-level MPCS using barrage filtering of an asynchronous encoded signal IX (1: 0) as interference with the duration of each change of this signal, not exceeding the threshold duration P · Tic taking into account (11) - (20) for P≥1.

To achieve this technical result, in a device for receiving and synchronizing an encoded signal containing three triggers, a synchronous counter equipped with a clock input, an account resolution input and an inverse recording resolution input, priority over the account resolution input, AND element, the first AND-NOT element the receiver-converter, the inputs of the differential encoded signal, which are the inputs of the receiver-converter, a clock input, a code input of the pause detection threshold, connected to the code input of the counter, and the outputs of the pause and pause clock signals, the code output of the synchronized encoded signal, the output of the encoded signal clock, a register, two OR-NOT elements, a delay element, the second, third and fourth AND-NOT elements, two OR elements, two comparators and a code the input threshold of the detection signal of the encoded signal, and the code output of the asynchronous encoded signal of the receiver-Converter is connected to the code input of the register and the first code input of the first comparator, the second the first input of which is connected to the code output of the synchronized encoded signal of the device and the code output of the register, the clock input of which is connected to the output of the clock signal of the encoded signal of the device and the direct output of the first trigger, the inverse output of which is connected to the reset input of the second trigger, the inverse output of which is connected to the first input of the first the AND-NOT element, the output of which is connected to the information input of the second trigger, the direct output of which is connected to the first input of the first OR-NOT element and the output with the pause phase of the device, the code input of the detection threshold of the encoded signal's clock signal is connected to the first code input of the second comparator, the bit inputs of the second code input of which are connected to the inputs of the second AND element, the first OR element and the bit outputs of the counter code output, the dominant asynchronous inverse reset input which is connected to the output of the second OR element, the first input of which is connected to the output of the delay element, the input of which is connected to the direct output of the third trigger and the first input of the third AND-NOT element, the output of which is connected to the counter recording permission input and the first inputs of the second OR-NOT element and the AND element, the second input of which is connected to the output of the second AND-NOT element, the counter resolution enable input and the second inputs of the first OR elements -NON and AND-NOT, the information input of the first trigger is connected to the output of the second OR-NOT element, the second input of which is connected to the output of the first comparator and the second input of the second OR element, the third input of which is connected to the output of the first OR-NOT element and the output of the clock pause signal of the device, the clock input of which is connected to the clock inputs of the counter and all the triggers, the inverse output of the third trigger is connected to the first input of the fourth AND gate, the output of which is connected to the third input of the AND element, the output of which is connected to the information input of the third trigger, and the outputs of the second comparator and the first OR element are connected respectively to the second inputs of the third and fourth AND-NOT elements, while the reset and installation inputs of all device triggers are dominant Asynchronous inverters and unused ones are connected to the logical 1 bus of the device.

The authors are not aware of technical solutions containing features equivalent to distinctive features (introducing the code output of a synchronized encoded signal, the output of the encoded signal clock, a register, two OR-NOT elements, a delay element, the second, third and fourth AND-NOT elements, two OR elements, the first and the second comparators and the code input threshold of the encoded signal clock signal) of the proposed device, which (compared with the prototype [13]) increase the noise immunity of the device using A continuous sequence of input clock pulses IC due to the noise-immune generation of the output synchronized encoded signal ОX (1: 0), the output clock signal OCX of the signal ОХ (1: 0) and the output clock signals of the beginning of the OPC pause and the OPC pause for any two-level or three-level MPCS (for example, a two-level MPC class 1B2B or three-level RZ or VTK) using barrage filtering of an asynchronous encoded signal IX (1: 0) as interference with the duration of any change in this signal not exceeding the threshold duration lnosti P · Tic for R≥1.

The drawing shows an electrical functional diagram of a device for receiving and synchronizing an encoded signal containing triggers from the first 1 to the third 3, a synchronous counter 4, equipped with a code input and code output, a clock input, a dominant asynchronous inverse reset input, a direct input to enable counting and an inverse input write permission, priority over the account resolution input, receiver-converter 5, register 6, first 7 and second 8 elements OR NOT, delay element 9, element 10 AND, AND elements NOT from the first 11 to the fourth 14, the first 15 and second 16 elements OR, the first 17 and second 18 comparators, inputs 19 differential encoded signal connected to the inputs of the receiver-Converter 5, the clock input 20 connected to the clock inputs of the triggers 1-3 and counter 4, the code output of the synchronized encoded signal, the output of the encoded signal clock, the start of the pause clock, the output of the pause clock, code input 21 of the pause detection threshold, which is the code input of counter 4, and code input 22 of the sync detection threshold needle of the encoded signal, wherein the code output of the asynchronous encoded signal of the receiver-converter 5 is connected to the code input of the register 6 and the first code input of the first comparator 17, the second code input of which is connected to the code output of the synchronized encoded signal of the device and the code output of register 6, the clock input of which is connected with the output of the clock signal of the encoded signal of the device and the direct output of the first trigger 1, the inverse output of which is connected to the reset input of the second trigger 2, inverse the output of which is connected to the first input of the first element 11 AND-NOT, the output of which is connected to the information input of the second trigger 2, the direct output of which is connected to the first input of the first element 7 OR-NOT and the output of the device pause clock signal, code input 22 of the encoded clock detection threshold the signal of which is connected to the first code input of the second comparator 18, the bit inputs of the second code input of which are connected to the inputs of the second element 12 AND-NOT, the first element 15 OR and the bit outputs of the code output with 4, the dominant asynchronous inverse reset input of which is connected to the output of the second element 16 OR, the first input of which is connected to the output of the delay element 9, the input of which is connected to the direct output of the third trigger 3 and the first input of the third element 13 AND-NOT, the output of which is connected to counter write enable input 4 and the first inputs of the second element 8 OR NOT and the AND element 10, the second input of which is connected to the output of the second element 12 AND NOT, the counter resolution enable input 4 and the second inputs of the first element 7 OR NOT and the first electronic element 11 AND NOT, the information input of the first trigger 1 is connected to the output of the second element 8 OR NOT, the second input of which is connected to the output of the first comparator 17 and the second input of the second element 16 OR, the third input of which is connected to the output of the first element 7 OR NOT the output signal of the pause start of the device, the inverse output of the third trigger 3 is connected to the first input of the fourth element 14 AND-NOT, the output of which is connected to the third input of the element 10 AND, the output of which is connected to the information input of the third trigger 3, and the outputs of the second the parator 18 and the first element 15 OR are connected respectively to the second inputs of the third 13 and fourth 14 elements AND NOT, while the reset and installation inputs of all the device triggers are the dominant asynchronous inverse, and the unused ones are connected to the device's logical 1 bus, which not shown in the drawing.

Denote by:

IXa and IXb, respectively, the first and second components of the differential three-level encoded signal IX (1) at the input 19 of the device;

X20 = IC - signal at the clock input 20 of the device;

Y (3: 0) and P (3: 0) - codes respectively on the code inputs 21 and 22;

C (3: 0) - code on the code output of the counter 4;

IX1 and IX0, respectively, the highest and lowest bit digits of the asynchronous encoded signal IX (1: 0) generated at the code output of the receiver-converter 5;

OX1 and OX0, respectively, the high and low digit digits of the synchronized encoded signal OX (1: 0) generated at the code output of register 6;

X1-X3 - signals at the direct outputs of triggers 1-3, respectively, and:

X1 = OSX - the encoded signal clock, such that such on the edge of the SOX in the register 6 is loaded the code OX (1: 0) = IX (1: 0);

X2 = ORX - pause sync signal;

NX1 = NOCX, NX2 = NOPX and NX3 - signals at the inverse outputs of triggers 1, 2 and 3, respectively;

X7-X16 and X17 and X18 are the signals at the outputs of elements 7-16 and comparators 17 and 18, respectively, whereby: X7 = OPC is the pause start sync signal.

With single signals at the installation and reset inputs, triggers 1-3 and counter 4 are synchronous machines with general synchronization along the edges of the clock pulses IC, acting on their clock inputs.

In the process of functioning of the device with single signals at the reset and installation inputs, information is received in triggers 1-3 on each front IC according to the equalities X1 = X8, X2 = X11, X3 = X10, information is received in register 6 on the edge of the clock signal X1 = OX according to the equality OX (1: 0) = IX (1: 0), writing to the counter 4 of the code Y (3: 0) is performed on the front of IC at X12 = 1, X13 = 0 and X16 = 1 according to the equality C (3: 0 ) = Y (3: 0) under the condition

and the above logical variables X7-X18 are formed by the formulas

Where

“! = N”, “#” and “&” - in the ABEL language, operators of operations “NOT”, “OR” and “AND”, respectively;

X3z = X9 - a signal repeating the signal X3 with a delay of 4 · Tz and generated at the output of element 9, formed, for example, by a serial connection of four elements NOT;

Tk - the average delay of any logical element of the device.

Counter 4 at X16 = 0 is fixed in the zero state C (3: 0) = 0000, and at X16 = 1, according to the clock pulses IC = X20 and signals X12 and X13, it functions as a synchronous machine with memory so that with X12 = 1 and X13 = 1 on the front of each IC, the code C (3: 0) of counter 4 is incremented by “1”, with X12 = 1 and X13 = 0 on the front of IC, the code C (3: 0) = Y (3: 0) is written into counter 4 the initial state of pause detection, and with X12 = 0 and X13 = 1, code C (3: 0) = 1111 is stored in counter 4, and the device with X2 = ORX = 0 generates a clock signal for the start of a pause OPC = X7 = 1 and signal X11 = 1 which, on the front of the next IC, sets trigger 2 to X2 = OPX = 1, and ystvo goes into a pause state and retain clock OPD = X2 = 1 up to the beginning of the first clock signal FSS = X1 = 1.

In view of the above, the functioning of the proposed device as an automaton with memory is logical to describe as a sequence of transitions from one state to another, namely from a pause state (SP)

in the first transition state (PPP)

Further, from the PPS (46), the device switches back to the SP (45) during an interference transition, and when the information transition is switched, the OXX = 1 clock signal is generated into the zero reception state (SPN)

or in a unit receiving state (SPE)

from SPN (47) (or SPE (48)) the device goes into the second transition state (IPN)

from IPN (49), the device switches back to STN (47) (or SPE (48)) during an interference transition, and when an information transition occurs, it switches to OX = 1 in SPE (48) (or SPN (47) or to the return state ( CB)

From SW (50), the device either switches to SP (45) after the formation of the clock signal of the beginning of the pause OPC = X9 = 1, or to the third transition state (TPS)

in the case of an interference transition, the device switches back to CB (50), and during the information transition, it switches to SPN (47) or SPE (48) with the formation of OSX = 1, where Q = (! X17 # X3) is a generalized a sign of the transition state of the device, given that the device is in the faculty (46) also with ORX & X12 = 1.

During operation, according to (45) - (51), at the beginning of the device switching to any transition state (PPS (46), IPS (49), TPN (51)) at X3 = 0, an output signal X16 is formed at the output of element 16 by X17 = 0 = 0, by which counter 4 is reset to C (3: 0) = 0000, for signals X13 = 1, X12 = 1 and X14 = 1, element 10 sets the signal X10 = 1, and for X10 = 1 on the first edge IC trigger 3 is set to X3 = 1 and allows for X12 = 1, X13 = 1 and X16 = 1 to counter 4 counting fronts IC, the number of which determines the first threshold number P according to the formula

so that with C (3: 0) = P (3: 0), signals X13 = 0, X10 = X13 = 0, X8 =! X17 are generated. Then, on the next edge of IC, Y (3: 0) is written into counter 4 at X13 = 0, trigger 3 at X10 = 0 is reset to X3 = 0, trigger 1 at X8 =! X17 = 0 remains in the reset state X1 = 0, and with X8 =! X17 = 1, trigger 1 is set and generates a clock signal OX = X1 = 1, along the edge of which register code OX (1: 0) = IX (1: 0) is written, comparator 17 sets the signal X17 = 1 earlier than the signal X9 will switch from "0" to "1", and the device will be in one of the following information states: SPN (47), SPE (48), CB (50). Then, on the next edge IC, trigger 1 is reset to X1 = OXX = 0, and the further operation of the device is carried out at X1 = 0, X3 = 0 and is completely determined by the value of the OX code (1: 0) and the further behavior in time of signal X17 (43).

If OX (1: 0) = 00, then with X17 = 1, the device is in CB (50), in which counter 4 counts the edges of IC at X12 = 1, X13 = 1 and X16 = 1 from the initial state C (3: 0) = Y (3: 0) pause detection, and the number of counted edges IC determines under condition (32) the second threshold number Y by the formula

Given (53), the pause detection time (TOP) is determined by the formula

so that when the counter 4 switches to C (3: 0) = 1111, element 12 generates a signal X12 = 0, which prohibits counter 4 from counting the edges of the IC and allows, when ORX = X2 = 0, the element 7 to generate a pause start signal OPC = X7 = 1, and element 11 of the signal X11 = 1. Then, with X11 = 1, on the next edge IC, trigger 2 sets the pause clock signal OPX = X2 = 1, and the device ends up in SP (45), from which it can go to PPS (46) only when X17 switches from “1” to “0 ".

From the foregoing it follows that if during operation of the proposed device, if X17 = 1 and X13 = 0, interference changes in the encoded signal IX (1: 0) are detected, then they are filtered during the operation of the device according to one of the functional graphs 1, 2, 3 (FG1, FG2, FG3), which are described by the expressions

and if information changes in signal IX (1: 0) are detected at X17 = 0 and X13 = 0, then the functioning of the device as a whole from SP (45) to SP (45) when entering a message in any two-level code is described by functional graph 4 (FG4)

and when entering a message, for example, in the form of a chess code "10 ... 10" in the RZ code is described by functional graph 5 (FG5)

and in VTK it is described by functional graph 6 (FG6)

Thus, the proposed device satisfies conditions (11) - (20) at P≥1, and its operation in time is a chain of transitions from one state to another in the form of functional graphs of type (55) - (60) with regular barrage filtering of synchronization each transient change in signal IX (1: 0) as interference at Ti≤P · Tic according to columns (55) - (57) and the regular transition of the device from the corresponding transition state ((46), (49), (51)) to the corresponding information state ((47), (48), (50)) at Ti≥ (1 + P) · Tic according to graphs of type (58) - (60).

If the device is supplemented with an OR element and an AND element to form a CXb bit synchronization signal according to the formula

CXb = OCX & (OX1 # OX0),

then it can be used as a noise-immune complete synchronous decoder of the RZ code, generating a synchronized signal OX = OX1 of receiving a bit of the RZ code accompanied by bit synchronization signals CXb, the beginning of an OPC pause and an OPC pause, or as a noise-free synchronous shaper of a synchronized signal reception OX = OX1 of a bit receiving code and clock CXb, OPC and OPC for any two-level code.

If the device is supplemented with an RS trigger with direct reset and installation inputs connected to the OX0 and OX1 outputs, respectively, then such a device can be used as a noise-immune full synchronous VTK decoder that generates a synchronized OX signal of the BTK bit reception at the RS output of the trigger, accompanied by CXb bit synchronization signals = OSX, the beginning of the OPC pause and the ORX pause, and the generated OX and CXb signals = OXX are functionally completely equivalent to the signals generated at the outputs of the asynchronous VT decoder K described in [3] on p.262, fig.4.20.

Directly from the descriptions of the technical solutions of the prototype [13] and this device, it follows that, due to essential features, the proposed device is more noise-resistant than the prototype due to the noise-resistant generation of the output synchronized encoded signal ОX (1: 0), the output clock signal OCX of the signal ОХ (1 : 0) and the output clock signals of the beginning of the OPC pause and the OPC pause for any two-level or three-level MPCS (for example, a two-level class 1В2В or a three-level RZ or VTK) with I can use the barrage filtering of the asynchronous encoded signal IX (1: 0) as interference when the duration of any change in this signal does not exceed the threshold duration P · Tic for P≥1.

LITERATURE

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Claims (1)

A device for receiving and synchronizing an encoded signal containing three triggers, a synchronous counter equipped with a clock input, an account resolution input and an inverse recording resolution input, priority over the account resolution input, AND element, first AND-NOT element, receiver-converter, inputs differential encoded signal, which are the inputs of the receiver-converter, the clock input, the code input of the pause detection threshold connected to the code input of the counter, and the outputs of the pause and pause clock signals from characterized in that it further comprises a code output of a synchronized encoded signal, a sync signal output of a coded signal, a register, two OR-NOT elements, a delay element, the second, third and fourth AND-NOT elements, two OR elements, two comparators and a detection threshold code input the clock signal of the encoded signal, the code output of the asynchronous encoded signal of the receiver-converter is connected to the code input of the register and the first code input of the first comparator, the second code input of which is connected nen with the code output of the synchronized encoded signal of the device and the code output of the register, the clock input of which is connected to the output of the clock signal of the encoded signal of the device and the direct output of the first trigger, the inverse output of which is connected to the reset input of the second trigger, the inverse output of which is connected to the first input of the first element And NOT, the output of which is connected to the information input of the second trigger, the direct output of which is connected to the first input of the first OR-NOT element and the output of the pause clock signal a device whose code input of the detection threshold of the clock signal of the encoded signal is connected to the first code input of the second comparator, the bit inputs of the second code input of which are connected to the inputs of the second NAND element, the first OR element and the bit outputs of the counter code output, the dominant asynchronous inverse reset input of which connected to the output of the second OR element, the first input of which is connected to the output of the delay element, the input of which is connected to the direct output of the third trigger and the first input of the third about the AND-NOT element, the output of which is connected to the counter recording permission input and the first inputs of the second OR-NOT element and the AND element, the second input of which is connected to the output of the second AND-NOT element, the counter account resolution input and the second inputs of the first OR-NOT elements and NAND, the information input of the first trigger is connected to the output of the second OR-NOT element, the second input of which is connected to the output of the first comparator and the second input of the second OR element, the third input of which is connected to the output of the first OR-NOT element and the clock signal output and at the beginning of a pause of the device, the clock input of which is connected to the clock inputs of the counter and all the triggers, the inverse output of the third trigger is connected to the first input of the fourth AND element, the output of which is connected to the third input of the AND element, the output of which is connected to the information input of the third trigger, and the outputs of the second comparator and the first OR element are connected respectively to the second inputs of the third and fourth AND-NOT elements, while the reset and installation inputs of all device triggers are dominant asynchronous inverse, and unused ones are connected to the logical 1 bus of the device.