RU2337501C2 - Method for blur compensation of moving object image and device for implementation of method - Google Patents

Abstract

FIELD: physics, computation equipment.

SUBSTANCE: the invention claims method of image blur compensation involving: calculation of difference between measured image pixel brightness and brightness assessment obtained earlier on the basis of previous frame sequence; movement detection by comparison of obtained difference to threshold value; defining of movement direction for each pixel; combination of adjoining pixels with the same movement direction in a single object; outlining contours of moving objects by adding their initial B(k) and gradient ▽(B(k)) of images; and generation of output image

where k₁, k₂ are weight factors. Device of image blur compensation includes: image sensor, controller, mode movement detection module, object detection module, correction module, first RAM device, second RAM device, third RAM device, counter, first comparator, second comparator, first multiplexor, second multiplexor, third multiplexor, fourth multiplexor, fifth multiplexor, sixth multiplexor, seventh multiplexor, first demultiplexor, second demultiplexor.

EFFECT: blur compensation for moving object image in real-time mode.

2 cl, 11 dwg

Description

The invention relates to computer technology and can be used to improve the clarity of the image coming from the video sensor when the video sensor is moving or moving objects are in the frame.

There is a method of eliminating image blur due to the movement of objects in a digital image (Tull D. L. Preventing blur caused by motion of the subject in a digital image, 2002, US patent No. 6441848). The method includes obtaining an image by a matrix photosensitive radiation receiver (MPPI) for a given accumulation time; calculating a variable value proportional to the intensity of the radiation flux for each pixel; calculating a second derivative of the specified variable for each pixel; comparing the value of the second derivative of the specified variable with a threshold value, the achievement of which corresponds to the detection of motion; calculating the accumulation time for each pixel as a percentage of the current accumulation time; change in accumulation time for each pixel according to the calculated percentage value.

The disadvantages of this method are:

- the presence of distortions in the resulting image caused by differences in brightness at the boundaries of regions with different accumulation times;

- its inapplicability for image receivers based on charge-coupled devices (CCD), for which it is impossible to change the accumulation time of each pixel separately.

A device is known that implements the function of eliminating image blur due to the movement of objects in a digital image (Tull DL Preventing blur caused by motion of the subject in a digital image, 2002, US patent No. 6441848), containing a matrix photosensitive radiation detector, in the composition of each elementary photosensor ( EF) which includes a motion detection circuit; focusing lens; a memory circuit connected to a matrix photosensitive radiation receiver that stores accumulation time values for each elementary photosensor.

The disadvantages of this device are:

- the high complexity of its technological design, associated with the need to embed motion detection schemes in each pixel;

- a decrease in the pixel fill factor (the ratio of the photosensitive surface of the pixel to its total area) due to the incorporation of a motion detection circuit into each pixel, which leads to a decrease in the sensitivity of the device and an increase in the level of geometric noise and noise of fixed wiring.

Closest to the invention is a method of compensating for blurriness caused by movement or saturation of an elementary photosensor, while expanding the dynamic range based on image synthesis over a series of frames (Liu et. All, Motion / saturation detection system and method for synthesizing high dynamic range motion blur free images from multiple captures, 2006, US patent No. 7061524). According to the method, the difference between the measured brightness of the image pixels and its previously obtained estimate is calculated on the basis of the sequence of previous frames, the movement is detected by comparing the obtained difference with a threshold value, in the absence of movement, the received brightness measurements are taken as a true image, if there is movement, the measured brightness values are adjusted based on received estimates.

The main disadvantage of this method is the processing of at least four frames to obtain an image with a sufficient degree of blur compensation, which imposes significant limitations on the speed of the device that implements the method, and in some cases, due to the formation of high resolution images by modern video sensors, the device cannot operate in the mode real time.

Closest to the proposed is a device for compensating for image blur caused by motion or saturation of EF (Liu et. All, Motion / saturation detection system and method for synthesizing high dynamic range motion blur free images from multiple captures, 2006, US patent No. 7061524). The device consists of: an image sensor, each EF of which contains motion / saturation detection means between the previous frame and the current frame; a processing unit that determines whether to accept for each EF a sample of the image captured during the current frame; a unit for estimating brightness during a global exposure time; a unit for determining the difference between the measured brightness obtained during the current frame and the brightness estimate generated during the previous frame for each EF; a unit for comparing the calculated difference with a threshold value for each EF; a block for estimating the brightness for each EF; an output image forming unit based on a final brightness estimate for each EF.

The disadvantage of this device is the low pixel duty ratio (not more than 10%), which significantly worsens the sensitivity of the video sensor, the high complexity of its technological design and high structural complexity associated with the need to incorporate motion detection schemes into each pixel.

An object of the invention is to compensate for blurring images of moving objects in real time for any type of MPPI (CCD based on semiconductor complementary metal-oxide-semiconductor (CMOS) pairs) while reducing the technological design of the device and reducing its structural complexity.

The problem is solved in that in the known method of compensating for motion blur caused by motion, including determining the interframe difference in brightness of the image, determining motion for each pixel of the image, adjusting the brightness of only moving pixels, the invention defines the direction of movement for each pixel by processing adjacent frames with a sliding window 3 × 3 elements and analysis of the total values of the elements of inter-frame differences, the union of adjacent pixels moving in one direction into an object based on the analysis of the distance between two pixels with the same direction of motion, underlining the contours of moving objects by adding the original image of a moving object with its gradient image.

The technical problem is solved by the fact that the controller, the MOD motion detection module, the object detection module, the correction module, the first RAM, the second RAM, the third RAM, the counter, the OR element, the first comparator, the second comparator, the first constant are introduced into the device containing the image sensor , second constant, first multiplexer, second multiplexer, third multiplexer, fourth multiplexer, fifth multiplexer, sixth multiplexer, seventh multiplexer, first demultiplexer, second demultiplexer, third constant.

The invention can be used to compensate for blurring images of moving objects in real time in various video sensors and systems of technical vision, made on the basis of solid-state MPPI of various types.

The invention is illustrated by drawings, where Fig. 1 shows an algorithm for a method of compensating for blurriness of an image, Fig. 2 shows codes of a direction for moving a pixel in an eight-connected neighborhood, Fig. 3 is a structural diagram of a device for compensating for blurring images of moving objects, and Fig. 4 is a structural controller diagram, FIG. 5 is a block diagram of a motion detection module, FIG. 6 is a block diagram of a register block, FIG. 7 is a block diagram of a summing block, FIG. 8 is a block diagram of an object detection module, in f g.9 - block diagram of the correction unit, Figure 10 - a block diagram of contour emphasizing module, 11 - the values of the constants register unit.

The process of compensating for blurring the image (Fig. 1) consists of several stages: reading the image, highlighting the moving pixels on the image based on the analysis of the interframe difference, determining the direction of movement of each pixel, combining adjacent pixels moving in the same direction into an object, emphasizing the contours of moving objects to compensate blurring the image by adding their original and gradient images, the formation of the output image.

The motion of each pixel relative to the current k-th frame is determined by the principle of inter-frame subtraction: the value of the difference of brightness of static pixels on adjacent frames is 0 (under the condition of constant illumination). The calculation is made for the eight-connected neighborhood of each pixel, each of the eight possible directions of movement is assigned a specific code.

To determine the number of the direction of movement r (Fig. 2) of each pixel (x, y), the frame is processed by a 3 × 3 sliding window as follows: for each pixel (x, y) of the current frame, a brightness matrix B (k) of adjacent pixels is compiled in 8 directions:

Elements of the matrix B (k), whose indices are 0, (X + 1) or (Y + 1), are taken equal to 0, where X, Y are the horizontal and vertical frame sizes, respectively.

Next, the matrix B (k) is converted into the matrix B ^* (k) by subtracting the brightness of the central pixel from the brightnesses of adjacent pixels:

This conversion allows you to take into account possible changes in the ambient illumination of the scene with the same arrangement of objects in the current frame relative to the previous frame.

Similarly, to process the previous (k-1) -th frame, the matrix B ^* (k-1) is compiled:

The result of subtracting the matrix B ^* (k-1) from the matrix B ^* (k) allows us to judge whether the central pixel remained stationary on adjacent frames if the central pixel of the resulting matrix B ^** (k / k-1) is equal to zero, t .e. the following condition is met:

If the central pixel of the resulting matrix B ^** (k / k-1) is not 0, a conclusion is drawn about the movement of this pixel.

Next, the direction of movement of each pixel is determined. For this, 8 matrices shifted by 1 pixel in each of 8 directions are formed from the matrix B ^* (k-1) (missing rows and / or columns are filled with zeros). The matrices for determining the displacement of the central pixel in the current frame relative to the previous one are defined in general form as follows:

To generate 8 resulting displacement matrices in each of the 8 directions, it is necessary to subtract each direction determination matrix from the matrix B ^* (k). The resulting image brightness matrices, which calculate the pixel movement on the current frame, are defined in general terms as follows:

The direction of movement of the pixel is the direction for which the total value of the brightness changes (the sum of all the elements of the resulting matrices) is minimal in absolute value.

where sup_ind (*) is a function whose value is the value of the upper index of the matrix B ^r (k / k-1).

Then, moving objects are determined. For this, it is necessary to find neighboring pixels with the same direction of motion, the search of which is carried out in accordance with formulas (8) - (13)

Neighboring pixels with the same direction of movement are grouped into objects in accordance with the formulas:

where ξ, ς are the coordinates of the pixel; Np + 1 - the minimum number of points in the object.

An object E _D is understood as a combination of image points different from the background with the direction of movement D, such that for each point there is at least one neighboring point located at a distance of 1 pixel, and the number of such points in the object must exceed the threshold value Np.

After that, the brightness correction of moving objects is implemented by emphasizing their contours (adding the original image with a gradient image). The output pixel brightness values are calculated as follows:

where ▽ (b _{x, y} (k)) is a gradient image such that

The brightness values of the static areas of the image remain unchanged.

The image blur compensation device (Fig. 3) comprises an image sensor DI 10, a controller 1, a motion detection module MOD 2, an object detection module MOO 3, a correction module MK 4, a first RAM 5, a second RAM 6, a third RAM 7, a counter 100, OR element 101, first comparator 102, first multiplexer 51, second multiplexer 52, third multiplexer 53, fourth multiplexer 54, fifth multiplexer 55, sixth multiplexer 57, seventh multiplexer 59, first demultiplexer 56, second demultiplexer 58, the input CLK / 3 is intended for tact signal in DI 10 and connected to the first input of controller 1, the group output of DI 10 is connected to the first group input of controller 1, the second group output of controller 1 is connected to the first group inputs of the first multiplexer 51 and third multiplexer 53, the group output of the first multiplexer 51 is connected to the group input of the first RAM 5, the group input-output of the first RAM 5 is connected to the group input of the first demultiplexer 56 and to the group output of the fifth multiplexer 55, the first group output of the demultiplexer 56 is connected to the fourth group input of controller 1, the group input-output of the second RAM 6 is connected to the group input of the second demultiplexer 58 and to the group output of the sixth multiplexer 57, the third group output of controller 1 is connected to the system bus, the fourth group output of controller 1 is connected to the first group input of the sixth multiplexer 57, the first group output of controller 1 is connected to the first group input of the fifth multiplexer 55, the first output of controller 1 is connected to the first input of the second multiplexer 52, the output of the second multiplexer 52 is connected to the input of the first RAM 5, the second output of controller 1 is connected to the first input of the fourth multiplexer 54, the output of which is connected to the input of the second RAM 6, the second and third group inputs of controller 1 are used to supply constants (X-1) and (Y- 1) respectively (where X, Y is the horizontal and vertical image dimension), the second input of controller 1 is designed to supply a CLK clock signal and is connected to the second input of MOD 2, the third input of controller 1 is connected to the output of the first comparator 102, the first group input of whichconnected to the group output of the counter 100 and the fifth group input of MOD 2, the constant 0 is applied to the second group input of the first comparator 102, the third output of controller 1 is connected to the first input of the OR element 101, the first input of MOD 2 is used to supply the CLK / 25 clock signal, the first and the second group inputs of MOD 2 are used to supply constants (X-3) and (Y-3), respectively, the third group input of MOD 2 is connected to the group output of the second demultiplexer 58, the fourth group input of MOD 2 is connected to the second group output of the first demultip lexor 56, the first group output of MOD 2 is connected to the second group inputs of the first multiplexer 51 and the third multiplexer 53, the second group output of MOD 2 is connected to the second group input of the seventh multiplexer 59, the third group output of MOD 2 is connected to the group input-output of RAM 7 and the first group input MOO 3, the first output of MOD 2 is connected to the second input of the OR element 101, the second output of MOD 2 is connected to the input of the seventh multiplexer 59, the third output of MOD 2 is connected to the input of the third RAM 7, the second and third group inputs of MOO 3 are designed started to feed constants (X-2) and (Y-2), respectively, the fourth group input MOO 3 is connected to the first group output MK 4, the fifth group input MOO 3 is connected to the fourth group output MK 4, the sixth group input MOO 3 is connected to group output of the counter 100, the first, second and third inputs of MOO 3 are designed to supply clock signals CLKX, CLKX6, CLKY, respectively, the first group output of MOO 3 is connected to the first group input of the seventh multiplexer 59, the group output of which is connected to the group input of the third RAM 7, second gro the pooled output of MOO 3 is connected to the first group input of MK 4, the third group output of MOO 3 is connected to the second group input of MK 4, the fourth group output of MOO 3 is connected to the third group input of MK 4, the output of MOO 3 is connected to the third input of the PLI 101 element and to the third input MK 4, the fourth input of the OR element 101 is connected to the output MK 4, the second group output MK 4 is connected to the third group input of the first multiplexer 51, the third group output MK 4 is connected to the second group input of the fifth multiplexer 55, the fourth group input MK 4 is designed to supply a threshold value P that determines the minimum number of pixels in the object, the fifth group input MK 4 is connected to the third group output of the first demultiplexer 56, the first and second inputs of MK 4 are used to supply clock signals CLKW and CLKZ, respectively, to the second input of the second multiplexer 52 a constant 0 is applied, the group output of the counter 100 is connected to the fourth group input of the first multiplexer 51, the group input of the second multiplexer 52, the third group input of the third multiplex an expor 53, the fifth group input of the fourth multiplexer 54, the third group input of the fifth multiplexer 55, to the second group input of the sixth multiplexer 57, and also to the second group inputs of the first demultiplexer 56 and the second demultiplexer 58, to the second, third, fourth inputs of the fourth multiplexer 54 constant 0, while the first multiplexer 51 ensures the passage of the signal from its first group input to its group output with a value of "0" at its fourth group input, from its second group the first input - with the value “1”, from its third group input - with the value “3”, the second multiplexer 52 provides a signal from its first group input to its group output with the value “0” at its third group input, from its second group input - with a value of “3”, the third multiplexer 53 provides a signal from its first group input to its group output with a value of “0” at its third group input, from its second group input - with a value of “1”, the fourth multiplexer 54 provides a signal from its first group input to its group output with a value of “0” at its fifth group input, from its second group input with a value of “1”, from its third group input with a value of “2”, from its the fourth group input - with a value of “3”, the fifth multiplexer 55 provides a signal from its first group input to its group output with a value of “0” at its third group input, from its second group input - with a value of “3”, the sixth multiplexer 57 provides a signal from its first group input to its group output with a value of “0” at its second group input, the first demultiplexer 56 provides a signal from its group input to its first group output with a value of “0” at its second group input, at a value of “1” - to its second group output, with a value of “3” - to its third group output, the second demultiplexer 58 provides a signal from its group input to its group output with a value of “1” on its second group ppovom inlet seventh multiplexer 59 provides signal transmission with a first group of its inputs to its output when a group value "0" at its input, and the second group input - at a value of "1".

The controller 1 (Fig. 4) comprises: a first OR element 11, a second OR element 12, a first counter 13, a second counter 14, a third counter 15, a first comparator 16, a second comparator 17, an address generator 18, an And element 19, a buffer 110, and demultiplexer 111, and the first input of the first counter 13 is the first input of the controller 1 and is designed to supply the CLK / 3 clock signal, the first group output of the first counter 13 is connected to the first group inputs of the first comparator 16 and address former 18, the group output of the former 18 is the second group out ohm controller 1, the second group input of the first comparator 16 is the second group input of the controller 1, the output of the first comparator 16 is connected to the second input of the first element OR 11, to the first input of the second counter 14 and to the first input of the element And 19, the group output of the second counter 14 is connected to the second group input of the address generator 18 and to the first group input of the second comparator 17, the second group input of the comparator 17 is the third group input of the controller 1, the output of the comparator 17 is connected to the second input of the element And 19, to the second input of the second element OR 12 and the first input of the first element OR 11, the third input of the first element OR 11, the first input of the second element OR 12 and the second input of the third counter 15 are connected to the third input of the controller 1, the first input of the third counter 15 is the second input of the controller 1 and is designed to supply a clock signal CLK, the group output of the third counter 15 is connected to the second group input of the buffer 110 and the second group input of the demultiplexer 111, the first group input of the buffer 110 is the first group input the controller, the group output of the buffer 110 is the first group output of the controller 1, the first group input of the demultiplexer 111 is the fourth group input of the controller 1, the first group output of the demultiplexer 111 is the third group output of the controller 1, the second group output of the demultiplexer 111 is the fourth group output of the controller 1, senior the group output bit of the third counter 15 is the first output of the controller 1, the output of the element And 19 is the third output of the controller 1, the least significant bit of the group Exit third counter 15 is a second output of the controller 1.

The motion detection module MOD 2 (Fig. 5) includes a first counter 21, a second counter 22, a third counter 23, a fourth counters 24, a first comparator 25, a second comparator 26, a first adder 27, a second adder 28, a first address generator 29, an OR element 210, AND element 211, first register block 212, second register block 213, third register block 214, fourth register block 215, fifth register block 216, sixth register block 217, seventh register block 218, eighth register block 219, ninth register block 220 , tenth register block 221, first a summing block 222, a second summing block 223, a third summing block 223, a fourth summing block 225, a fifth summing block 226, a sixth summing block 227, a seventh summing block 228, an eighth summing block 229, a ninth summing block 230, a minimum determination circuit 231, a third comparator 233, fourth comparator 234, fifth comparator 235, sixth comparator 236, seventh comparator 237, eighth comparator 238, ninth comparator 239, tenth comparator 240, eleventh comparator 241, encoder 242, third adder 244, fourth adder 245, second form address equalizer 246, twelfth comparator 247, the first input of the first counter 21 being the first input of MOD 2 and designed to supply a clock signal with a frequency of CLK / 25, the second input of the first counter 21, which is the reset input, is connected to the output of the OR element 210, the output of the first the comparator 25 is connected to the second input of the OR element 210 and the first input of the second counter 22, the group output of the first counter 21 is connected to the first group input of the first comparator 25, the first group input of the first adder 27 and the first group input h of the fourth adder 245, the group output of the second counter 22 is connected to the first group input of the second comparator 26, the first group input of the second adder 28 and the first group input of the third adder 244, the second group input of the first comparator 25 is the first group input of MOD 2 and is designed to supply a constant value (X-3), the second group input of the second comparator 26 is the second group input of MOD 2 and is designed to supply a constant value (Y-3) the output of the second comparator 26 is connected to the second input of the second about the counter 22, which is the reset input, and to the first input of the OR element 210, the input of the third counter 23, which is the second input of MOD 2, is used to supply the CLK clock signal, the group output of the third counter 23 is connected to the second group input of the first adder 27, the output of the third counter 23 is connected to the input of the fourth counter 24, the group output of which is connected to the second group input of the second adder 28, the group output of the first adder 27 is connected to the first group input of the first shaper address 29, and the group output the second adder 28 is connected to the second group input of the first address generator 29, the output of the first address generator 29 is the first group output of MOD 2, the first group input of the first register block 212 is the fourth group input of MOD 2, the third group input of MOD 2 is connected to the first group inputs of the second register block 213, third register block 214, fourth register block 215, fifth register block 216, sixth register block 217, seventh register block 218, eighth register block 219, the ninth register block 220, the tenth register block 221, the second group inputs of the first register block 212, the second register block 213, the third register block 214, the fourth register block 215, the fifth register block 216, the sixth register block 217, the seventh register block 218, the eighth register block 219, the ninth register block 220, the tenth register block 221 are connected to the group output of the fourth counter 24, the third group inputs of the first register block 212, the second register block 213, t the second register block 214, the fourth register block 215, the fifth register block 216, the sixth register block 217, the seventh register block 218, the eighth register block 219, the ninth register block 220, the tenth register block 221 are connected to the group output of the third counter 23, the group of outputs of the first register block 212 is connected to the first input groups of the first summing block 222, the second summing block 223, the third summing block 224, the fourth summing block 225, the fifth summing block 226, the sixth summing block 227, seventh summing block 228, eighth summing block 229, ninth summing block 230, output group of the second register block 213, third register block 214, fourth register block 215, fifth register block 216, sixth register block 217, seventh register block 218 , the eighth register block 219, the ninth register block 220, the tenth register block 221 are connected to the second group inputs of the first summing block 222, the second summing block 223, the third summing block 224, fourth summing block 225, fifth summing block 226, sixth summing block 227, seventh summing block 228, eighth summing block 229, ninth summing block 230, group outputs of the first summing block 222, second summing block 223, third summing block 224, fourth summing block 225, the fifth totalizing unit 226, the sixth totalizing unit 227, the seventh totalizing unit 228, the eighth totalizing unit 229, the ninth totalizing unit 230 are connected to the first, second, third, respectively the fourth, fifth, sixth, seventh, eighth, ninth inputs of the minimum determination unit 231, as well as the first group inputs of the third comparator 233, fourth comparator 234, fifth comparator 235, sixth comparator 236, seventh comparator 237, eighth comparator 238, ninth comparator 239 , the tenth comparator 240, the second group inputs of which are connected to the group input of the minimum detection circuit 231, the group output of the fifth summing block 226 is connected to the first group input of the eleventh comparator 241, to the second groups whose input is constant 0, the outputs of the third comparator 233, fourth comparator 234, fifth comparator 235, sixth comparator 236, seventh comparator 237, eighth comparator 238, ninth comparator 239, tenth comparator 240 are connected to the group input of the encoder 242, the group output of which the third group output of MOD 2, the output of the eleventh comparator 241 is the third output of MOD 2, the second group inputs of the third adder 244, fourth adder 245 and twelfth comparator 247 are connected to constant 2, the first outputs of the third adder 244 and the fourth adder 245 are connected to the group inputs of the second address generator 246, the group output of which is the second group output of MOD 2, the first group input of the twelfth comparator 247 is the fifth group input of MOD 2, the inputs of element 211 are connected to the outputs of the first comparator 25 and the second comparator 26, respectively, the output of the element And 211 is the first output of MOD 2.

Each register block 212 ÷ 221 (Fig. 6) consists of a first comparator 81, a second comparator 82, a third comparator 83, a fourth comparator 84, a fifth comparator 85, a sixth comparator 86, a seventh comparator 87, an eighth comparator 88, a ninth comparator 89, the first register 810, second register 811, third register 812, fourth register 813, fifth register 814, sixth register 815, seventh register 816, eighth register 817, ninth register 818, first adder 819, second adder 820, third adder 821, fourth adder 822 fifth with Matter 823, sixth adder 824, seventh adder 825, eighth adder 826, first constant 851, second constant 852, third constant 854, fourth constant 854, fifth constant 855, sixth constant 856, seventh constant 857, eighth constant 858, ninth constant , the tenth constant 860, the eleventh constant 861, the twelfth constant 862, the thirteenth constant 863, the fourteenth constant 864, the fifteenth constant 865, the sixteenth constant 866, the seventeenth constant 867, the eighteenth constant 868, and the first group input of the register block and connected to the group inputs of the first register 810, second register 811, third register 812, fourth register 813, fifth register 814, sixth register 815, seventh register 816, eighth register 817, ninth register 818, the second group input of the register block is connected to the first group the inputs of the first comparator 81, the second comparator 82, the third comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87, the eighth comparator 88, the ninth comparator 89, the third group register input the block is connected to the third group inputs of the first comparator 81, the second comparator 82, the third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87, the eighth comparator 88, the ninth comparator 89, the outputs of the first comparator 81, the second comparator 82, the third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87, the eighth comparator 88, the ninth comparator 89 are connected to the inputs of the first register 810, the second register 811, the third register 812, fourth register 813, fifth register 814, sixth register 815, seventh register 816, eighth register 817, ninth register 818, respectively, group outputs of the first register 810, second register 811, third register 812, fourth register 813, sixth register 815 , seventh register 816, eighth register 817, ninth register 818 connected to the first group inputs of the first adder 819, second adder 820, third adder 821, fourth adder 822, fifth adder 823, sixth adder 824, seventh adder 825, eighth the adder 826, respectively, the group output of the fifth register 814 is connected to the second group inputs of the first adder 819, the second adder 820, the third adder 821, the fourth adder 822, the fifth adder 823, the sixth adder 824, the seventh adder 825, the eighth adder 826, the outputs of the first adder 819 , the second adder 820, the third adder 821, the fourth adder 822, the fifth adder 823, the sixth adder 824, the seventh adder 825, the eighth adder 826 are a group of outputs of the register block, the output of the fifth adder 823 is I am the fifth output of the group of outputs of the register block, the output of the seventh adder 825 is the seventh output of the group of outputs of the register block, the first constant 851, the third constant 853, the fifth constant 855, the seventh constant 857, the ninth constant 859, the eleventh constant 861, the thirteenth constant 863, 865, the seventeenth constant 867 is connected to the second group inputs of the first comparator 81, the second comparator 82, the third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87, the eighth comparator 88, the ninth comparator 89, respectively, the second constant 851, the fourth constant 854, the sixth constant 856, the eighth constant 858, the tenth constant 860, the twelfth constant 862, the fourteenth constant 864, the sixteenth constant 866, the eighteenth fourth constant 868 the inputs of the first comparator 81, second comparator 82, third comparator 83, fourth comparator 84, fifth comparator 85, sixth comparator 86, seventh comparator 87, eighth comparator 88, ninth comparator 89 correspond permanently. The values of the first constant 851, the second constant 852, the third constant 854, the fourth constant 854, the sixth constant 856, the seventh constant 857, the eighth constant 858, the ninth constant 859, the tenth constant 860, the eleventh constant 861, the twelfth constant 862, and thirteen constants 863, fourteenth constant 864, fifteenth constant 865, sixteenth constant 866, seventeenth constant 867, eighteenth constant 868 is determined from the table depicted in Fig.11.

Each adder block 222-230 (Fig. 7) consists of a first adder 91, a second adder 92, a third adder 93, a fourth adder 894, a fifth adder 95, a sixth adder 96, a seventh adder 97, an eighth adder 98, and a ninth adder 99, wherein the outputs of the first adder 91, second adder 92, third adder 93, fourth adder 94, fifth adder 95, sixth adder 96, seventh adder 97, eighth adder 98 are connected to the first, second, third, fourth, fifth, sixth, seventh, eighth inputs ninth adder 99 respectively Naturally, the first inputs of the first adder 91, the second adder 92, the third adder 94, the fourth adder 94, the fifth adder 96, the seventh adder 97, the eighth adder 98 are the first group of inputs of the adder block, the second inputs of the first adder 91, the second adder 92, the third adder 93, the fourth adder 94, the fifth adder 95, the sixth adder 96, the seventh adder 97, the eighth adder 98 are the second group of inputs of the adder block, the group output of the ninth adder 99 is a group output ohm of the summing block.

The MOO 3 object definition module (Fig. 8) consists of a first counter 31, a second counter 32, a third counter 33, a fourth counter 34, a fifth counter 35, a sixth counter 36, a trigger 37, a first AND element 38, a first OR element 39, a first adder 310, second adder 311, third adder 312, fourth adder 313, fifth adder 314, first comparator 315, second comparator 316, second address former 318, data converter 319, first address former 320, second AND element 321, first multiplexer 322, the first element is NOT 323, first register 324, third comparator 325, third element And 327, fourth comparator 328, fifth comparator 331, sixth comparator 332, seventh comparator 333, eighth comparator 334, ninth comparator 335, tenth comparator 336, second register 337, third register 338 , fourth register 339, fifth register 340, sixth register 341, seventh register 342, eleventh comparator 343, twelfth comparator 344, thirteenth comparator 345, fourteenth comparator 346, fifteenth comparator 347, sixteenth comparator 348, h the fourth element And 361, the fifth element And 362, the sixth element And 363, the seventh element And 364, the eighth element And 365, the ninth element And 366, the eighth register 367, the ninth register 368, the tenth register 369, the eleventh register 370, the twelfth register 371, thirteenth register 372, second OR element 373, third OR element 374, fourth OR element 375, fifth OR element 376, seventh counter 377, eighth counter 378, ninth counter 379, fourteenth register 380, tenth element AND 381, tenth counter 382, buffer element 383, second mu multiplexer 384, eleventh element AND 385, twelfth element And 386, second buffer element 387, third multiplexer 388, seventeenth comparator 389, third buffer element 391, eighteenth comparator 392, first RAM 71, second RAM 72, third RAM 73, the first input the first element And 38 is the first input of MOO 3 and is designed to supply a clock signal CLKX, the output of the trigger 37 is connected to the second input of the first element And 38, the output of the first element And 38 is connected to the first input of the first counter 31, the group output of the first the meter 31 is connected to the first group input of the first address generator 320 and to the first group input of the first comparator 315, the second group input MOO 3 is connected to the second group input of the first comparator 315, the output of the first comparator 315 is connected to the first input of the second element And 321, to the second input the first element OR 39 and to the first input of the second counter 32, the output of the first element OR 39 is connected to the second input of the first counter 31, the group output of the second counter 32 is connected to the first group input of the second comparator 316 and the second group input of the first shaper address 320, whose output is connected to the first group input of the first multiplexer 322, the third group input MOO 3 is connected to the second group input of the second comparator 316, the output of the second comparator 316 is connected to the second input of the second element And 321, to the second input the second counter 32 and to the first input of the first element OR 39, the output of the second element And 321 is the output of MOO 3, the output of the trigger 37 is connected to the input of the first element NOT 323 and to the input of the first register 324, the output of the first element NOT 323 sub is accessible to the input of the first multiplexer 322, to the third input of the fifth counter 35, to the second input of the sixth counter 36 and to the first and second inputs of the third buffer element 391, whose output is connected to the input / output of the first RAM 71, the first group input MOO 3 is connected to the group the input of the first register 324, the group output of the first register 324 is connected to the first group input of the third comparator 325, to whose second group input the constant 0 is supplied, the output of the third comparator 325 is connected to the first input of the third AND 327 element, the output of which is connected It is connected to the first input of the trigger 37, the input / output of the first RAM 71 is connected to the first input of the fourth comparator 328, whose second input is constant 1, the output of the fourth comparator 328 is connected to the second input of the third AND element 327, the input of the third counter 33 is the second input of the MOO 3 and is intended to supply a clock signal CLKX6, the group output of the third counter 33 is connected to the input of the fourth counter 34, the group output of the third counter 33 is connected to the first group input of the first adder 310, to which the second group input is supplied to 1, the output of the first adder 310 is connected to the first group input of the second adder 311, whose second group input is connected to the group output of the fifth counter 35, the third group input of the second adder 311 is connected to the group output of the first counter 31, the first group input of the third adder 312 is connected to the group output of the fourth counter 34, the second group input of the third adder 312 is connected to the group output of the sixth counter 36, the third group input of the third adder 312 is connected to the group output of the second counter a 32, the group outputs of the second adder 311 and the third adder 312 are connected respectively to the first and second group inputs of the second address generator 318, the group output of which is connected to the second group input of the first multiplexer 322 and to the group input of the first RAM 71, the group output of the third counter 33 is connected to the first group inputs of the fifth comparator 331, the sixth comparator 332, the seventh comparator 333, the eighth comparator 334, the ninth comparator 335, the tenth comparator 336, the group output of the fourth counter 34 connected to the third group inputs of the fifth comparator 331, sixth comparator 332, seventh comparator 333, eighth comparator 334, ninth comparator 335, tenth comparator 336, the second group input and the fourth group input of the fifth comparator 331 are supplied with constant 0, the second group input and to the fourth group input of the sixth comparator 332, respectively, constant 1 and constant 0 are supplied, to the second group input and to the fourth group input of the seventh comparator 333 are fed respectively constant 2 and constant 0, to the second the group input and the fourth group input of the eighth comparator 334 are supplied, respectively, the constant 0 and constant 1, the second group input and the fourth group input of the ninth comparator 335 are supplied with the constant 1, the constant 2 are fed to the second group input and the fourth group input of the tenth comparator 336, respectively and constant 1, the output of the fifth comparator 331 is connected to the input of the second register 337, the output of the sixth comparator 332 is connected to the input of the third register 338, the output of the seventh comparator 333 is connected to the input of the fourth reg Istra 339, the output of the eighth comparator 334 is connected to the input of the fifth register 340, the output of the ninth comparator 335 is connected to the input of the sixth register 341, the output of the tenth comparator 336 is connected to the input of the seventh register 342, the first group inputs of the second register 337, third register 338, fourth register 339 , fifth register 340, sixth register 341, seventh register 342 connected to the first group input MOO 3, group outputs of the second register 337, third register 338, fourth register 339, fifth register 340, sixth register 341, seventh register 342 are connected respectively to the first group inputs of the eleventh comparator 343, twelfth comparator 344, thirteenth comparator 345, fourteenth comparator 346, fifteenth comparator, 347 and sixteenth comparator 348, whose second group inputs are connected to the group output of the first register 324, the output of the eleventh comparator 343 the first input of the fourth element And 361 and to the third input of the ninth element And 366, the output of the twelfth comparator 344 is connected to the first input of the fifth element And 362, to the second input of the fourth of that element And 361, to the first input of the sixth element And 363, to the second input of the seventh element And 364, to the first input of the eighth element And 365 and to the first input of the ninth element And 366, the output of the thirteenth comparator 345 is connected to the second input of the fifth element And 362 and the fifth input of the ninth element And 366, the output of the fourteenth comparator 346 is connected to the first input of the seventh element And 364 and the sixth input of the ninth element And 366, the output of the fifteenth comparator 347 is connected to the second input of the eighth element And 365 and the fourth input of the ninth element And 366, output q of the sixteenth comparator 348 is connected to the second input of the sixth element And 363 and the second input of the ninth element And 366, the output of the fifth element And 362 is connected to the third input of the sixth element And 363, whose output is connected to the third input of the eighth element And 365, whose output is connected to the third the input of the seventh element And 364, whose output is connected to the third input of the fourth element And 361, the outputs of the fourth element And 361, the fifth element And 362, the sixth element And 363, the seventh element And 364, the eighth element And 365, the ninth element And 366 are connected respectively the first inputs of the eighth register 367, the ninth register 368, the tenth register 369, the eleventh register 370, the twelfth register 371, the thirteenth register 372, whose second inputs are connected to the output of the tenth comparator 336, and the third inputs of these registers are connected to the output of the fifth comparator 331, the output of the eighth register 367 is connected to the second input of the fifth OR element 376 and to the first input of the second OR element 373, the output of the ninth register 368 is connected to the first input of the third OR element 374 and to the second input of the second OR element 373, the output of the tenth p register 369 is connected to the first input of the fourth OR element 375 and to the third input of the second OR element 373, the output of the eleventh register 370 is connected to the first input of the fifth OR element 376 and to the fourth input of the second OR element 373, the output of the twelfth register 371 is connected to the third input of the fourth element OR 375 and to the fifth input of the second element OR 373, whose output is connected to the first input of the seventh counter 377 and to the first input of the eighth counter 378, the output of the third element OR 374 is connected to the first input of the fifth counter 35, the fourth output OR element 375 is connected to the first input of the sixth counter 36, the output of the fifth element OR 376 is connected to the second input of the fifth counter 35, the output of the thirteenth register 372 is connected to the second input of the ninth counter 379, which is an inverse input, to the first input of the tenth element And 381 and to the first the input of the tenth counter 382, the first input of the ninth counter 379, is the third input of MOO 3 and is designed to supply the CLKY clock signal, the first output of the ninth counter 379 is connected to the second input of the tenth element And 381, the output of the tenth element And 381 sub is accessible to the input of the fourteenth register 380, the group output of the seventh counter 377 is connected to the group input of the fourteenth register 380, the group output of the fourteenth register 380 is connected to the group input of the buffer element 383, whose output is connected to the group input-output of the second RAM 72, the group output of the tenth counter 382 connected to the first group input of the second multiplexer 384, whose second group input is the fourth group input of MOO 3, the group output of the second multiplexer 384 is connected to the group input of the second RAM 72, the first and second outputs of the ninth counter 379 are connected respectively to the first and second inputs of the eleventh element And 385, the first input of which is inverse, and the output is connected to the second input of the twelfth element And 386, whose output is connected to the input of the second RAM 72, the first group input the fourth adder 313 is connected to the group output of the fifth counter 35, the second group input of the fourth adder 313 is connected to the group output of the first counter 31, the first group input of the fifth adder 31 is connected to the group output of the second counter 32, the second group input of the fifth adder 314 is connected to the group output of the sixth counter 36, the group outputs of the fourth adder 313 and the fifth adder 314 are respectively connected to the first and second group inputs of the data converter 319, whose output is connected to the group input of the second buffer element 387, group the output of which is connected to the group input-output of the third RAM 73, the group output of the eighth counter 378 is connected to the first group input of the third multiplexer 388, the second group input of the third mult Ilexer 388 is the fifth group input of MOO 3, the group output of the third multiplexer 388 is connected to the group input of the third RAM 73, the first group input of the seventeenth comparator 389 is connected to the group output of the first counter 31, the second group input of the seventeenth comparator 389 is connected to the group output of the second counter 32, at the third group input of the seventeenth comparator 389 a constant 0 is supplied, the output of the seventeenth comparator 389 is connected to the second input of the eighth counter 378 and to the second input of the tenth counter 382, sixth the MPO 3 input is connected to the first group input of the eighteenth comparator 392, the constant 2 is supplied to the second group input, the output of the eighteenth comparator 392 is connected to the first input of the twelfth element And 386, the input of the second multiplexer 384 and the input of the third multiplexer 388, the group output of the first multiplexer 322 is the first group output of MOO 3, the group output of the tenth counter 382 is the second group output of MOO 3, the group input / output of the second RAM 72 is the third group output of MOO 3, group the input / output of the third RAM 73 is the fourth group output of MOO 3, while the trigger 37 is an RS-trigger, the first input of which is an R-input, the second input is an S-input, the first output of the ninth counter 379 is the least significant bit of its output value, the second the output is in the highest category, the inputs of the second multiplexer 324 and the third multiplexer 388 are inverse inputs, the data of the first RAM 71 are single-bit.

Correction module MK 4 (Fig. 9) consists of the first register 453, the first comparator 454, the first counter 455, the second comparator 456, the pulse generator 457, the second element And 458, the second counter 459, the third comparator 460, the first trigger 461, the first element And 462, fourth comparator 463, fifth comparator 464, third counter 465, second trigger 466, second register 467, third register 468, fourth register 469, multiplexer 470, data converter 471, first adder 472, second adder 473, first constant 474, equal to 1, shaper addresses 475, second constant 476, equal to 0, third constant 477, equal to 1, fourth constant 478, equal to 2, underline emphasis module 479, fifth register 480, seventh comparator 481, fifth constant 482, equal to 3, third element AND 483, sixth comparator 484, the input of the first register 453 being the third input of MK 4, the first group input of MK 4 connected to the group input of the first register 453, the group output of the first register 453 connected to the first group input of the first comparator 454, the output of the first comparator 454 connected to the second input of the first counter 455 and to the first output of MK 4, the first group output of MK 4 is connected to the group output of the first counter 455, the second group input of MK 4 is connected to the first group input of the second comparator 456, to the first group input of the third comparator 460 and to the first group input of the generator pulses 457, the fourth group input MK 4 is connected to the second group input of the second comparator 456, the output of the second comparator 456 is connected to the input of the pulse generator 457, to the second input of the third counter 465 and to the first input of the first trigger 461, in the output of the pulse generator 457 is connected to the first input of the second AND element 458, whose output is connected to the first input of the second counter 459, whose group output, which is the fourth group output of MK 4, is connected to the second group input of the third comparator 460, whose output is connected to the second input of the first trigger 461 and to the second input of the second counter 459, the output of the first trigger 461 is connected to the second input of the first element And 462, the output of the first element And 462 is connected to the first input of the first counter 455, the first input MK 4 is designed to supply output signal CLKW and connected to the first input of the first element And 462 and the first input of the third element And 483, the second input of which is connected to the output of the second trigger 466, and the output of the third element And 483 is connected to the second input of the second element And 458, the second input MK 4 is for applying a clock signal CLKZ and is connected to the first input of the third counter 465, the group output of the third counter 465 is connected to the group input of the fourth comparator 463, whose output is connected to the first input of the second trigger 466 and to the input of the second register 467, group input One of which is connected to the fifth group input of the MK 4 module, the group inputs of the third register 468 and the fourth register 469 are also connected to the fifth group input of the MK 4 module, the group output of the third counter 465 is connected to the ninth group input of the multiplexer 470, the third group input of MK 4 is connected to the group input of the data converter 471, whose first group output is connected to the first, third and fourth group inputs of the multiplexer 470 and the first input of the first adder 472, the second group output of the data converter 471 connected to the fifth, sixth and eighth group inputs of the multiplexer 470 and the second group input of the second adder 473, the third constant 474 equal to 1 is fed to the second group input of the first adder 472 and to the first group input of the second adder 473, the group output of the first adder 472 is connected to the second the group input of the multiplexer 470, the group output of the second adder 473 is connected to the seventh group input of the multiplexer 470, the first and second group outputs of the multiplexer 470 are connected respectively to the first and second input m of the address generator 475, whose group output is the second group output MK 4, the output of the fifth comparator 464 is connected to the input of the third register 468, the output of the sixth comparator 484 is connected to the input of the fourth register 469, to the second group inputs of the fourth comparator 463, fifth comparator 464, sixth comparator 484 is supplied with constant values specified by a second constant 476, a third constant 477, a fourth constant 478 equal to 0, 1 and 2, respectively, group outputs of the second register 467, third register 468 and fourth register 469 p are connected respectively to the first, second, and third group inputs of the underlining module 479, whose group output is connected to the group input of the fifth register 480, the output of the third counter 465 is connected to the first group input of the seventh comparator 481, to whose second input the fifth constant 482, equal to 3, is supplied , the output of the seventh comparator 481 is connected to the second input of the second trigger 466 and to the input of the fifth register 480, whose group output is the third group output of MK 4, the output of the second trigger 466 is the second output of MK 4.

The loop emphasis module IPC 479 (FIG. 10) consists of a first multiplier 411, a second multiplier 412, a third multiplier 413, a fourth multiplier 414, a third adder 417, a square root highlighting module 419, a first adder 420, a second adder 421, and a fourth adder 422, moreover, the first group input of the IPC 479 is connected to the first group input of the first adder 420, the second group input of the IPC 479 is connected to the second group input of the first adder 420 and the first group input of the second adder 421, the third group input of the IPC 479 is connected to the second group input of the second adder 421, the group output of the first adder 420 is connected to the first and second group inputs of the first multiplier 411, the group output of the second adder 421 is connected to the first and second group inputs of the second multiplier 412, the group outputs of the first multiplier 411 and the second multiplier 412 are connected respectively, to the first and second group inputs of the third adder 417, whose group output is connected to the group input of the square root selection module 419, the group output of the selection of square about the root 419 is connected to the first group input of the third multiplier 413, the second group input of which is the fourth group input of the IPC 479 and is designed to supply a constant value k1 (where k1 is the first integer weight coefficient that determines the degree of underline of the loops), the group output of the third multiplier 413 is connected to the first group input of the fourth adder 422, the second group input of the IPC 479 is connected to the first group input of the fourth multiplier 414, the second group input of which is the fifth group input IPC house 479 and is designed to supply a constant value of k2 (where k2 is the second integer weight coefficient that determines the degree of underlining of the loops), the group output of the fourth multiplier 414 is connected to the second group input of the fourth adder 422, the group output of the fourth adder 422 is the group output of the IPC 479, wherein the first adder 420 and the second adder 421 perform a subtraction function.

The blurr compensation device operates in four modes, set by the value at the group output of the counter 100. The device operation modes are sequentially alternated from 0 to 3 for each frame received from a 10-inch ID. In the zero mode, the processed frame is output to the system bus and data is recorded from the DI 10. In the first mode, the detection and determination of the direction of motion for each pixel are performed. In the second mode, pixels with the same direction of movement are grouped into objects. In the third mode, for the detected moving objects, the calculation and correction of the brightness of the pixels is performed in order to compensate for the blurriness of the image.

In the zero mode, the input of the DI 10 receives the input signal CLK / 3. From the group output of the DI 10 to the first group input of the controller 1, the pixel brightness of the current image frame is sequentially transmitted.

Controller 1 operates in three modes, which are alternately sequentially from 2 to 0 for each pixel, and provides: in mode 2 — data output from the first RAM 5 to the system bus, in mode 1 — rewriting the frame from the first RAM 5 to the second RAM 6 , in mode 0 - recording data from the image sensor into the first RAM 5. In all modes of the controller 1, the data of the first RAM 5 and the second RAM 6 are processed at the address generated on the second group output of the controller 1.

In mode 2, the controller 1 reads the pixel brightness value from the first RAM 5 and issues it to the system bus. To do this, the controller 1 at its second group output generates an address value and transfers it to the first group input of the first multiplexer 51, from the group output of which it goes to the group input of the first RAM 5. At this address, the pixel brightness value of the current frame from the group input-output of the first RAM 5 is read and fed to the first group input of the first demultiplexer 56, from the first group output of which it is transmitted to the fourth group input of the controller 1 and then comes from the third group output scooter 1 on the system bus.

Then, in mode 1, controller 1 writes the pixel brightness value read from the first RAM 5 to the second RAM 6. The pixel brightness value is read at the previously generated address and transmitted from the group input-output of the first RAM 5 to the first group input of the first demultiplexer 56, from the output of which it arrives at the fourth group input of controller 1. From the fourth group output of controller 1, the pixel brightness value is fed to the first group input of the sixth multiplexer 57, from the group output of which it arrives at group of input-output of the second RAM 6.

Then, in mode 0, controller 1 records the brightness value of the current pixel received from DI 10 in the first RAM 5. For this, the pixel address value previously generated at the second group output of controller 1 is supplied to the first group input of the first multiplexer 51 and then from the group output of the first multiplexer 51 to the group input of the first RAM 5. From the first group output of the controller 1, the brightness value of the current pixel goes to the group input of the fifth multiplexer 55, from the group output of which the brightness value is current of the first pixel is transferred to the input-output of the first RAM 5. Reading / writing data from the first RAM 5 and the second RAM 6 for all operating modes of the device is performed similarly to the zero mode.

The second and third group inputs of controller 1 receive the constants (X-1) and (Y-1), respectively.

At the first output of controller 1, a signal is generated that determines the operation mode of the first RAM 5: reading or writing data. For this, the signal from the first output of the controller 1 is fed to the first input of the second multiplexer 52, from the output of which it is transmitted to the input of the first RAM 5. At the second output of the controller 1, a signal is generated that determines the operation mode of the second RAM 6: reading or writing data. To do this, the signal from the second output of the controller 1 is fed to the first input of the fourth multiplexer 54, from the output of which it is transmitted to the input of the second RAM 6.

The signal at the third output of the controller 1, which enters the first input of the OR element 101 and then from its output to the input of the counter 100, increments the value at the group output of the counter 100 and switches the operating mode of the device from zero to the first. From the group output of the counter 100, the signal goes to the first group input of the first comparator 102, the constant 0 is applied to the second group input of the first comparator 102. From the output of the first comparator 102, the signal is fed to the third input of controller 1. At a single value of this signal, the controller 1 is reset and disabled, at zero value of this signal, the controller is enabled.

The operating mode number of the device from the group output of the counter 100 goes to the fourth group input of the first multiplexer 51, the group input of the second multiplexer 52, the third group input of the third multiplexer 53, the group input of the fourth multiplexer 54, the third group input of the fifth multiplexer 55 and the second group input of the sixth multiplexer 57 as well as to the second group inputs of the first demultiplexer 56 and the second demultiplexer 58.

In the first mode of operation of the device, MOD 2 detects and determines the direction of movement for each pixel.

The first and second group inputs of MOD 2 receive the constants (X-3) and (Y-3), respectively. The first input of MOD 2 receives the clock frequency CLK / 25.

At the first group output of MOD 2, the address value of the current processed pixel is sequentially generated, which is fed to the second group inputs of the first multiplexer 51 and third multiplexer 53, from the group outputs of which it then goes to the group inputs of RAM 5 and RAM 6, respectively. The fourth group input MOD 2 from the second group output of the first demultiplexer 56 receives the brightness value of the pixel of the current frame, the input of which this value was received from the group input-output of RAM 5. The third group input MOD 2 from the second group output of the second demultiplexer 58 receives the brightness value pixel of the previous frame, the input of which this value came from the group input-output of RAM 6.

The fifth group input of MOD 2 from the group output of the counter 100 is the number of the operating mode of the device. In the first mode of operation of the device, a zero signal is generated at the second output of MOD 2, and in the remaining modes of operation of the device, a single signal is supplied to the input of the seventh multiplexer 59. From the second group output of MOD 2, the value of the current pixel address is supplied to the second group input of the seventh multiplexer 59 which from the group output of the seventh multiplexer 59 is transmitted to the group input of the third RAM 7. The direction of movement is received to the group input-output of the third RAM 7 from the third group output of MOD 2 Live pixel at which a unit value to output the third MOD 2 supplied to the third input of the RAM 7, is written in this RAM. Upon completion of the processing of the last pixel of the frame, a single signal is generated at the first output of MOD 2, which arrives at the second input of the OR element 101 and transfers the device to the next (second) mode of operation.

In the third mode of operation of the device, MOO 3 sequentially analyzes the direction of movement of each pixel and groups pixels with the same direction of movement into objects.

The second and third group inputs of MOO 3 receive the constants (X-2) and (Y-2), respectively. The first input of MOO 3 receives the clock frequency CLKX. The second input MOO 3 receives the clock frequency CLKX6. The third input of MOO 3 receives the clock frequency CLKY.

The sixth group input MOO 3 from the group output of the counter 100 receives the number of the operating mode of the device. From the first group output of MOO 3, the value of the address of the current analyzed pixel goes to the first group input of the seventh multiplexer 59 and then from its output to the group input of the third RAM 7. From the group input-output of the third RAM 7, the value of the direction of movement of the current pixel goes to the first group input of MOO 3. Upon completion of the processing of the last pixel of the frame, a single signal is generated at the output of MOO 3; input MK 4 and providing a record of the value of the number of objects formed on the second group output MOO 3 and fed to the first group input MK 4.

In the fourth mode of operation of the MK 4 device, sequentially for all the generated MOO 3 objects, it determines the number of pixels that make up the object, calculates the adjusted values of the brightness of the pixels of moving objects and writes the adjusted values of the brightness of the pixels in the first RAM 5.

The CLKW clock frequency arrives at the first input of MK 4, the CLKZ clock frequency at the second input of MK 4.

In the process of its work, MK 4 at the first group output generates the address value at which the number of pixels of the current analyzed object is recorded in MPO 3 and feeds it to the fourth group input of MPO 3. At the fourth group output of MK 4, the address value is formed from which the MPO 3, the coordinates of the current processed pixel are read, and fed to the fifth group input of MOO 3. From the third group output of MOO 3 to the second group input of MK 4 the number of points of the current analyzed object is received. From the fourth group output MOO 3 to the third group input MK 4 receives the coordinates of the current pixel of the current analyzed object.

The fifth group input MK 4 receives data (brightness of pixels of the corrected area) from the fourth group output of the first demultiplexer 56, read from the group input-output of the first RAM 5 at the address generated on the second group output of MK 4 and applied to the fourth group input of the first multiplexer 51 , from the output of which it is transmitted to the group input of the first RAM 5, and filed to the first group input of the first demultiplexer 56.

In the process, MK 4 at its second group output generates an address value that defines the coordinates of the pixel with the adjusted brightness value, and feeds it to the fourth group input of the first multiplexer 51, from the group output of which this address value goes to the group input of the first RAM 5. On the third group output MK 4 is formed by the adjusted value of the brightness of the pixel, which is fed to the fourth group input of the fifth multiplexer 55, from the group output of which it is fed to the group input The first RAM 5 is written to it.

The fourth group input MK 4 is supplied with a threshold value that determines the minimum number of pixels in the object. At the output of MK 4, a single signal is generated, which arrives at the fourth input of the OR element 101 and puts the device into zero operation mode.

Controller 1 operates as follows. At the first input of the first counter 13, which determines the x coordinate of the current pixel being processed, a clock signal CLK / 3 is received, according to which the value at the group output of the first counter 13 is increased by one and fed to the first group input of the first comparator 16. At the second group input of the first comparator 16 a constant (X-1) is supplied, where X is the horizontal frame size. From the output of the first comparator 16, the signal is supplied to the second input of the first element OR 11, the output of which is fed to the second input of the first counter 13. At a single value of this signal, the first counter 13 is reset. At the same time, the signal from the output of the first comparator 16 is fed to the first input the second counter 14, which determines the coordinate of the current processed pixel, from the output of which the signal is fed to the first group input of the second comparator 17, the second group input of which is supplied with a constant (Y-1), where Y is the size frame vertically. From the output of the second comparator 17, the signal is fed to the second input of the second OR element 12 and to the first input of the first OR element 11. From the output of the second OR element 12, the signal is fed to the second input of the second counter 14. At a single value of this signal, the second counter is reset 14. Thus Thus, sequential enumeration of coordinates (x, y) of pixels is provided, where x∈ [0, X-1], y∈ [0, Y-1].

From the group output of the first counter 13 and the group output of the second counter 14, the coordinates (x, y) of the current pixel are received respectively at the first and second group inputs of the address generator 18, whose group output on which the value of the address of the current pixel is generated is the second group output of the controller 1 .

The third counter 15, designed to set the current operating mode of the controller, provides the formation of values from 0 to 2 on its two-bit group output. The CLK clock signal is supplied to the first input of the third counter 15, which provides an increment of the value at the counter output. From the group output of the third counter 15, the signal is supplied to the second group input of the buffer 110, to the first group input of which a signal from the image sensor 10 is supplied. If the value 0 is used at the second group input of the buffer 110, the signal from DI 10 is transmitted to the group output of the buffer 110, which is the first group output of the controller 1. With other values at the second group input of the buffer 110, its group output is in the third high-impedance state.

From the output of the first comparator 16, from the output of the second comparator 17 and the senior discharge of the group output of the third counter 15, the signals are fed to the first, second and third inputs of the element And 19, the output of which the signal is fed to the third output of the controller 1 and means the completion of 0 operation mode of the compensation device motion blur.

From the group output of the third counter 15, the signal is supplied to the second group input of the demultiplexer 111, the first group input of which is the fourth group input of the controller 1. At a value of 0 at the second group input of the demultiplexer 111, the signal is transmitted from its first group input to its first group output, which is the third group output of the controller 1. With a value of 1 at the second group input of the demultiplexer 111, it is possible to connect its first group input to its second group output , which is the fourth group output of the controller 1.

The third input of the first element OR 11, the first input of the second element OR 12 and the second input of the third counter 15 receives a signal, a unit value of which blocks the operation of the controller 1.

The signal from the second output of the controller 1 is used to control the read / write mode of the second RAM 6.

The motion detection module 2 operates as follows. The first input of the first counter 21 receives a clock signal CLK / 25, along which the first counter 21 increments its value. From the group output of the first counter 21, the x coordinate of the current pixel being processed is fed to the first group input of the first adder 27 and the first group input of the first comparator 25, to the second group input of which the value (X-3) is received. If the values coincide on both of their group inputs, the first comparator 25 supplies a signal to the second input of the OR element 210, from the output of which the signal goes to the second input of the first counter 21 and resets the first counter 21 to zero. At the same time, from the output of the first comparator 25, the signal enters the first input of the second counter 22, from the group output of which the signal enters the first group input of the second comparator 26, the second group input of which supplies the value (Y-3). When the values coincide on both of their group inputs, the second comparator 26 generates a single signal supplied to the second input of the second counter 22 and the first input of the OR element 210 and then from its output to the second input of the first counter 21, thereby resetting the first counter 21 and the second counter 22 to zero state. Thus, at the group output of the first counter 21, the x coordinate of the current processed pixel is successively formed, taking values from 0 to (X-3); at the output of the second counter 22, a coordinate is formed sequentially at the current processed pixel, taking values from 0 values to (Y-3).

At the input of the third counter 23, a clock signal CLK is received, at the group output of the third counter 23, values i from 0 to 4 inclusive are generated sequentially, which are transmitted to the second group input of the first adder 27. When the third counter 23 is overflowed, a signal is generated at its second output the input of the fourth counter 24 and incrementing its output value. From the group output of the fourth counter 24, the values of j from 0 to 4 inclusively arrive at the second group input of the second adder 28. From the group outputs of the first counter 21 and the second counter 22, the x and y values go to the first group inputs of the first adder 27 and the second adder 28. On group outputs of the first adder 27 and the second adder 28 are formed values that define the coordinates (x + i, y + j) of the current pixel, which are fed to the first and second group inputs of the first address generator 29. The first address generator 29 produces at its output group addresses A formation according to the formula A = (x + i) + (y + j) * X, and delivers the address A for the first group output MOD 2.

The first group input of the first register block 212 from the fourth group input of MOD 2 receives the brightness value of the current pixel of the current frame. The first group inputs of the second register block 213, the third register block 214, the fourth register block 215, the fifth register block 216, the sixth register block 217, the seventh register block 218, the eighth register block 219, the ninth register block 220, the tenth register block 221 from the third group input MOD 2 receives the brightness value of the current pixel of the previous frame. The second group inputs of the first register block 212, the second register block 213, the third register block 214, the fourth register block 215, the fifth register block 216, the sixth register block 217, the seventh register block 218, the eighth register block 219, the ninth register block 220, tenth register block 221 receives the values of j from the group output of the fourth counter 24. At the third group inputs of the first register block 212, the second register block 213, the third register block 214, the fourth register block 215, the register unit 216 of the fifth, sixth register unit 217, the register unit 218 of the seventh, eighth register unit 219, the register unit 220 of the ninth, tenth register unit 221 receives the values of i from the group output of the third counter 23.

At the group output of the first register block 212, matrix elements B (k) are formed in accordance with formula (1) and are fed to the first group inputs of the first summing block 222, the second summing block 223, the third summing block 224, the fourth summing block 225, and the fifth summing block 226, a sixth summing block 227, a seventh summing block 228, an eighth summing block 229, a ninth summing block 230.

At the group outputs of the second register block 213, the third register block 214, the fourth register block 215, the fifth register block 216, the sixth register block 217, the seventh register block 218, the eighth register block 219, the ninth register block 220, the tenth register block 221, matrix elements are formed B ^* (k) for each of eight directions of movement in accordance with formula (2) and fed to the second inputs of the first group of the summing unit 222, a second summing block 223, a third summing unit 224, chetvertog Adder block 225, the summing unit 226 of the fifth, sixth summing junction 227, summing unit 228 of the seventh, eighth summing unit 229, the ninth summing block 230.

At the group outputs of the first summing block 222, the second summing block 223, the third summing block 224, the fourth summing block 225, the fifth summing block 226, the sixth summing block 227, the seventh summing block 228, the eighth summing block 229, the ninth summing block 230, matrix elements are formed B ^* (k-1) in accordance with formula (3).

The value from the group output of the fifth summing block 226 is fed to the first group input of the eleventh comparator 241, the second group input of which is supplied with a threshold value, when compared with which the fact of the presence of movement of the current pixel of the current frame is determined. From the output of the eleventh comparator 241, the signal is supplied to the third output of MOD 2.

The values from the group outputs of the first summing block 222, the second summing block 223, the third summing block 224, the fourth summing block 225, the sixth summing block 227, the seventh summing block 228, the eighth summing block 229, and the ninth summing block 230 go to the corresponding group inputs of the determining block minimum 231 and to the first group inputs of the third comparator 233, fourth comparator 234, fifth comparator 235, sixth comparator 236, seventh comparator 237, eighth comparator 238, ninth comp a radiator 239, a tenth comparator 240. The second group inputs of the third comparator 233, the fourth comparator 234, the fifth comparator 235, the sixth comparator 236, the seventh comparator 237, the eighth comparator 238, the ninth comparator 239, and the tenth comparator 240 receive the value from the group output of the minimum determination unit 231.

Thus, at the outputs of the third comparator 233, fourth comparator 234, fifth comparator 235, sixth comparator 236, seventh comparator 237, eighth comparator 238, ninth comparator 239, tenth comparator 240. At the second group inputs of the third comparator 233, fourth comparator 234, fifth comparator 235, sixth comparator 236, seventh comparator 237, eighth comparator 238, ninth comparator 239, tenth comparator 240 in the “1 of N” code, the directions of movement of the current pixel of the current frame are generated, which are fed to g group input of encoder 242. At the output of encoder 242, which is the third group output of MOD 2, the values of the directions of movements in binary code are generated.

From the group output of the first counter 21, the x coordinate of the current pixel goes to the first group input of the fourth adder 245. From the group output of the second counter 22, the coordinate of the current pixel goes to the first group input of the third adder 244. To the second group inputs of the third adder 244 and the fourth adder 245, and also the second group input of the twelfth comparator 247 receives a constant 2. From the group outputs of the third adder 244 and the fourth adder 245, the coordinates of the current pixel (x + 2, y + 2) go to the first the second and second group inputs of the second shaper address 246, the group output of which is the second group output MOD 2.

From the output of the first comparator 25 and from the output of the second comparator 26, the signals are fed to the first and second inputs of the element And 211, the output of which the signal is fed to the first output of MOD 2. This signal increments the mode value of the image blur compensation device.

Each of the register blocks 212-221 operates as follows. From the second group input of the register block, the value of i comes from the first group inputs of the first comparator 81, second comparator 82, third comparator 83, fourth comparator 84, fifth comparator 85, sixth comparator 86, seventh comparator 87, eighth comparator 88, and ninth comparator 89 the third group input of the register block to the third group inputs of the first comparator 81, the second comparator 82, the third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87 , the eighth comparator 88, the ninth comparator 89, the third input of the register unit is connected to the third input of the first comparator 81, the second comparator 82, the third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87, the eighth comparator 88, the ninth comparator 89 receives the value of j. The values i, j determine the coordinates of the current pixel of the current 3 × 3 processing window. The coordinates of the points of the current processing window, defined by the first constant 851, the second constant 852, the third constant 854, the fourth constant 854, the sixth constant 855, the seventh constant 857, the eighth constant 858, the ninth constant 859, the tenth constant 861, 861, one , twelfth constant 862, thirteenth constant 863, fourteenth constant 864, fifteenth constant 865, sixteenth constant 866, seventeenth constant 867, eighteenth constant 868, are fed to the second and fourth group inputs first comparator 81, second comparator 82, third comparator 83, fourth comparator 84, fifth comparator 85, sixth comparator 86, seventh comparator 87, eighth comparator 88, ninth comparator 89. At the outputs of the first comparator 81, second comparator 82, third comparator 83, the fourth comparator 84, the fifth comparator 85, the sixth comparator 86, the seventh comparator 87, the eighth comparator 88, the ninth comparator 89 are formed logical units with the same values on their first, second group inputs and third, fourth volume group inputs, respectively, and enter the inputs of the first register 810, second register 811, third register 812, fourth register 813, fifth register 814, sixth register 815, seventh register 816, eighth register 817, ninth register 818, outputs of the first register 810, second register 811, third register 812, fourth register 813, sixth register 815, seventh register 816, eighth register 817, ninth register 818. From the first group input of the register block to the group inputs of the first register 810, second register 811, third register and 812, the fourth register 813, the fifth register 814, a sixth register 815, the seventh register 816, an eighth register 817, the ninth register 818 receives the brightness value of the current pixel. Registers are designed to store the brightness of the pixels of the processing window 3 × 3. From the group output of the fifth register 814, the brightness value of the central pixel is supplied to the second group inputs of the first adder 819, second adder 820, third adder 821, fourth adder 822, fifth adder 823, sixth adder 824, seventh adder 825, eighth adder 826. From group outputs the first register 810, the second register 811, the third register 812, the fourth register 813, the sixth register 815, the seventh register 816, the eighth register 817, the ninth register 818 the brightness of the peripheral pixels of the processing window 3 × 3 steps t the first inputs of the first adder group 819, second adder 820, a third adder 821, a fourth adder 822, the sixth adder 824, the adder 825 of the seventh, eighth adder 826 whose outputs are the outputs of the register group unit. Adders provide the subtraction of the value received at the second group input from the value received at the first group input. Thus, at the output of the register block, the matrix B ^* (k) is determined, which is determined by formula (2).

Each of the summing blocks 222 ÷ 230 operates as follows. The values received at the first group inputs of the first adder 91, the second adder 92, the third adder 93, the fourth adder 94, the fifth adder 95, the sixth adder 96, the seventh adder 97, the eighth adder 98 are subtracted from the values received at the second group inputs of the same adders respectively. The differences obtained from the group outputs of the first adder 91, the second adder 92, the third adder 93, the fourth adder 94, the fifth adder 95, the sixth adder 96, the seventh adder 97, and the eighth adder 98 go to the corresponding group inputs of the ninth adder 99, at the output of which the value , which determines the amount of displacement in each of 8 directions in accordance with formula (4).

The MOO 3 object definition module 3 is designed to determine objects described by the set of coordinates of its pixels in accordance with formula (14). For this, MOO 3 performs a sequential analysis of the signs of the direction of movement of each pixel, in the case of movement, searches adjacent to the current pixels having the same direction of movement and determines the number of pixels of each object.

MOO 3 works as follows. At the first input of the first element And 38, which is the first input MOOZ, receives a clock signal CLKX. A signal is received at the second input of the first And 38 element from the output of the first trigger 37, allowing the clock signal CLKX to pass from the output of the first And 38 element to the first input of the first counter 31. At the group output, the first counter 31 generates a value that determines the x coordinate of the current processed pixel, which arrives at the first group input of the first address shaper 320 and at the first group input of the first comparator 315. From the second group input MOO 3 the value (X-2) is supplied to the second group input of the first comparator 315. If the values coincide on both of their group inputs, the first comparator 315 supplies a signal to the second input of the OR element 39, from the output of which the signal goes to the second input of the first counter 31 and resets the first counter 31 to zero. At the same time, from the output of the first comparator 315, the signal enters the first input of the second counter 32, from the group output of which the signal enters the first group input of the second comparator 316, the second group input of which supplies the value (Y-2). When the values coincide, the second comparator 316 generates a single signal supplied to the second input of the second counter 32 and the first input of the OR element 39 and then from its output to the second input of the first counter 31, thereby resetting the first counter 31 and the second counter 32 to zero. Thus, at the group output of the first counter 31, the x coordinate of the current processed pixel is successively generated, taking values from 1 to (X-2); at the output of the second counter 32, a coordinate is formed sequentially at the current processed pixel, taking values from 1 value to (Y-2).

At the second group input of the first shaper address 320, the value Y is received from the group output of the second counter 32. At the output of the first shaper address 320, the address of the current pixel is generated and goes to the first group input of the first multiplexer 322.

From the output of the first comparator 315 and from the output of the second comparator 316, the signals are fed to the first and second inputs of the And 321 element, the output of which the signal is fed to the first output of MOO 3. This signal increments the mode value of the image blur compensation device.

From the output of the first trigger 37, the signal through the first inverter 323 is fed to the input of the first multiplexer 322 and to the input of the first register 324. The group input of the first register 324 receives the value of the index of the direction of movement of the current pixel and is stored at this input at a unit level and is output to group output of the first register 324. The group input of the first register 324 is the first group input of MOO 3. From the group output of the first register 324 the value of the index of the direction of movement of the current pixel goes to the first the group input of the third comparator 325, to the second group input of which a constant 0 is applied. From the output of the third comparator 325, which is an inverse output, the signal goes to the first input of the third element And 327. From the output of the fourth comparator 328, which is an inverse output, to the second input of the third element And 327, a signal is received notifying that the current pixel has already been processed / not processed. At the first input of the fourth comparator 328, from the input / output of the RAM 71, a pixel processing flag is received, and a constant 1 is supplied to its second input. From the output of the third element And 327, a signal whose single state prohibits the transition to processing the next pixel is sent to the first input of the first trigger 37, resetting this trigger to zero.

When the output state of the third AND 327 element is zero, the first counter 31 and the second counter 32 generate control signals at their outputs for processing the next pixel, and when the output state of the third And 327 element is single, the pixel is searched for whose properties satisfy the condition from formula (14). To do this, the input of the third counter 33 receives the signal CLKX6, incrementing the counter value, the output of which values i from 0 to 2 are generated. From the output of the third counter 33, the signal goes to the input of the fourth counter 34, incrementing the counter value, the output of which values j from 0 to 1. From the output of the third counter 33, the signal also enters the first group input of the first adder 310, the constant 1 is supplied to the second group input of which (i-1) is generated at the group output of the first adder 310. The values (i-1, j) determine the coordinates of the current analyzed point in the vicinity of the point (x, y) (figure 1).

From the group output of the first adder 310, information is supplied to the first group input of the second adder 311, the auxiliary group 1 from the group output of the fifth counter 35 is supplied to the second group input. The x value from the group output of the first counter 31 is received to the third group input of the second adder 31. C the group output of the fourth counter 34, the values of j go to the first group input of the third adder 312, the second group input of which is supplied with an auxiliary variable m from the group output of the sixth counter 36. The third group input of the third adder 312 receives the value of y from the group output of the second counter 32. At the group outputs of the second adder 311 and the third adder 312, the values (x + i + 1) and (y + j + m) are formed, which determine pixel coordinates used when reading data from RAM 70 and writing pixel processing attributes to RAM 71. From the group output of the third counter 33 to the first group inputs of the fifth comparator 331, sixth comparator 332, seventh comparator 333, eighth comparator 334, ninth comparator 335, tenth to comparator 336 receives the value of i. The third group inputs of the fifth comparator 331, the sixth comparator 332, the seventh comparator 333, the eighth comparator 334, the ninth comparator 335, and the tenth comparator 336 receive the value j. The second group input and the fourth group input of the fifth comparator 331 are supplied with a constant 0. The second group input and the fourth group input of the sixth comparator 332 are supplied with the constant 1 and the constant 0. The second group input and the fourth group input of the seventh comparator 333 are respectively fed constant 2 and constant 0. To the second group input and to the fourth group input of the eighth comparator 334, respectively, constant 0 and constant 1. are fed to the second group input and to the fourth group input of girls of this comparator 335, a constant 1 is supplied. A constant 2 and a constant 1 are supplied to the second group input and the fourth group input of the tenth comparator 336, respectively. Thus, the outputs of the fifth comparator 331, sixth comparator 332, seventh comparator 333, eighth comparator 334, ninth comparator 335, of the tenth comparator 336, a single signal is generated that allows data recording and is connected to the inputs of the second register 337, third register 338, fourth register 339, fifth register 340, sixth register 341, seventh register 3 42, respectively, at the first group inputs of which a code for the direction of movement of the pixel is supplied. Thus, after reading a region of 6 pixels defined by the coordinates (i, j) (relative to the coordinates of the current pixel (x, y)), at the group outputs of the second register 337, third register 338, fourth register 339, fifth register 340, sixth register 341, of the seventh register 342, codes of the directions of movement of pixels of the current analyzed subregion are recorded, which are fed to the first group inputs of the eleventh comparator 343, twelfth comparator 344, thirteenth comparator 345, fourteenth comparator 346, fifteenth compara torus, 347 and sixteenth comparator 348, to the second group inputs of which the value of the code of the direction of movement of the current pixel (x, y) is supplied. From the output of the eleventh comparator 343, the signal is fed to the first input of the fourth element And 361 and to the third input of the ninth element And 366. From the output of the twelfth comparator 344, the signal is fed to the first input of the fifth element And 362, to the second input of the fourth element And 361, to the first input of the sixth element And 363, to the second input of the seventh element And 364, to the first input of the eighth element And 365 and to the first input of the ninth element And 366. From the output of the thirteenth comparator 345, the signal is fed to the second input of the fifth element And 362 and the fifth input of the ninth element And 366. From exit fourteen comparator 346, the signal is supplied to the first input of the seventh element And 364 and the sixth input of the ninth element And 366. From the output of the fifteenth comparator 347, the signal is fed to the second input of the eighth element And 365 and the fourth input of the ninth element And 366. From the output of the sixteenth comparator 348, the signal is fed to the second input of the sixth element And 363 and the second input of the ninth element And 366. From the output of the fifth element And 362, the signal goes to the third input of the sixth element And 363. From the output of the sixth element And 363, the signal goes to the third input of the eighth element And 365. From the output of the eighth element And 365, the signal goes to the third input of the seventh element And 364. From the output of the seventh element And 362 the signal goes to the third input of the fourth element And 361. The outputs of the fourth element And 361, the fifth element And 362, the sixth element And 363, the seventh element And 364, the eighth element And 365, the ninth element And 366 are connected respectively to the first inputs of the eighth register 367, the ninth register 368, the tenth register 369, the eleventh register 370, the twelfth register 371, the thirteenth register 372, the second inputs of which receive a signal the output of the tenth comparator 336, which provides data recording in registers, to whose third inputs the signal from the output of the fifth comparator 331, cleans the contents of these registers. Thus, at the outputs of the eighth register 367, ninth register 368, tenth register 369, eleventh register 370, twelfth register 371, thirteenth register 372, the result of checking conditions (8) - (12), respectively, is generated.

Depending on conditions (8) - (11), the fifth counter 35 is incremented / decremented or the sixth counter 36 is incremented, and when condition (12) is fulfilled, it proceeds to check whether this group of pixels is an object. To do this, from the output of the eighth register 367, the signal is supplied to the second input of the fifth OR element 376 and to the first input of the second OR element 373; from the output of the ninth register 368, the signal is supplied to the first input of the third OR element 374 and to the second input of the second OR element 373; the output of the tenth register 369, the signal is supplied to the first input of the fourth element OR 375 and to the third input of the second element OR 373; the output of the eleventh register 370, the signal is supplied to the first input of the fifth element OR 376 and to the fourth input of the second element OR 373; the output of the twelfth register 371, the signal is fed to the third input of the fourth OR element 375 and to the fifth input of the second OR element 373. As a result, at the output of the second OR element 373, when the next pixel belonging to this object is found, a single signal value is generated, which is fed to the first input of the seventh counter 377, which stores the number of points of the current object, and the first input of the eighth counter 378, which stores the total number of points in all found objects. From the output of the third OR element 374, a signal notifying the need to increase the pixel abscissa (x + i + 1, y + j + m) by 1 is fed to the first input of the fifth counter 35. From the output of the fourth OR element 375, a signal notifying the need to increase pixel ordinates (x + i + 1, y + j + m) by 1, is fed to the first input of the sixth counter 36. From the output of the fifth element OR 376, a signal notifying the need to reduce the pixel abscissa (x + i + 1, y + j + m) by 1, is fed to the second input of the fifth counter 35. The fifth counter 35 and the sixth counter 36 are reset to zero by feeding n their third and second inputs, respectively, from the output signal of the NOR 323.

The first input of the ninth counter 379 receives a clock signal CLKY. From the group output of the seventh counter 377, the value of the number of points in the current object goes to the group input of the fourteenth register 380. From the output of the thirteenth register 372, the signal goes to the second input of the ninth counter 379, the first input of the tenth element And 381 and the first input of the tenth counter 382. To the second input of the tenth element And 381, a signal is supplied from the first output of the ninth counter 379. The signal from the output of the tenth element And 381 to the input of the fourteenth register 380 allows data to be written to the register. From the group output of the fourteenth register 380, the signal is fed to the group input of the buffer element 383, from the output of which it is fed to the group input-output of the second RAM 72. From the group output of the tenth counter 382, the current object number is fed to the first group input of the second multiplexer 384, from the group output which he arrives at the group input of RAM 72. Thus, in RAM 72 is recorded the number of pixels of the current object. From the first and second outputs of the ninth counter 379, the signals are fed to the first and second inputs of the eleventh element And 385, the output of which the signal is then sent to the second input of the twelfth element And 386. From the output of the twelfth element And 386, a signal allowing / disabling data recording in the second RAM 72, is fed to the second input of the second RAM 72.

The first group input of the fourth adder 313 receives the value 1 from the group output of the fifth counter 35; the second input of the fourth adder 313 receives the value of x from the group output of the first counter 31. The first group input of the fifth adder 314 receives the value of y from the group output of the second counter 32; the second input of the fifth adder 314 receives the value m from the group output of the sixth counter 36. From the group outputs of the fourth adder 314 and the fifth adder 315, the pixel coordinates (x +, y + m) are sent to the first and second group inputs of the data converter 319, combining the two bytes of data per word. From the output of the data converter 319, the data goes to the group input of the second buffer 387, from the output of which the coordinates of the current pixel go to the group input-output of the third RAM 73. The address of the recording coordinates of the current pixel is the current value of the total number of all points of the objects supplied from the group output of the eighth counter 378 to the first group input of the third multiplexer 388, from the output of which it goes to the group input of the third RAM 73. The value x s comes to the first group input of the seventeenth comparator 379 the group output of the first counter 31. The second group input of the seventeenth comparator 379 receives the value of y from the group output of the second counter 32. The constant 0 is supplied to the third input of the seventeenth comparator 379. A single signal is generated at the output of the seventeenth comparator 379 when the values at all its inputs match and feed to the second input of the eighth counter 378 and the second input of the tenth counter 382, resetting these counters to zero.

Writing to the first RAM 71 is performed for each processed pixel. To do this, from the output of the element NOT the signal goes to the input of the first RAM 71 and allows data to be written to the first RAM 71. Next, the same signal goes to the first and second inputs of the third buffer element 391, from the output of which a signal having a unit value is fed to the input / the output of the first RAM 71. As a result, a constant 1 corresponding to the pixel processing attribute is written to the RAM 71 at the corresponding address generated by the second address generator 318.

The enabling signal for writing data to the second RAM 72 and the third RAM 73 is the signal generated at the output of the eighteenth comparator 392, the first group input of which from the sixth group input MOO 3 receives the value of the operating mode number of the entire device, and the second input - constant 2.

Correction module 4 operates as follows. From the first group input MK 4 to the group input of the first register 453, the x coordinate values of the current processed pixel are received. From the second group input MK 4 the first group input of the second comparator 456 receives the coordinate values of the current processed pixel.

From the third input of MK 4, the signal enters the input of the first register 453. From the third group input of MK 4, the value of the number of objects detected in the frame is sent to the group input of the first register 453. Thus, the first register 453 stores the value of the number of objects detected in the frame, which is supplied from its group output to the first group input of the first comparator 454. The number of the next processed object is fed to the second group input of the first comparator 454 from the group output of the first counter 455. From the output of the first comparator 454, a signal that takes a single value at the end of processing all the objects goes to the second input of the first counter 455 and to the first output of MK 4. At the same time, from the group output of the first counter 455, the number of the current object goes to the first group output of MK 4. The third group input MK 4 receives the value of the number of pixels of the current object, which is fed to the first group input of the second comparator 456, the second group input of which from the fourth group input MK 4 receives a threshold an entity that defines the minimum allowable number of pixels in an object at which it is not considered an interference. At the output of the second comparator 456, in case of exceeding the threshold, a unit value is formed, which is fed to the input of the pulse generator 457 and allows its operation. This value from the output of the second comparator 456 is also fed to the first input of the first trigger 461 and resets it to zero. The group input of the pulse generator 457 from the third group input MK 4 receives the number of pixels of the current object. The pulse generator 457 generates at its output a number of pulses that match the number of pixels of the current object. From the output of the pulse generator 457, the pulses are fed to the first input of the second element And 458, the output of which pulses are fed to the first input of the second counter 459. At the group output of the second counter 459, the number of the current pixel of the current processed object is generated, which goes to the second group input of the third comparator 460 , the first group input of which from the third group input MK 4 serves the total number of points of the current object. Upon completion of the processing of all the pixels of the current object, a single signal is generated at the output of the third comparator 460, which arrives at the second input of the first trigger 461 and sets it to a single state. At the output of the first trigger 461, a single signal is generated, applied to the second input of the first element And 462 and allowing the passage of signals from its first input connected to the first input of MK 4. As a result, the output of the first element And 462 generates a pulse applied to the first input of the third counter 465 and increasing the value of the number of objects per unit. The signal from the first input of MK 4 is also fed to the first input of the third element And 483, the second input of which receives a signal from the output of the second trigger 466. From the output of the third element And 483, the signal is fed to the second input of the second element And 458.

From the output of the third comparator 460, the signal also goes to the second input of the second counter 459 and at a single value of the signal resets the second counter 459 to the zero state. From the second input MK 4 at the first input of the third counter 465 receives a clock signal CLKZ. A signal is received at the second input of the third counter 465 from the output of the second comparator 456, allowing the increment of the third counter 465. The third counter 465 determines the number of the correction step and takes a value from 0 to 4.

The number of the current stage of correction from the group output of the third counter 465 goes to the group input of the fourth comparator 463, which takes a single state when the mode number is zero. The signal from the output of the fourth comparator 463 is fed to the first input of the second trigger 466, which this signal is converted to the zero state, thereby prohibiting the processing of the current pixel of the current object. Also, this signal is fed to the input of the second register 467, to the group input of which the brightness value of the current pixel is supplied from the fifth group input of module MK 4. The same value goes to the group inputs of the third register 468 and the fourth register 469. To determine the address of the current pixel, the value of the mode number from the group output of the third counter 465 goes to the ninth group input of the multiplexer 470. From the sixth group input MK 4, the signal goes to the group input of the data converter 471, which performs the function of splitting a word into 2 bytes, from the first group output of which the x coordinate is supplied to the first, third and fourth group inputs of the multiplexer 470 and the first input of the first sum torus 472. From the second group output of the data converter 471, the coordinate y is supplied to the fifth, sixth and eighth group inputs of the multiplexer 470 and the second group input of the second adder 473. The third constant is supplied to the second group input of the first adder 472 and the first group input of the second adder 473. 474, equal to 1. From the group outputs of the first adder 472 and the second adder 473, the values (x + 1) and (y + 1) respectively enter the second and seventh group inputs of 470 multiplexer. At the first group output of 470 multiplexer values corresponding to the values at the first, second, third or fourth of its group inputs are generated, at the second group output of the multiplexer 470 values are generated corresponding to the values at its fifth, sixth, seventh or eighth group inputs and determined by the value at its ninth group input. From the first and second group outputs of the multiplexer 470, the pixel coordinates are sent to the first and second input of the address shaper 475, respectively, at the output of which the value of the current pixel address is supplied to the second group output of MK 4. Single values are generated at the outputs of the fifth comparator 464 and sixth comparator 484 for the numbers of the correction stages 1 and 2, respectively, and go to the inputs of the third register 468 and the fourth register 469, respectively. The second group inputs of the fourth comparator 463, the fifth comparator 464, the sixth comparator 484 are supplied with constant values specified by the fourth constant 476, the fifth constant 477, and the fourth constant 478 equal to 0, 1, and 2, respectively.

Thus, at the group outputs of the second register 467, the third register 468 and the fourth register 469, upon completion of the three stages of correction, brightness values of three pixels are determined, determined by the coordinates (x, y), (x + 1, y) and (x, y + 1 ), which are supplied respectively to the first, second, and third group inputs of the underlining module 479, at the output of which a compensated pixel brightness value (x, y) is formed in accordance with formula (16), and fed to the group input of the fifth register 480. Fifth register 480 by a signal at its input by taken from the output of the seventh comparator 481, which takes a single value with a value of 3 at the group output of the third counter 462, fed to the first group input of the seventh comparator 481, whose second input has a value of the fifth constant 482, equal to 3, records information on its group input and data output to the third group output MK 4. At the same time, from the output of the seventh comparator 481, the signal is fed to the second input of the second trigger 466, which translates this trigger into a single state and allows processing as follows th pixel of the current object.

The module underline contours (IPC) 479 operates as follows. From the first group input of the IPC 479, the pixel brightness (x + 1, y) is supplied to the first group input of the first adder 420. From the second group input of the IPC 479, the brightness of the pixel (x, y) is supplied to the second group input of the first adder 420 and the first group input of the second adder 421. From the third group input of the IPC 479, the pixel brightness (x, y + 1) is supplied to the second group input of the second adder 421. The first adder 420 at its group output generates a value equal to the difference in values at its first and second group inputs. The second adder 421 at its group output generates a value equal to the difference in values at its second and first group inputs. From the group output of the first adder 420, the value goes to the first and second group inputs of the first multiplier 411. From the group output of the second adder 421, the value goes to the first and second group inputs of the first multiplier 412. From the group outputs of the first multiplier 411 and the second multiplier 412, the values go to the first and the second group inputs of the third adder 417, from the output of which the value is supplied to the input of the square root selection module 419. Thus, blocks 420, 421, 411, 412, 417, 419 determine the gradient value in sponds to the formula (17). From the group output of the square root selection module 419, the value is supplied to the first group input of the third multiplier 413, to the second group input of which from the fourth group input of the IPC 479 a constant value k1 is determined, which determines the degree of underlining of the contour. From the group output of the third multiplier 413, the value is supplied to the first group input of the fourth adder 422, the second group input of which is supplied from the group output of the fourth multiplier 414. The pixel brightness (x, y) from the second group input of the IPC is supplied to the first group input of the fourth multiplier 414 479. At the second group input of the fourth multiplier 414 from the fifth group input of the IPC 479, a constant value k2 is determined, which determines the degree of underlining of the contour. At the group output of the fourth adder 422, a corrected pixel brightness value is generated.

All modules of the device, with the exception of the image sensor, can be implemented in a programmable logic integrated circuit of medium degree of integration, which will ensure high technical and economic performance of the device.

The repetition periods of clock signals should be related by the following relations

- signals CLK, CLK / 3, CLK / 25

T _CLK = 3 * T _{CLK / 3} ,

T _CLK = 25 * T _{CLK / 25} ,

where T _CLK , T _{CLK / 3} , T _{CLK / 25} - the repetition periods of the clock signals CLK, CLK / 3, CLK / 25, respectively;

- signals CLKX, CLKX6

T _CLKX = 6 * 7 _CLKX6 ,

where T _CLKX , T _CLKX are the repetition periods of clock signals CLKX, CLKX6, respectively.

The repetition periods of clock signals CLK, CLKX, CLKY, CLKW, CLKZ are not related to each other by time constraints and are selected when implementing a device for compensating for motion blur in moving objects based on a specific element base.

The invention provides compensation for motion blur in moving objects in real time and can be used to correct image distortions in video sensors made on the basis of various types of solid-state matrix photodetectors, technical vision systems, and also in video information display means - liquid crystal displays.

Claims (2)

1. A method of compensating for motion blur of moving objects, including calculating the difference between the measured brightness of the image pixels and its previously obtained estimate based on the sequence of previous frames, detecting the movement by comparing the difference with a threshold value, characterized in that the image is additionally read, the direction of movement of each pixels, combine adjacent pixels moving in one direction into an object, underline the contours of moving objects by dix their original B (k) and gradient ▽ (B (k)) image, an output image is formed

where k ₁ , k ₂ - weighting factors. 2. The device for implementing the method according to claim 1, containing an image sensor (DI), characterized in that it contains a controller, a motion detection module (MOD), an object detection module (MOO), a correction module (MK), the first RAM , second RAM, third RAM, counter, OR element, first comparator, first multiplexer, second multiplexer, third multiplexer, fourth multiplexer, fifth multiplexer, sixth multiplexer, seventh multiplexer, first demultiplexer, second demultiplexer, and the input of the DI and the first input of the controller These are the CLK-RW clock inputs, the group output of the DI is connected to the first group input of the controller, the second group output of the controller is connected to the first group inputs of the first multiplexer and third multiplexer, the group output of the first multiplexer is connected to the group input of the first RAM, the group input-output of the first RAM is connected to the group input of the first demultiplexer and to the group output of the fifth multiplexer, the first group output of the first demultiplexer is connected to the fourth group input of the controller, gr The main input-output of the second RAM is connected to the group input of the second demultiplexer and to the group output of the sixth multiplexer, the third group output of the controller is connected to the system bus, the fourth group output of the controller is connected to the first group input of the sixth multiplexer, the first group output of the controller is connected to the first group input of the fifth multiplexer, the first output of the controller is connected to the first input of the second multiplexer, the output of the second multiplexer is connected to the input of the first RAM, the second output the controller is connected to the first input of the fourth multiplexer, the output of which is connected to the input of the second RAM, the constants (X-1) and (Y-1) respectively arrive at the second and third group inputs of the controller, the second input of the controller and the second input of the MOD are clock inputs CLK, the third controller input is connected to the output of the first comparator, the first group input of which is connected to the group output of the counter and the fifth group input of the MOD, the constant 0 is applied to the second group input of the first comparator, the third controller output is connected to the first input of the OR element, the first input of the MOD is a clock input CLK / 25, the first, second group inputs of the MOD are designed to supply constants (X-3) and (Y-3), respectively, the third group input of the MOD is connected to the group output of the second demultiplexer, the fourth group input of the MOD is connected to the second group output of the first demultiplexer, the first group output of the MOD is connected to the second group inputs of the first multiplexer and the third multiplexer, the second group output of the MOD is connected to the second group input of the seventh mult Iplexor, the third group output of the MOD is connected to the group input-output of RAM and the first group input of the MOO, the first output of the MOD is connected to the second input of the OR element, the second output of the MOD is connected to the input of the seventh multiplexer, the third output of the MOD is connected to the input of the third RAM, the second and third MOO group inputs are designed to supply constants (X-2) and (Y-2) respectively, the fourth MOO group input is connected to the first MK group output, the fifth MOO group input is connected to the fourth MK group output, the sixth MOO group input is connected it is connected to the group output of the counter, the first, second and third inputs of the MOO are designed to supply clock signals CLKX, CLKX6, CLKY, respectively, the first group output of the MOO is connected to the first group input of the seventh multiplexer, the group output of which is connected to the group input of the third RAM, the second group output The MOO is connected to the first group input of the MK, the third group output of the MOO is connected to the second group input of the MK, the fourth group output of the MOO is connected to the third group input of the MK, the output of the MOO is connected to the third input of OR to the third MK input, the fourth input of the OR element is connected to the MK output, the second group MK output is connected to the third group input of the first multiplexer, the third MK group output is connected to the second group input of the fifth multiplexer, a threshold value is applied to the fourth group input of MK P, which determines the minimum number of pixels in the object, the fifth group input MK is connected to the third group output of the first demultiplexer, the first and second MK inputs are designed to supply a clock signal CLKW and CLKZ, respectively, the constant 0 is applied to the second input of the second multiplexer, the group output of the counter is connected to the fourth group input of the first multiplexer, the group input of the second multiplexer, the third group input of the third multiplexer, the fifth group input of the fourth multiplexer, the third group input of the fifth multiplexer, to the second group input of the sixth multiplexer, as well as to the second group inputs of the first demultiplexer and second demultiplexer, to the second, third, fourth input The fourth multiplexer is supplied with the constant 0, while the first multiplexer provides a signal from its first group input to its group output with a value of “0” at its fourth group input, from its second group input with a value of “1”, from its third group input - with a value of "3", the second multiplexer ensures the passage of a signal from its first group input to its group output with a value of "0" on its third group input, from its second group input - with a value “3”, the third multiplexer provides a signal from its first group input to its group output with a value of “0” at its third group input, from its second group input with a value of “1”, the fourth multiplexer provides a signal from its first group entering your group output with a value of “0” at its fifth group input, from your second group input with a value of “1”, from your third group input with a value of “2”, from your fourth group input with a value of and “3”, the fifth multiplexer provides a signal from its first group input to its group output with a value of “0” at its third group input, from its second group input with a value of “3”, the sixth multiplexer provides a signal from its first group input to its group output with a value of “0” at its second group input, the first demultiplexer provides a signal from its group input to the first group output with a value of “0” at its second group input, pr and a value of “1” to its second group output, with a value of “3” to its third group output, the second demultiplexer provides a signal from its group input to its group output with a value of “1” at its second group input, the seventh multiplexer provides a signal from its first group input to its group output with a value of “0” at its input, and from the second group input with a value of “1”.

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