RU2327200C1 - Random sequences generator - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: random sequences generator relates to computing processes, in particular, to discrete sequences generators and may be used in digital computers, TV, telecommunication systems, in generation of the orthogonal address sequences, as well as in the data protection systems. The said generator consists of the clock pulse generator, NO-component, n-digit counter, two AND-components, one shift register, function number register and trigger. The generator incorporates the units of generation of producing sequence, the key and the module 2 adder.

EFFECT: wider functions of the Wolsch function generator thanks to possibility of generation of random sequences.

2 cl, 2 dwg, 3 tbl

Description

The invention relates to computer technology, in particular to discrete sequence generators, and can be used in digital computing devices, television, telecommunication systems in the formation of orthogonal address sequences, as well as in information protection systems.

A known Walsh function generator containing a master oscillator, a shift register, a function number register, an element NOT, an AND element, and a trigger, the output of the function number register being connected to a parallel information register of the shift register, the output of the master oscillator connected to the clock input of the shift register and to the input of the element NOT, the output of the element NOT and the serial output of the shift register through the AND element are connected to the counting input of the trigger (see USSR author's certificate No. 1076892, class G06F 1/02, 1982).

However, this generator has significant complexity due to the large number of bits in the shift register used (2n-1 for 2n generated Walsh functions), since each bit of the shift register is a trigger.

Closest to the technical nature of the claimed invention is a Walsh function generator containing a master oscillator, an element NOT, a shift register, a register of a function number, an element AND, a trigger, an n-bit counter and an additional element And (see RF patent No. 2275683, cl. G06G 7/26, 2006).

The disadvantage of this device is its limited functionality, namely the lack of the possibility of forming derived sequences based on Walsh functions.

The purpose of the invention is the expansion of the functionality of the generator of Walsh functions by providing the possibility of forming derivative sequences.

The invention consists in the implementation of the following method of forming derived sequences.

It is known that Walsh functions (or sequences), possessing the property of mutual orthogonality for all sequences constructed according to a single algorithmic rule (that is, included in one ensemble of sequences), at the same time, have extremely unsatisfactory autocorrelation properties, which makes their use in modern telecommunication systems.

Improvements in the autocorrelation properties of Walsh sequences can be achieved by forming derived sequences on their basis. For this, the Walsh sequences of one ensemble must be symbolically combined with a generating sequence that is the same in duration with Walsh sequences, but with better autocorrelation properties. The indicated properties of the producing sequences correspond to characteristic discrete sequences (CDA) (see: Sverdlik MB Optimal discrete signals. M., "Soviet Radio", 1975).

A comparative characteristic of the maximum emissions of the periodic (PAKF) and aperiodic (AAKF) correlation functions of Walsh sequences of duration l = 16 and the sequences formed on the basis of the union of the Walsh and CDA sequences is shown in Table 1.

Type of CF Walsh sequences Derived Sequences R _max (m) R _min (m) m (x)

R _max (m) R _min (m) m (x)

PAKF one -one -0.039 0.533 0 -0.333 -0.071 0.02 AAKF 0.866 -0.944 -0.071 0.278 0.311 -0.421 -0.004 0,071

выбросов боковых лепестков корреляционных функций производные последовательности значительно превосходят соответствующие им последовательности Уолша.The table shows that the size of the maximum emissions R _max (m) of the correlation functions and the magnitude of the variance

emissions of the side lobes of the correlation functions, the derived sequences significantly exceed the corresponding Walsh sequences.

To generate characteristic discrete sequences in the proposed generator, the following algorithm is used:

1. The initial data for the formation of the CDA is the module p equal to the required duration of the sequence, which is a simple integer positive number, and also the antiderivative element θ over the field GF (p).

2. Two arrays of numbers are formed step by step: M (1) with dimension p and M (2) with dimension (p-1). The formation of the array M (1) consists in determining at each step the number of the element of the array by calculating the value (A + 1) mod p (where A = (A '× θ) mod p, A' is the value of the number A obtained in the previous calculation step , and at the first step A = 1) and assigning to this element a value equal to the number of the calculation step. The first element of the array M (1) is assigned the value "1". The formation of the array M (2) consists in assigning to the ith element of the array (i is the number of the calculation step) the value (A + 1) mod p obtained at this calculation step.

3. Upon completion of the formation of both arrays on their basis, CDA is formed step by step in accordance with the following rule:

H _i = (M (1) _j ) mod 2, where j = (M (2) _i ) +1) mod p,

where i is the calculation step number

Example

Let p = 7, θ = 5. In this case, it is necessary to perform (p-1) = 6 calculation steps to form the arrays M (1) and M (2). At each step, the value A = (A '* θ) mod p must be calculated. Since at the first step of calculation A = 1, then at the second A = (1 * 5) mod 7 = 5, at the third A = (5 * 5) mod 7 = 4, at the fourth A = 6, at the fifth A = 2 , on the sixth A = 3. Thus, the second element of the array M (1) will take the value 1, the sixth - 2, the fifth - 3, the seventh - 4, the third - 5, the fourth - 6. The first element of the array M (2) will take the value (A + 1) = 2 the second is 6, the third is 5, the fourth is 0, the fifth is 3, and the sixth is 4.

Thus, upon completion of the formation, the arrays M (1) and M (2) will have the following form:

M1 = [1 1 5 6 3 2 4], M2 = [2 6 5 0 3 4].

Further, in accordance with paragraph 3 of the algorithm, the desired numerical sequence is generated. The first element of the sequence H ₁ = (M (1) _{(M (2) 1) +1} ) mod 2 = (M (1) ₃ ) mod 2 = (5) mod 2 = 1. The second element of the sequence H ₁ = (4) mod 2 = 0. Similarly, the remaining elements of the sequence are formed.

Thus, the resulting sequence will look like:

H = 1 0 0 1 0 1.

After the generating sequence is formed, it is added modulo 2 with Walsh sequences symbolically. The result of the addition will be the desired derived sequences.

Figure 1 presents a diagram of a generator of derivative sequences, figure 2 is a diagram of a block forming a generating sequence.

The derivative sequence generator consists of a clock generator 1, a generating sequence generating unit 2, a key 3, an element NOT 4, an n-bit counter 5, a first element AND 6, a shift register 7, a register of a function number 8, a second element And 9, a trigger 10 , adder 11 modulo 2.

The output of the function number 8 register is connected to the parallel information input of the shift register 7, the output of the clock pulse generator 1 is connected to the input of the key 3, as well as to the third input of the generating sequence generating unit 2, the first output of which is connected to the control input of the key 3, the second output is connected to the second input of the adder 11 modulo 2, the output of the key 3 is connected to the clock input of the shift register 7 and to the input of the element NOT 4, the output of the element NOT 4 and the serial output of the shift register 7 through the element And 9 are connected to the counting input to trigger 10, the shift register 7 is closed into the ring by a feedback circuit through the And 6 element, the second input of which is connected to the output of the high-order bit of counter 5, the counting input of which is connected to the output of key 3.

In the initial position, the key 3 is open, and the values of the antiderivative element θ and module p are respectively supplied to the first and second inputs of the device. The senior bit of the n-bit counter 5 is set to a single state, and the remaining bits to zero, trigger 10 is set to a single state.

Before starting work, the code combination, which is a truncated code of the Walsh sequence number, is copied from register 8 of the function number to shift register 7.

The binary code of the Walsh sequence number to be recorded in shift register 7 is determined by the following tables:

a) for N = 4 (where N is the volume of the Walsh sequence system)

Table 1 Walsh sequence decimal number Walsh sequence binary number Walsh Sequence Number Binary Code 0 00

one 01 2
3 10
eleven Combinations written to shift register 7

b) for N = 8

table 2 Walsh sequence decimal number Walsh sequence binary number Walsh Sequence Number Binary Code 0 000

one 001 2 010 3 011 four one hundred 5 101 6
7 110
111 Combinations written to shift register 7

c) for N = 16

Table 3 Walsh sequence decimal number Walsh sequence binary number Walsh Sequence Number Binary Code 0 0000

one 0001 2 0010 3 UN four 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 eleven 1011 12 1100 13 1101 fourteen
fifteen 1110
1111 Combinations written to shift register 7

The process of generating derivative sequences begins with the start of a clock generator 1. From the output of the generator, the clock pulses are fed to the input of the counter 3 and to the third input of the unit 2 for generating the generating sequences.

The generating sequence generating unit 2 (FIG. 2) contains a control unit 12, a key 13, a control unit 14, a modulator 15, an OR element 16, a counter 17, a first ROM 18, a remainder generating unit 19, a first adder 20, a switching unit 21 , the second ROM 22, the block 23 of the formation of the remainder modulo 2, the second adder 24.

In the initial position, the values of the antiderivative element θ and module p, respectively, are supplied to the first and second inputs of the control unit 12, and these inputs are disconnected from the corresponding outputs of the block. The third output of the control unit 12 is used to transmit information about the value of the module and the change in the values of the module and the antiderivative element to the control unit.

The process of generating a generating sequence starts from the moment the first single clock pulse appears at the input of the key 13 and the first input of the control unit 14. In the initial position, the input of the key 13 is connected to the first output, so a single character from the first output of the key 13 is fed to the first input of the multiplier 15 modulo. Since at the first clock cycle, the remaining inputs of the multiplier 15 are not fed modulo the data, a single pulse is fed to the least significant bit of the output of the multiplier, from which it goes to the input of the first adder 20 as a binary code of the number “1”, and also to the feedback circuit. In the first adder 20, the value supplied to its input is increased by one by adding one to the least significant bit of the binary code of the number. From the output of the first adder 20, the resulting code of the number “2” is sent to the first input of the switching unit 21, the second input of which receives the value from the output of the counter 17. Since the clock pulse is transmitted from the first output of the key 13 to the counting input of the counter 17 , then at the output of the counter on the first clock cycle the value “1” will be generated. Considering that at the first clock cycle, the value of the number “2” is supplied to the first input of the switching unit 21, the value of the number “1” will be recorded in the second cell of the second ROM 22. The first cell of the second ROM 22 is always “1”.

From the output of the first adder 20, the resulting number code also goes to the first input of the residual generation unit 19. Since at the first step of operation the module code is not supplied to the second input of the residual block 19, the value of the number “2” from the output of the residual block 19 is fed to the input of the first ROM 18, where it is written into the first cell.

After the completion of the first clock pulse, the control unit 14 at its first output generates a signal for reconnecting the input of the key 13 from the first to the second output, and at the second output, a signal for connecting the inputs of the code recording of the antiderivative element and the module to the first and second outputs of the control unit 12, respectively. At the second and subsequent clock cycles, the clock read pulses are fed to the clock input of the multiplier 15 modulo, as well as through the OR element 16 to the counting input of the counter 17. At each clock pulse in the multiplier 15 modulo multiplication occurs (the value of which is fed to the fourth input of the multiplier ) the values generated in this block at the previous clock cycle and fed through the feedback circuit to the second input of the multiplier, to the value of the antiderivative element received at the third input of the multiplier.

The obtained value from the output of the multiplier 15 enters the feedback circuit and to the input of the first adder 20. After increasing by one, the obtained value from the output of the first adder 20 enters the first input of the switching unit 21, where it determines the cell address of the second ROM 22, into which the value is written, coming from the counter 17, as well as to the first input of the residual formation unit 19, the second input of which receives the value of the module. From the output of the residual formation block 19, the obtained value is fed to the input of the first ROM 18, where it is recorded in the i-th cell (i-tick number).

Thus, at each step, starting from the second, in the first ROM 18, in each cell, starting from the second, the value of the remainder modulo p of the value of the number A formed in the multiplier 15 modulo and increased by one, that is, ( A + 1) mod p, and in the (A + 1) -th cell of the second ROM 22 the value i will be written (i is the measure number).

Upon completion of the (p-1) -th cycle (p - module), the control unit 14 at the first output will generate a signal for connecting the input of the key 13 to the third output of this unit, and at the second output - a signal for disconnecting the first and second outputs of the control unit 12. At the third output of the control unit 14, a signal will be generated to turn on the key 3 and to supply clock pulses to the generator elements responsible for the formation of Walsh sequences.

Under the influence of clock pulses coming from the output of the key 3 to the clock input of the shift register 7, the information recorded in it is shifted and fed to one of the inputs of the second element And 9, the second input of which receives an inverted clock pulse. Information from the output of the shift register 7 also goes to one of the inputs of the first element And 6, the second input of which receives the unit potential from the output of the highest order of the counter 5. Information from the output of the first element And 6 will go to the input of the shift register 7 until the high order of counter 5 will be in a single state. Since counter 5 has n digits, and before starting its work, “1” was written in its highest digit, this will happen after 2 ^n-1 clock cycles of generator 1. Thus, in the shift register 7, feedback circuits are written (2 ^{n -1} -1) characters that came out of it, and, therefore, they will re-enter the input of the second element And 9, that is, the input of the second element And 9 will not receive the truncated, but the full code of the Walsh sequence number.

The voltage at the output of the second element And 9 is gated, and for each binary interval of minimum duration there is one gate, and the duration of each gate is equal to half the duration of the clock interval. The signals from the input of the second element And 9 are received at the counting input of the trigger 10, previously set to a single state. The moments of occurrence of logical units at the output of the second element And 9 correspond to the moments of changes in sign of the generated Walsh sequence, therefore, at the output of trigger 10, the corresponding Walsh sequence is formed. Elements of the Walsh sequence from the output of the trigger 10 are supplied to the first input of the adder 11 modulo 2.

At the same time, in block 2 for generating the generating sequence, clock pulses from the third output of key 13 will be supplied to the clock inputs of both ROMs. Under their action, the value of each cell of the first ROM 18 in turn, starting from the first cell, will be fed to the output of the first ROM 18, increased by one in the second adder 24 and fed to the second input of the second ROM 22, where it will determine the address of the cell whose value on this the clock cycle should go to the output of the second ROM 22. This value will go to the input of the block 23 of the formation of residues modulo 2. From the output of this block, which is the second output of the block 2 of the formation of the generating sequence, the characters "1" or "0" will come in and the second input of the adder 11, where modulo 2 will add up with the characters of the Walsh sequence. At the output of the adder 11 modulo 2 elements of the derived sequence will be formed.

In the event of a change in the duration of the producing sequence (module p) or the order of its formation (antiderivative element θ), a signal will be generated at the third output of the control unit 12, which will be transmitted to the second input of the control unit 14. In this case, the block 14 at the first input will generate a signal for connecting the input of the key 13 to the first output, at the third input - a signal to turn off the key 3, at the fourth output - a signal to reset the counter 17, after which the derivative sequence is formed in accordance with the above algorithm.

Claims (2)

1. A derivative sequence generator comprising a clock, an element NOT, an n-bit counter, a first and second element AND, a shift register, a function number register, a trigger, the output of the function number register being connected to a parallel information input of the shift register, the output of the element NOT and the serial output of the shift register through the And element is connected to the counting input of the trigger, the shift register is closed to the ring by a feedback circuit through the And element, the second input of which is connected to the output of the senior discharge A device, characterized in that a generating sequence generating unit, a key and an adder modulo 2 are inserted into it, and the output of the clock pulse generator is connected to the key input, as well as to the third input of the generating sequence generating unit, the first output of which is connected to the control input of the key, the second output is to the second input of the adder modulo 2, the key output is connected to the clock input of the shift register, to the input of the element NOT and to the counter input of the counter, the first input of the generating unit lnosti connected to an input record of a primitive element of the code, the second input forming unit generating a sequence is connected to an input of the recording unit of code latch output is connected to the first input of the adder modulo 2, whose output is the output of the generator. 2. The device according to claim 1, characterized in that the generating sequence generating unit comprises a control unit, a key, a control unit, a modulator, an OR element, a counter, a first and second ROM, a remainder forming unit, a first and second adder, a switching unit , the remainder forming unit modulo 2, wherein the first input of the generating sequence generating unit is connected to the first input of the control unit, the second input of the generating sequence generating unit is connected to the second input of the control unit, third input the generating sequence generating unit is connected to the key input and the first input of the control unit, to the second input of which the third output of the control unit is connected, the first output of the control unit is connected to the third input of the multiplier modulo, the second output of the control unit is connected to the fourth input of the multiplier modulo and to the second the input of the residual formation unit, the first output of the control unit is connected to the control input of the key, the second output of the control unit is connected to the third input of the control unit, the third output of the unit board is the first output of the generating sequence generation unit, the fourth output of the control unit is connected to the counter zeroing input, the first key output is connected to the first input of the multiplier modulo and to the first input of the OR element, the second output of the key is connected to the clock input of the multiplier modulo and to the second input OR element, the output of which is connected to the counting input of the counter, the third output of the key is connected to the clock inputs of both ROMs, the output of the multiplier is connected modulo to the input of the first adder and to the second modulator input of the multiplier, the output of the first adder is connected to the first input of the switching unit, the counter output is connected to the second input of it, as well as to the first input of the residual formation unit, the output of the switching unit is connected to the first input of the second ROM, the output of the residual formation unit is connected to the input of the first ROM, the output of the first ROM is connected to the input of the second adder, the output of the second adder is connected to the second input of the second ROM, the output of the second ROM is connected to the input of the remainder block modulo 2, the output of this block ka is the second output of the generating sequence generating unit.

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